SI9123DQ-E3
更新时间：2024-10-20 19:03:17
品牌：VISHAY
描述：Switching Regulator/Controller, Voltage-mode, 500kHz Switching Freq-Max, PDSO16
概述
规格参数
数据手册SI9123DQ-E3 概述
Switching Regulator/Controller, Voltage-mode, 500kHz Switching Freq-Max, PDSO16 开关式稳压器或控制器
SI9123DQ-E3 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Active |
| 包装说明： | TSSOP, TSSOP16,.25 | Reach Compliance Code： | unknown |
| 风险等级： | 5.77 | 控制模式： | VOLTAGE-MODE |
| JESD-30 代码： | R-PDSO-G16 | JESD-609代码： | e3 |
| 湿度敏感等级： | 1 | 端子数量： | 16 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | TSSOP |
| 封装等效代码： | TSSOP16,.25 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | 认证状态： | Not Qualified |
| 子类别： | Switching Regulator or Controllers | 表面贴装： | YES |
| 最大切换频率： | 500 kHz | 温度等级： | INDUSTRIAL |
| 端子面层： | Matte Tin (Sn) | 端子形式： | GULL WING |
| 端子节距： | 0.635 mm | 端子位置： | DUAL |
| Base Number Matches： | 1 |
SI9123DQ-E3 数据手册
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PDF下载Si9123
Vishay Siliconix
500-kHz Half-Bridge DC-DC Converter With
Integrated Secondary Synchronous Rectification Control
FEATURES
D 12-V to 72-V Input Voltage Range
D Hiccup Current Control During Shorted Load
D Low Input Voltage Detection
D Compatible with ETSI 300 132-2 100 V, 100-ms
Transients
D Programmable Soft-Start Function
D Programmable Oscillator Frequency
D Over Temperature Protection
D Integrated Half-Bridge 1-A Primary Drivers
D Secondary Synchronous Rectifier Control
D Voltage Mode Control
APPLICATIONS
D Voltage Feedforward Compensation
D High Voltage Pre-Regulator Operates During Start-Up
D Current Sensing On Low-Side Primary Device
D Network Cards
D Power Supply Modules
DESCRIPTION
Si9123 is a dedicated half-bridge controller IC ideally suited to
fixed telecom dc-dc converter applications where high
efficiency is required at low output voltages (e.g. <3.3 V).
Designed to operate within the voltage range of 12-72 V and
withstand 100 V, 100 ms transients, the IC is capable of
controlling and directly driving both primary side MOSFET
switches of a half-bridge circuit.
very low on-resistance of the secondary MOSFETs, a
significant increase in the efficiency can be achieved as
compared with conventional Schottky diodes for today’s low
output voltages. On-chip control of the dead time delays
between the primary and secondary signals keep efficiencies
high and prevents accidental destruction of the power
transformer or wasted energy from self timed approaches.
Such a system can achieve conversion efficiencies well in
excess of 90%.
High conversion efficiency is achieved by use of synchronous
rectifying MOSFET transistors in the secondary. Due to the
FUNCTIONAL BLOCK DIAGRAM
V
INEXT
+
C
D
VIN1
−
R
C
EXT
D
BOOST
1
V
IN
To
CC
Power
Transformer
V
BST
L
X
V
CC
Pre-Reg
H
CV
CC
(High)
V
OUT
EP
Voltage
Control
Primary
Drivers
Voltage
Information
SS
C
LOAD
R
LOAD
D
L
Soft-
Start
PWM
(Low)
C
SS
R
S
CS2
CS1
Current
Control
Secondary
Drivers
Pulse
Transformer
SEC_SYNC
Si9123
Half-Bridge
Synchronous
Controller
Driver
Logic
Error
Amp
Opto
1.215 V
Figure 1.
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
1
Si9123
Vishay Siliconix
DESCRIPTION (CONTINUED)
Si9123 has advanced current monitoring circuitry to permit the
user to set the maximum current in the primary circuit. Such a
feature acts as protection against output shorts. Upon sensing
an overload condition, the converter is shut off for a period of
time and then soft-start cycle is re-initiated, achieving hiccup
mode operation. Current sensing is by means of a sense
resistor on the low-side primary device. An integrated
over−temperature shutdown circuit also protects the system.
circuit permits direct operation from input voltage with only one
series resistor during startup. The pre-regulator automatically
disconnects from the input supply when the output voltage is
established by means of a feedback winding from the filter
inductor.
Si9123 is available in both standard and lead (Pb)-free
TSSOP-16 pin packages. In order to satisfy the stringent
ambient temperature requirements, Si9123 is rated to handle
the industrial temperature range of –40 to 85_C.
The 100-V depletion mode MOSFET integrated pre-regulator
DETAILED BLOCK DIAGRAM
V
IN
V
CC
R
OSC
V
REF
V
UVLO
Pre-Regulator
BST
+
−
Level
Shift
D
H
8.8 V
L
X
High-Side
Driver
V
INDET
V
FF
V
V
UV
+
OSC
−
V
REF
Ramp
Error Amplifier
V
V
CC
SD
+
−
2.2 R
D
550 mV
L
Low-Side
Driver
R
PWM
Comparator
EP
−
+
+
−
V
CC
1.65 V
Driver
Control
and
I
4I
CC
SS
Timing
SEC_SYNC
PGND
Gain
SEC_SYNC
Driver
CS2
CS1
Hiccup
Mode Start
+
−
Peak DET
OTP
Si9123
Over Current Protection
GND
Figure 2.
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
2
Si9123
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (ALL VOLTAGES REFERENCED TO GND = 0 V)
V
V
V
V
V
V
V
(Continuous) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V
(100 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
SEC_SYNC Drive Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . . 5 mA
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150_C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C
IN
IN
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 V
CC
BST
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 V
a
Power Dissipation
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 V
LX
TSSOP-16 (T = 25_C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 W
A
− V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
BST
LX
Thermal Impedance (ꢀ
)
JA
b
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100_C/W
, R
REF OSC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
CC
Notes
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
CC
a. Device mounted on JEDEC compliant 1S2P (4-layer) test board..
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
b. Derate −10 mW/_C above 25_C.
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE (ALL VOLTAGES REFERENCED TO GND = 0 V)
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 to 72 V
C
C
C
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 nF
IN
SS
ꢀ
C
C
. . . . . . . . . . . . . . . . . . . . . . . 100 ꢁ F/ESR ꢁ 100 mꢂ and 0.1 ꢁ F
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 ꢁ F
REF
VIN1
VIN2
V
CC
Operating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 to 13.2 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 ꢁ F
BOOST
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ꢁ F
LOAD
CV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 ꢁ F
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 to 600 kHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 to 72 kꢂ
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 kꢂ
CC
f
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V −0. 3 V
CC
OSC
R
R
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
CC
OSC
Reference Voltage Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 mA
EXT
a
SPECIFICATIONS
Limits
Test Conditions Unless Specified
−40 to 85_C
CS1 = CS2 = 0 V, f
= 500 kHz, V = 48 V
IN
NOM
V
INDET
= 4.8 V; 10 V ꢁ V ꢁ 13.2 V
Parameter
Symbol
Minb
Typc
Maxb
Unit
CC
Reference (3.3 V)
Output Voltage
V
V
CC
= 12 V, 25_C Load = 0 mA
3.2
3.3
3.4
−50
−75
V
REF
Short Circuit Current
Load Regulation
I
V
REF
= 0 V
mA
mV
dB
SREF
dVr/dlr
PSRR
I
= 0 to −2.5 mA
−30
REF
Power Supply Rejection
@ 100Hz
60
Oscillator
Accuracy (1% R
Max Frequency
)
R
OSC
= 30 kꢂ, f = 500 kHz
NOM
−20
−40
20
%
OSC
F
R
OSC
= 24 kꢂ
600
kHz
MAX
Error Amplifier
Input Bias Current
Gain
I
V
EP
= 0 V
−15
ꢁ A
BIAS
A
V
−2.2
5
Bandwidth
BW
MHz
dB
Power Supply Rejection
Slew Rate
PSRR
SR
@ 100Hz
60
0.5
V/ꢁ s
Current Sense Amplifier
Input Voltage CM Range
Input Amplifier Gain
V
V
− GND, V − GND
CS2
ꢂ150
17.5
5
mV
dB
CM
CS1
A
VOL
Input Amplifier Bandwidth
Input Amplifier Offset Voltage
BW
MHz
V
ꢂ5
150
−50
OS
V
CC
Hiccup Threshold
V
Increase CS2 Until SS Hiccups
Decrease CS2 Until SS Clamps
mV
THCUP
Hysteresis
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
3
Si9123
Vishay Siliconix
a
SPECIFICATIONS
Limits
Test Conditions Unless Specified
−40 to 85_C
CS1 = CS2 = 0 V, f
= 500 kHz, V = 48 V
IN
NOM
V
INDET
= 4.8 V; 10 V ꢁ V ꢁ 13.2 V
CC
Parameter
Symbol
Minb
Typc
Maxb
Unit
PWM Operation
D
V
= 0 V
90
92
95
MAX
EP
e
Duty Cycle
f
= 500 kHz
%
OSC
D
V
= 1.85 V
ꢃ
1
5
MIN
EP
Pre-Regulator
Input Voltage (Continuous)
Input Leakage Current
V
I
= 10 ꢁ A
72
10
V
IN
IN
I
V
= 72 V, V ꢄ V
IN CC REG
LKG
ꢁ A
I
I
V
IN
= 72 V, V
ꢃ
V
86
4
200
6.5
REG1
REG2
INDET
ꢄ V
INDET REF
SD
Regulator Bias Current
V
IN
= 72 V, V
mA
V
Pre-Regulator Drive Capacility
I
V
ꢃ V
REG
20
7.4
8.5
START
CC
9.1
9.1
9.2
8.6
8.6
0.5
10.4
9.7
V
V
ꢄ V
REF
REG1
INDET
V
Pre-Regulator Turn Off
CC
T
= 25_C
= 25_C
A
Threshold Voltage
V
V
V
= 0 V
REG2
INDET
7.15
8.1
9.8
9.3
d
Undervoltage Lockout
V
CC
Rising
UVLO
T
A
V
UVLO
Hysteresis
V
UVLOHYS
Soft-Start
I
I
0
ꢃ V ꢃ 2 V
be
12
60
20
100
8.1
28
SS1
SS
Soft-Start Current Output
ꢁ
A
2 V ꢃ V ꢃ 4.8 V
200
8.85
SS2
be
SS
Soft-Start Completion Voltage
V
Normal Operation
7.35
V
SS_COMP
Shutdown
V
Shutdown FN
Hysteresis
V
V
Rising
INDET
350
550
200
720
INDET
INDET
SD
mV
V
V
V
INDET
VINDET Input Threshold Voltages
V
− V Under Voltage
V
UV
V
INDET
Rising
3.13
3.3
0.3
3.46
INDET
INDET
IN
V
Hysteresis
V
INDET
Over Temperature Protection
Activating Temperature
T Increasing
160
130
J
_C
ꢁ A
De-Activating Temperature
T Decreasing
J
Converter Supply Current (VCC
)
Shutdown
I
I
I
I
Shutdown, V
= 0 V
50
1.8
3.0
140
2.8
350
3.8
6.8
CC1
CC2
CC3
CC4
INDET
Switching Disabled
Switching w/o Load
V
ꢃ V
INDET REF
V
ꢄ V , f = 500 kHz
REF NOM
4.4
INDET
mA
Switching with C
V
CC
= 12 V, C = C = 3 nF, C
= 0.3 nF
15.2
LOAD
DH
DL
SEC_SYNC
CS2 − CS1 = 200 mV, C = C = 3 nF
DL
DH
V
CC
Hiccup Current
I
4.3
HCUP
C
= 0.3 nF
SEC_SYNC
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
4
Si9123
Vishay Siliconix
a
SPECIFICATIONS
Limits
Test Conditions Unless Specified
−40 to 85_C
CS1 = CS2 = 0 V, f
= 500 kHz, V = 48 V
IN
NOM
V
INDET
= 4.8 V; 10 V ꢁ V ꢁ 13.2 V
Parameter
Symbol
Minb
Typc
Maxb
Unit
CC
Output MOSFET DH Driver (High-Side)
V
−
BST
0.3
Output High Voltage
V
Sourcing 10 mA
Sinking 10 mA
OH
V
V
+
LX
Output Low Voltage
Boost Current
V
OL
0.3
I
0.8
1.55
−0.4
−1.0
1.0
2.4
BST
V
V
= 48 V, V
= 48 V, V
= V + V
mA
A
LX
BST
LX
CC
L
X
Current
I
−0.8
−0.1
LX
SOURCE
Peak Output Source
Peak Output Sink
Rise Time
I
−0.75
= V + V
LX
BST
LX
CC
I
0.75
SINK
t
18
28
28
r
T
A
= 25_C, C = 3 nF, V = 12 V, 20 − 80%
ns
DH
CC
Fall Time
t
f
22
Output MOSFET DL Driver (Low-Side)
V
−
CC
Output High Voltage
V
Sourcing 10 mA
Sinking 10 mA
OH
0.3
V
Output Low Voltage
Peak Output Source
Peak Output Sink
Rise Time
V
0.3
OL
I
−1.0
1.0
19
−0.75
SOURCE
V
CC
= 12 V
A
I
0.75
SINK
t
28
28
r
T
A
= 25_C, C = 3 nF, V = 12 V, 20 − 80%
ns
DL
CC
Fall Time
t
f
24
Secondary_Synchronous Driver
V
−
CC
Output High Voltage
Output Low Voltage
V
Sourcing 10 mA
Sinking 10 mA
OH
0.4
V
V
0.4
110
95
OL
d1
d3
d2
d4
t
t
t
t
90
75
Leading Edge Delays
Trailing Edge Delays
T
A
= 25_C, V = 12 V, L = 48 V, See Figure 3
CC
X
ns
90
110
95
C
DH
= C = 3 nF, C = 0.3 nF
SGC_SYNC
DL
65
Peak Output Source
Peak Output Sink
Rise Time
I
−100
100
16
SOURCE
V
= 12 V
mA
ns
CC
I
SINK
t
r
28
28
T
A
= 25_C, C
= 3 nF, V = 12 V, 20 − 80%
SEC_SYNC CC
Fall Time
t
f
17
Voltage Mode
Error Amplifier
Current Mode
Current Amplifier
Notes
Input to high-side switch off
Input to low-side switch off
ꢃ200
ꢃ200
t
d1DH
d2DL
ns
ns
t
Input to high-side switch off
Input to low-side switch off
ꢃ200
ꢃ200
t
d3DH
t
d4DL
a. Refer to PROCESS OPTION FLOWCHART for additional information.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (−40_ to 85_C).
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at V = 12 V unless otherwise noted.
CC
d.
V
tracks V
by a diode drop
H
UVLO
REG1
e. Measured on D or D outputs.
L
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
5
Si9123
Vishay Siliconix
TIMING DIAGRAMS FOR MOS DRIVERS
V
CC
SEC_SYNC
GND
V
CC
D
L
GND
V
BST
V
MID
D
H
GND
Time
D
H
BST
50%
L
X
VL
X
D , L
D , L
H X
H
X
V
MID
SEC_SYNC
D , L
SEC_SYNC
50%
V
CC
50%
SEC_SYNC
H
X
GND
Leading
Trailing
t
d3
t
d4
D
L
50%
GND
Leading
Trailing
t
d1
t
d2
Figure 3.
Hiccup
Time Out
Soft
Start
Over Current
Detected
VOLTS
SS
2 V
be
GND
Time
t
2
t
1
Figure 4.
Soft-Start, Hiccup Mode Operation
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
6
Si9123
Vishay Siliconix
PIN CONFIGURATION
Si9123DQ (TSSOP-16)
ORDERING INFORMATION
Part Number
Temperature Range
Package
V
BST
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
V
CC
D
H
Si9123DQ-T1
Si9123DQ-T1—E3
Si9123DQ
Tape and Reel
Bulk
V
L
X
REF
−40 to 85_C
GND
D
L
R
PGND
SEC_SYNC
SS
OSC
EP
V
INDET
CS1
CS2
Top View
PIN DESCRIPTION
Pin Number
Name
Function
1
2
3
4
5
6
V
Input supply voltage for the start-up circuit.
Supply voltage for internal circuitry
IN
V
CC
V
REF
3.3-V reference, decoupled with 1-ꢁ F capacitor
Ground
GND
R
OSC
External resistor connection to oscillator
Voltage control input
EP
V
under voltage detect and shutdown function input. Shuts down or disables switching when V
falls below
IN
INDET
7
V
INDET
preset threshold voltages and provides the feed forward voltage.
8
CS1
CS2
Current limit amplifier negative input
9
Current limit amplifier positive input
10
11
12
13
14
15
16
SS
Soft-Start control − external capacitor connection
Secondary side timing signal
SEC_SYNC
PGND
Power ground.
D
L
Low-side gate drive signal – primary
L
X
High-side source and transformer connection node
High-side gate drive signal – primary
D
H
BST
Bootstrap voltage to drive the high-side n-channel MOSFET switch
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
7
Si9123
Vishay Siliconix
DETAILED FUNCTIONAL BLOCK DIAGRAM
V
CC
V
IN
Pre-Regulator
+
−
Reference
Voltage
3.3 V
V
REG
9.1 V
V
REF
V
REF
9.1 V
V
UVLO
+
+
−
−
V
V
UV
High-Side
Primary
Driver
V
INDET
V
REF
8.6 V
SD
BST
+
−
Voltage
Feedforward
160_C Temp
High Voltage
Interface
D
H
Protection
550 mV
L
X
V
SD
V
V
UV UVLO
R
OSC
OSC
OTP
Oscillator
Clock
Clock
Logic
Low-Side
Primary
Driver
V
CC
132 kꢂ
D
L
60 kꢂ
EP
−
+
−
+
Logic
V
REF
/2
PGND
PWM
Generator
Current
Control
Secondary
Synchronous
Driver
Gain
CS2
CS1
V
CC
+
−
SEC_SYNC
100 mV
Blanking
V
CC
80 ꢁ A
20 ꢁ A
SS
SS Control
GND
SS Enable
Figure 5.
DETAILED OPERATION
Start-Up
When VINEXTrises above 0 V, the internal pre-regulator begins
charging the external capacitor on VCC. The charging current
is limited to typically 40 mA by the internal 100 V DMOS device.
When VCC exceeds the UVLO voltage of 8.8 V, a soft-start
cycle of the controller is initiated to provide power to the
secondary. Once switching commences, the internal gate
drivers for the primary side switching transistors and the drive
current into the secondary synchronization driver draw
additional current from the VCC capacitor and pre-regulator.
A detailed Functional Block Diagram is shown in Figure 5 with
additional detail of the pre-regulator shown in Figure 6. The
pre-regulator circuit acts as a linear regulator to provide VCC
directly from the VINEXT supply until the VCC supply voltage
between 10 V to 13.2 V can be sustained from an auxiliary
winding from the secondary of the power inductor.
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
8
Si9123
Vishay Siliconix
The pre-regulator will remain on until VCC equals VREG but
between VUVLO and VREG, excessive current may result in
VCC falling below VUVLOand stopping soft-start operation. This
situation is avoided by the hysteresis between VREG and
VUVLO and correct sizing of the VCC capacitor, bootstrap
capacitor, the soft-start capacitor, the primary MOSFET gate
driving charge, and load on the SEC_SYNC output. The value
of the VCC capacitor should be chosen to be capable of
maintaining soft-start operation with VCCabove VUVLO until the
clamp turns on at 14.5 V to shunt excessive current to GND.
In systems where operation is directly from a 12 V supply,
VINEXT and VCC can be connected to the 12 V bus.
The soft-start circuit is designed for the dc-dc converter to start
up in an orderly manner and reduce component stress.
Soft-start is achieved by ramping the maximum attainable duty
cycle during the soft-start time. The duty cycle is increased
from zero to the final value at the rate set by an external
capacitor, CSS as shown in Figure 7. The hiccup time is set by
an internal 20 µA current source charging CSS from 0 V to
2 Vbe, at which point switching begins. Then a 100 µA charging
current is applied to CSS to charge from 2 Vbe to the final value
controlling the duty cycle as it rises. In the event of UVLO,
shutdown or over current, the SS pin will be held low (<1 V)
disabling driver switching. A longer soft-start time may be
needed for highly capacitive loads and high peak-output
current applications. In the event of an over current condition
being detected, the soft-start pin will be pulled low and the
cycle will start again performing a hiccup as shown in
Figure 4. The hiccup off-time, t1, is given by:
V
CC current can be supplied from the external circuit (e.g., via
an auxiliary winding on the secondary inductor).
V
INEXT
R
EXT
= 1.4 kꢂ
Auxillary
V
IN
V
CC
HV
DMOS
V
CC
C
VCC
1.2 V
20 ꢁ A
4.7 ꢁ F
t1 ꢅ CSS
ꢆ
14.5 V
V
REF
GND
The soft-start time t2 is can be estimated as:
Figure 6.
High-Voltage Pre-Regulator Circuit
ꢇC
ꢆ nꢈ
K ꢆ 100 ꢁ A
SS ꢆ VOUT
(
t2
ꢅ
)
The feedback voltage from the output of the auxiliary winding
must sustain VCC above VREG to fully disconnect the
pre-regulator, isolating VCC from VINEXT. VCC is then
maintained above VREG for the duration of operation. In the
event of an over voltage condition on VCC, an internal voltage
where VOUT is the output of the converter, and n is the turns
ratio of the primary to each secondary winding, and K is the
ratio of the resistive divider from VINEXT to VINDET (typically
10/1).
V
CC
+
4I
GM
Peak Detect
−
I
SS Control
SS Enable
CS1
CS2
−
AV
A
ꢆ150 mV
ꢆ100 mV
V
SS
+
Blank
C
SS
A
V
Figure 7.
Current-Sense and Soft-Start Circuit Block Diagram
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
9
Si9123
Vishay Siliconix
Care should be taken to control the operating time using the
internal pre-regulator to prevent excessive power dissipation in
the IC. The use of an external dropping resistor connected in
series with the VIN pin to drop the voltage during start up is
recommended. The value of R EXT is selected to drop the input
voltage to the IC under worst case conditions thereby
dissipating power in the resistor, instead of the IC. If the supply
output is shorted and the auxiliary winding does not provide the
VCC current, then continuous soft-start cycles will occur. The
average power in the IC during start-up where the hiccup
operation would be performed continuously is given by:
Voltage feed-forward is implemented by taking the attenuated
VINEXT signal at VINDET to directly modulate the duty cycle.
This relationship is shown in the Typical Characteristic section,
Duty Cycle vs. VINDET, page 12. The response time to line
transients is very short since the PWM duty cycle is changed
directly without having to go through the error amplifier
feedback loop. At start-up, i.e., once VCC is greater than
VUVLO, switching is initiated under soft-start control which
increases the maximum attainable switch on-time linearly over
the soft-start period. Start-up from a VINDET power down,
over-temperature, or over current is also initiated under
soft-start control.
ꢊt I
ꢇI
ꢈꢌ
CC2 ꢋ t2 CC4 ꢋ ISEC_SYNC
1
Half-Bridge and Synchronous Rectification Timing
Sequence
(
)
Power IC ꢉ VIN
ꢆ
ꢇ
ꢈ
t1 ꢋ t2
The PWM signal generated within the IC controls the low and
high-side bridge drivers on alternate cycles. A period of
inactivity always results after initiation of the soft-start cycle
until the soft-start voltage reaches approximately 2 Vbe and
PWM generated switching begins. The first bridge driver to
switch is always the low-side, DL as this allows charging of the
high-side boost capacitor. The timing and coordination of the
drives to the primary and secondary stages is very important
and the relationships are shown in Figure 3. It is essential to
avoid the situation where both of the secondary MOSFETs are
on when either the high or the low-side switch are active. In this
situation the transformer would effectively be presented with a
short across the output. The SEC_SYNC timing signal is set
to be ahead of the primary drive outputs by 50 − 80 ns.
ꢊt I
ꢇI
ꢈꢌ
CC2 ꢋ t2 CC4 ꢋ ISEC_SYNC
1
ꢇ
ꢈ
ꢇ
ꢈ
Power REXT ꢉ VINEXT ꢍ VIN
ꢆ
ꢇ
ꢈ
t1 ꢋ t2
where ICC2 is the non-switching supply current, ICC4 is the
supply current while switching, ISEC_SYNC is the average
current out of the SEC_SYNC pin, and t1 and t2 are defined in
Figure 4.
After the feedback voltage from the secondary overrides the
internal pre−regulator, no current flows through REXT
example of the feedback circuitry is shown in Figure 15.
. An
The SS pin has a predictable +1.25-mV/_C temperature
coefficient and can be used to continuously monitor the
junction temperature of the IC for a given power dissipation.
Primary High- and Low-Side MOSFET Drivers
The drive voltage for the low-side MOSFET switch is provided
directly from the VCC supply. The high-side MOSFET however
requires the gate voltage to be enhanced above VIN. This is
achieved by bootstrapping the VCC voltage onto the LX voltage
(the high-side MOSFET source). In order to provide the
bootstrapping an external diode and capacitor are required as
shown on the application schematic. The capacitor will charge
up after the low-side driver has turned on. The driver signals
DH and DL are shown in Figure 3. The drive currents for the
primary side MOSFETs is supplied from the VCC supply and
can influence start up conditions.
Reference
The reference voltage of Si9123 is set at 3.3 V. The reference
voltage should be de-coupled externally with a 0.1 ꢁF
capacitor and has 50-mA source capability. The REF pin
voltage is 0 V in shutdown mode.
Voltage Mode PWM Operation
Under normal load conditions, the IC operates in voltage mode
and generates a fixed frequency pulse-width modulated signal
to the drivers. Duty cycle is controlled over a wide range to
maintain the output voltage under line and load variation.
Voltage feed-forward is also included to improve line regulation
and transient response. In the half-bridge topology requiring
isolation between output and input, the reference voltage and
error amplifier are supplied externally, usually on the
secondary side.
Secondary Synchronization Driver
The secondary side MOSFETs are driven by the SEC_SYNC
output via a pulse transformer and gate driver circuits. The
time relationships are shown in Figure 3. Logic circuitry on the
secondary side is required to align the synchronous rectifier
gate drive with the primary drive. The current supplied to the
pulse transformer is drawn from VCC
.
The output error signal is usually passed to the power
converter through an opto-coupling device for isolation. The
error information enters the IC via pin EP and where 0 V results
in the maximum duty cycle, whilst 2 V represents minimum
duty cycle. The EP error signal is gained up by -2.2X via an
inverting amplifier and compared against the internal ramp
generator. The relationship between Duty Cycle and VEP is
shown in the Typical Characteristic section, Duty Cycle vs. VEP
25_C, page 12.
Oscillator
The oscillator is designed to operate at a frequencies up to
500 kHz. The 500-kHz operating frequency allows the
converter to minimize the inductor and capacitor size,
improving the power density of the converter. The oscillator
and therefore the switching frequency is programmable by a
resistor on the ROSC pin. The relationship is shown in the
Typical Characteristics, FOSC vs. ROSC
.
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
10
Si9123
Vishay Siliconix
Hiccup Operation
When the applied voltage is greater than VREF and VCC is
greater than VUVLO, the output drivers are activated as normal.
If the voltage applied to the VINDET pin is greater than VCC
−0.3 V, the high-side driver, DH , will stop switching until the
voltage drops below VCC −0.3 V. If continuous switching is
desired under maximum VINEXTconditions, the resistive tap on
the VINEXT divider must be set to accommodate the normal
Current limiting is achieved by monitoring the differential
voltage between CS1 and CS2 pins which are connected
across a primary low-side sense resistor. Once the differential
voltage exceeds the 150-mV trigger point, Hiccup operation is
started. The SS pin is pulled to ground and switching stops until
the SSpincharges up to 2 Vbe whereupon a duty cycle limited
soft-start is initiated. The upper and lower switching points of
the current limit have 50 mV of hysteresis.
V
CC operating voltage. Alternatively, a zener clamp diode from
VINDET to GND may also be used.
VINDET also provides the input to the voltage feed-forward
function by adjusting the amplitude of the PWM ramp to the
PWM comparator.
VINEXT Voltage Monitor – VINDET
The Si9123 provides a means of sensing the voltage on
VINEXT to control the operating mode and provides the
feed-forward control voltage to the PWM controller. This is
achieved by choosing an appropriate resistive tap between
Shutdown Mode
If VINDET pin is forced below 470 mV the device will enter
SHUTDOWN mode. This powers down all unnecessary
functions of the controller, ensures that the primary switches
are off and results in a low level current demand of 140 ꢁA from
the VINEXT or VCC supplies.
V
INEXT and ground.
When the VINDET voltage is greater than 720 mV but less than
VREF and VCC is greater than VUVLO, all internal circuitry is
enabled, but switching is stopped.
TYPICAL CHARACTERISTICS
V
SS
vs. Temperature, V = 12 V
CC
V
REG
vs. Temperature, V = 48 V
IN
8.20
8.15
8.10
8.05
8.00
7.95
7.90
10.0
9.5
9.0
8.5
8.0
7.5
T
= +1.25 mV/C
C
V
INDET
ꢄ V
REF
V
INDET
ꢄ V
REF
T
= −11 mV/C
C
−50 −25
0
25
50
75
100 125 150
−50 −25
0
25
50
75
100 125 150
Temperature (_C)
Temperature (_C)
I
vs. V vs. Temperature
I
vs. V vs. Temperature
CC
SS1
CC
SS2
25
140
130
120
110
100
90
V
CC
= 13 V
23
21
19
17
15
V
CC
= 13 V
V
CC
= 12 V
V
CC
= 12 V
V
CC
= 10 V
V
CC
= 10 V
80
−50
−25
0
25
50
75
100
125
−50
−25
0
25
50
75
100
125
Temperature (_C)
Temperature (_C)
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
11
Si9123
Vishay Siliconix
TYPICAL CHARACTERISTICS
F
OSC
vs. R
@ V = 12 V
V vs. Temperature, V = 12 V
REF CC
OSC
CC
600
500
400
300
200
3.300
3.295
3.290
3.285
3.280
3.275
3.270
20
30
40
50
(kꢂ )
60
70
80
−50
−25
0
25
50
75
100
R
Temperature (_C)
OSC
I
vs. SS Duty Cycle, C = 22 nF
D , D Duty Cycle vs. V
HCUP
SS
L
H
EP
10
9
100
90
80
70
60
50
40
30
20
10
0
3.6 V = V
INDET
4.8 V
8
7.2 V
7
V
CC
= 12 V
6
V
V
C
C
= 12 V
CC
iINDET
DH
= 4.8 V
= C = 3 nF
5
DL
= 0.3 nF
SEC_SYNC
4
10
20
30
40
50
0.0
0.5
1.0
1.5
2.0
SS Duty Cycle (%) = t / (t + t )
V
EP
(V)
2
1
2
Duty Cycle vs. V
@ 25_C
= 1.2 V, V = 9.5 V
CC
INDET
V
EP
D , D Delay vs. Temperture
L
H
100
90
80
70
60
50
40
30
120
100
80
V
V
V
= 60 V
BST
LX
CC
= 48 V
= 12 V
t
d1
t
d2
t
d3
t
d4
D , D
L
H
60
40
−50
−25
0
25
50
75
100
125
2.5
3.5
4.5
V
5.5
(V)
6.5
7.5
Temperature (_C)
INDET
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
12
Si9123
Vishay Siliconix
TYPICAL CHARACTERISTICS
I
vs. Temperature
REG2
I
vs. Temperature
CC3
4.2
4.0
3.8
3.6
3.4
3.2
4.75
4.55
4.35
4.15
3.95
3.75
Drivers w/o C
IN
LOAD
Drivers w/o C
CC
LOAD
V
= 48 V
V
= 12 V
−50
−25
0
25
50
75
100
−50
−25
0
25
50
75
100
800
800
Temperature (_C)
Temperature (_C)
D , D I
H
vs. V
OL
D , D I
vs. V
OH
L
SINK
H
L
SOURCE
250
200
150
100
50
250
200
150
100
50
V
= 12 V
V
CC
= 12 V
CC
0
0
0
200
400
600
0
200
400
600
800
V
(mV)
V
(mV)
OL
OH
SEC_SYNC I
vs. V
OH
SEC_SYNC I
vs. V
OL
SOURCE
SINK
35
30
25
20
15
10
5
35
30
25
20
15
10
5
V
CC
= 12 V
V
CC
= 12 V
0
0
0
200
400
600
800
0
200
400
(mV)
600
V
(mV)
V
OH
OL
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
13
Si9123
Vishay Siliconix
TYPICAL WAVEFORMS
Figure 8. Over Current Hiccup (CS2 = 200 mV)
Figure 9. Over Current Hiccup Cycle
D
20 V/div
20 V/div
H
D
20 V/div
20 V/div
H
V
CC
= 12 V
V
CC
= 12 V
D
L
D
L
CS2 100 mV/div
SS 1 V/div
CS2 100 mV/div
SS 1 V/div
GND
C
SS
= 22 nF
C
SS
= 22 nF
200 ꢁ s/div
200 ꢁ s/div
Figure 10. Pre-Regulator Start-Up
Figure 11. Operating Driver Waveforms
V
CC
= 12 V
D
H
5 V/div
V
INEXT
SEC_SYNC
5 V/div
10 V/div
V
CC
D
L
5 V/div
2 ms/div
500 ns/div
Figure 12. SEC_SYNC Set-Up Time (t , t
)
Figure 13. SEC_SYNC Set-Up Time (t , t )
d1 d2
d3 d4
V
BST
= 60 V
SEC_SYNC
5 V/div
GND
D
H
5 V/div
V
CC
= 12 V
V
CC
= 12 V
D
L
5 V/div
SEC_SYNC
5 V/div
GND
GND
100 ns/div
100 ns/div
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
14
Si9123
Vishay Siliconix
LOGIC REPRESENTATIVE APPLICATION SCHEMATIC
1N4001
D3
U1
5 V Reg
V
AUX
+5 V
V
AUX
5 V
1 V
V
OUT
3
IN
C36
0.1 ꢁF
C37
0.1 ꢁF
GND
+5 V
D1B
R33
BAT54S
OUT
P
470 ꢂ
D1A
BAT54S
+5 V
L2A
GND
+5 V
4
3
D1B
PRE
CLX
D
L4A
C35
R31
TX
OUT
L3A
BAT54S
1
2
GATE
A
5
6
Q
Q
R32
1 kꢂ
3
2
1
10 ꢂ
0.1 ꢁF
2
D1A
BAT54S
CLR
C36
10 ꢁF
74AC00
L4B
74AC32
L3B
74HC74
L2A
+5 V
4
6
10
GATE
B
PRE
CLX
5
9
Q
5
OUT
11
12
13
N
8
74AC32
+5 V
Q
D
CLR
74AC00
R37
1 kꢂ
+5 V
D1B
BAT54S
74HC74
R35
5 kꢂ
R34
470 ꢂ
GND
1
Q5
2N3904
D1A
BAT54S
V
OUT
R36
5 kꢂ
Figure 14.
Document Number: 72098
S-40692—Rev. C, 19-Apr-04
www.vishay.com
15
C15
1 nF
R14
VIN
EXT
D11
SMAJ12CA
R16
10 ꢂ
+
3.3 ꢂ
C1
1 ꢁF
100 V
C4
15 ꢁF
50 V
C3
15 ꢁF
50 V
R27
1.4 kꢂ
C2
1 ꢁF
50 V
+
+
+
4
D1
5, 6,
7, 8
1
3
1, 2,
3
D8
DAS19
Q1
Si4486EY
5, 6,
7, 8
BAS19
C10
4.7 ꢁF
16 V
1
16
15
Q3
Si4886DY
V
BST
D2
IN
T
1
C8
0.1 ꢁF
1, 2
10MQ100N
Si9123
2
3
4
4
V
V
D
L
CC
H
5, 6,
7, 8
1, 2,
3
4
T3
5, 6
14
13
1, 2, 3
LEP-9080
REF
X
C29
470 pF
C9
1 ꢁF
Q2
Si4486EY
5, 6,
7, 8
Q4
Si4886DY
5
4
11,
12
GND
D
D4
R13
L
1:3
15 ꢂ
30BQ040
7, 8, 9
1 W
5
12
1, 2, 3
R
PGND
D5
OSC
4
C30
C20
680 pF
100 V
Q5
R6
35 kꢂ
30BQ040
1, 2, 3
200−800 pF
R1
90 kꢂ
11
10
9
9, 10
D7
D6
EP SEC_SYNC
Si4886DY
30BQ040
6
7
5, 6,
7, 8
MBR0520
R10
1, 2,
3
V
SS
INDET
2 kꢂ
7, 8
D3
3.3 V
R5
10 kꢂ
8
R12
0.02 ꢂ
3, 4
10MQ100N
C
4
S1
C
S2
C22
+
C23
C24
C32
10 ꢁF
6.3 V
VOUT
8:2:2
EPC19
+
+
+
5, 6,
7, 8
1, 2,
3
47 ꢁF
47 ꢁF
47 ꢁF
C11
1 nF
C14
C12
10 V
10 V
10 V
15 pF
22 nF
OUT_GND
Q6
Si4886DY
C5
1 ꢁF
50 V
C6
C7
+
R11
2 kꢂ
4
+
+
R7
15 ꢁF
15 ꢁF
50 V
50 V
R15
C16
GND
2 kꢂ
3.3 ꢂ
1 nF
LOGIC
2
2
Q7B
3
Q8B
C21
1 ꢁF
V
OUT
T2
3
TX_OUT
5 V
GATE
OUT
A
B
P
4
6
4
6
GATE
OUT
N
2:1
EP7
V
AUX
U2
MOC207
GND
R26
5.6 kꢂ
V
1
6
5
IN +
1
1
R19
2.2 kꢂ
C28
1 nF
C25
33 nF
R18
300 kꢂ
2
Q7A
Si3552DV
Q8A
Si3552DV
5
5
V
−
IN
C34
0.1 ꢁF
R24
1 Mꢂ
7
R22
33 kꢂ
7
3
2
6
+
−
U3
LM7301
R25
2 kꢂ
4
R23
18.6 kꢂ
U4
LM4041C1M3−1.2
3
C19
4.7 ꢁF
16 V
+
C33
0.1 ꢁF
1
2
C26
0.1 ꢁF
C27
0.1 ꢁF
OUT_GND
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| SI9123DQ-T1-E3 | VISHAY | IC 1 A SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PDSO16, LEAD FREE, TSSOP-16, Switching Regulator or Controller | 获取价格 |
|
| SI9124 | VISHAY | 500-kHz Push-Pull DC-DC Converter With Integrated Secondary Synchronous Rectification Control | 获取价格 |
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| SI9124DQ | VISHAY | 500-kHz Push-Pull DC-DC Converter With Integrated Secondary Synchronous Rectification Control | 获取价格 |
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| SI9124DQ-E3 | VISHAY | Analog Circuit, PDSO16 | 获取价格 |
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| SI9124DQ-T1 | VISHAY | 500-kHz Push-Pull DC-DC Converter With Integrated Secondary Synchronous Rectification Control | 获取价格 |
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| SI9124DQ-T1-E3 | VISHAY | Analog Circuit, PDSO16 | 获取价格 |
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| SI9130 | VISHAY | Pin-Programmable Dual Controller?Portable PCs | 获取价格 |
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| SI9130CG | VISHAY | Pin-Programmable Dual Controller?Portable PCs | 获取价格 |
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| SI9130CG-T1 | VISHAY | Pin-Programmable Dual Controller?Portable PCs | 获取价格 |
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