SI9139DG-2518 [VISHAY]
Multi-Output, Individual On/Off Control Power-Supply Controller; 多路输出，独立的开/关控制电源控制器
| 型号： | SI9139DG-2518 |
| 厂家： | 
VISHAY |
| 描述： | Multi-Output, Individual On/Off Control Power-Supply Controller |
| 文件： | 总17页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si9139
New Product
Vishay Siliconix
Multi-Output, Individual On/Off Control Power-Supply Controller
D 28-Pin SSOP Package
FEATURES
D Output Overvoltage Protection
D Five Output 50-W, Triple Output DC-DC-Controller
D Output Undervoltage Shutdown
D Up to 95% Efficiency
D Power-Good Output (RESET)
D "3% Total Regulation (Line, Load and Temperature)
D 4.5-V to 30-V Input Voltage Range
APPLICATIONS
D Two Fixed 1.5-V, 1.8-V, 2.0-V, 2.2-V, 2.5-V, 2.8-V, 3.3-V Outputs
D One Adjustable 1.24-V to 20-V Output
D Notebook and Subnotebook Computers
D PDAs and Mobile Communicators
D Portable Display
D 3.3-V Reference Output
D 5-V/30-mA Linear Regulator Output
D Individual ON/OFF Control for A and B Outputs
D 300-kHz Low-Noise Fixed Frequency Operation
D High Efficiency Pulse Skipping Mode Operation at Light Load
D Only Three Inductors RequiredNo Transformer
D LITTLE FOOTR Optimized Output Drivers
D Internal Under Voltage Lockout and Soft-Start
D Minimum Number of External Control Components
D Multimedia Set-Top Box
D Telecommunications Infrastructure
D Network Equipment
D Distributed Power Conversion
DESCRIPTION
The Si9139 is current-mode PWM and PSM converter
controller, with two high current, high efficiency synchronous
buck controllers and an adjustable buck-boost controller
whose output can be set between 1.24 V and 20 V with an
external resistor divider. Designed for fixed and portable
devices, it offers a total of five power outputs (three tightly
regulated dc/dc converter outputs, a precision 3.3-V reference
and a 5-V LDO output. Individually controlled power-up
sequencing, power-good signal with delay, internal frequency
compensation networks and automatic boot-strapping
simplify the system by minimizing the number of external
components while achieving conversion efficiencies
approaching 95%.
The Si9139 is available in a 28-pin SSOP package and
specified to operate over the extended commercial (-40_C to
85_C) temperature range.
FUNCTIONAL BLOCK DIAGRAM
V
IN
(4.5 V to 30 V)
5-V
Linear
Regulator
3.3-V
Voltage
Reference
V
REF
V
L
(+3.3 V)
(5.0 V)
V
V
OUT
OUT
A
0 - 6BA
1.5- V - 3.3-V
1.8- V - 3.3-V
0 - 6 A
SMPS
SMPS
A
B
V
OUT
C
Auxiliary SMPS
Programmable
1.24-V to 20-V/500 mA
Adjustable
ON
ON
A
Logic Control
Power_Good
RESET
(Power_Good)
B
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
1
Si9139
New Product
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
V
P
V
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36 V
DH to LX , DH to LX ,
A A B B
IN
DH to LX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (BST +0.3 V)
C
C
x
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 V
GND
a
Continuous Power Dissipation (T = 70_C)
A
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.5 V
L
b
28-Pin SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 mW
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40 _C to 85_C
Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40 _C to 125_C
Lead Temperature (Soldering, 10 Sec.) . . . . . . . . . . . . . . . . . . . . . . . . . . 300_C
BST , BST , BST to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +36 V
A
B
C
V
Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous
L
LX to BST ; LX to BST ; LX to BST . . . . . . . . . . . . . . . . . -6.5 V to 0.3 V
A
A
B
B
C
C
Inputs/Outputs to GND
(CS , CS , CSP, CSN) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (V +0.3 V)
A
B
L
Notes
RESET, ON , ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V
A
B
a. Device mounted with all leads soldered or welded to PC board.
DL , DL , DL to PGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to (V +0.3 V)
b. Derate 9.52 mW/_C above 70_C.
A
B
C
L
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
SPECIFICATIONS
Test Conditions
Limits
Typb
V
= 15 V , I = I
= 0 mA
IN
VL
REF
Parameter
Buck Controller A
Mina
Maxa
Unit
T
A
= -40_C to 85_C, All Controllers ON
Total Regulation (Line, Load, and Temperature)
V
= 4.5 V to 30 V, 0 < V
- V < 90 mV
FB3
-3
0
3
IN
CS3
V
V
= 6.0 V to 30 V
= 4.5 V to 30 V
0.5
1.0
0.5
160
180
IN
IN
Line Regulation
Load Regulation
%
0 < V
- V
FB3
< 90 mV
CS3
V
V
> 2.5 V
90
125
OUT
OUT
Current Limit
V
- V
mV
CSA
FBA
< 2.5 V
100
Bandwidth
L = 10 mH, C = 330 mF
= 20 mW
50
65
7
kHz
_
Phase Margin
Minimum Duty Cycle
R
SENSE
%
Buck Controller B
Total Regulation (Line, Load, and Temperature)
V
= 4.5 V to 30 V, 0 < V
- V < 90 mV
FB5
-3
0
3
IN
CS5
V
V
= 6.0 V to 30 V
= 4.5 V to 30 V
0.5
1.0
0.5
160
180
IN
IN
Line Regulation
Load Regulation
%
0 < V
- V
FBB
< 90 mV
CSB
V
V
> 2.5 V
< 2.5 V
90
125
OUT
OUT
Current Limit
V
- V
mV
CSB
FBB
100
Bandwidth
L = 10 mH, C = 330 mF
= 20 mW
50
65
7
kHz
_
Phase Margin
Minimum Duty Cycle
R
SENSE
%
Auxiliary Controller C
Total Regulation (Line, Load, and Temperature)
Output Voltage Set to 12 V
V
= 4.5 V to 30 V, 0 < V
- V
< 300 mV
IN
CSP
CSN
-5
0
5
R
5
= 26.4 kW, R = 10 kW (See Figure 1)
6
V
V
= 6.0 V to 30 V
0.5
1.0
IN
%
Line Regulation
= 4.5 V to 30 V
IN
Load Regulation
0 < V
- V
FBN
< 300 mV
0.5
CSP
Current Limit
V
- V
280
360
10
450
mV
kHz
_
CSP
CSN
Bandwidth
L = 10 mH, C = 100 mF
= 100 mW, C = 120 pF
Phase Margin
R
SENSE
65
comp
Current-Sense Common Mode Voltage Range
Feedback Input Voltage Range
Minimum Duty Cycle
Maximum Duty Cycle
0.0
0.0
2.1
2.1
V
7
%
V
= 5 V
85
IN
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
2
Si9139
New Product
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Limits
Typb
V
= 15 V , I = I
= 0 mA
IN
VL
REF
Parameter
Mina
Maxa
Unit
T
A
= -40_C to 85_C, All Controllers ON
Internal 5-V Regulator
V
Output Current (Internal and External)
30
75
60
mA
L
V
V
V
Output
All Controllers OFF, V >5.5 V, 0 <I <30 mA
4.7
3.6
5.5
4.2
L
L
L
IN
L
V
Fault Lockout Voltage
Fault Lockout Hysteresis
V
Falling Edge
L
mV
Reference
REF Output
3.24
1.20
3.3
25
3.36
60
V
mV
V
REF Load Regulation
Auxiliary Feedback Voltage
0 to 1 mA
FB Pin
C
1.24
1.28
Supply Current
Supply Current*Shutdown
Supply Current*Operation
All Converters OFF, No Load
All Controllers ON, No Load, f = 300 kHz
25
60
mA
1100
1800
OSC
Oscillator
Oscillator Frequency
Maximum Duty Cycle
270
92
300
95
330
14
kHz
%
Fault Detection SMPSA and SMPSB Outputs
Overvoltage Trip Threshold
With Respect To Unloaded Output Voltage
6
10
%
CS or CS Driven 2% Above Overvoltage Trip
A
B
Overvoltage-Fault Propagation Delay
1.5
ms
Threshold
Output Undervoltage Threshold
With Respect to Unloaded Output Voltage
From each SMPS Enabled
-40
16
-30
20
-20
24
%
Output Undervoltage Lockout Time
ms
RESET
With Respect To Unloaded Output Voltage
Rising Edge
RESET Start Threshold
-5.5
%
Falling Edge, FB or FB Driven 2% Above Overvol-
tage or 2% Below Undervoltage Lockout Thresholds
A
B
RESET Propagation Delay (Falling)
RESET Delay Time (Rising)
Inputs and Outputs
1.5
ms
With Respect to 2nd SMPS Lockout Time Done
92
107
122
ms
Feedback Input Leakage Current
Input Leakage Current
FB = 1.24 V
1
C
mA
ON , ON , V = 0 V or V
L
"1
A
B
IN
Gate Driver Sink/Source Current (Buck)
Gate Driver On-Resistance (Buck)
Gate Driver Sink/Source Current (Auxiliary)
Gate Driver On-Resistance (Auxiliary)
RESET Output Low Voltage
DL , DH , DL , DH Forced to 2 V
1
2
A
W
A
A
A
B
B
High or Low
7
DH , DL Forced to 2 V
0.2
C
C
High or Low
15
0.4
1
W
V
RESET, I
= 4 mA
SINK
RESET Output High Leakage
RESET = 5 V
mA
ONA, ONB
Logic Low
Logic High
V
0.8
IL
V
V
2.4
IH
Notes
a. The algebraic convention is used whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing, and are measured at T = 25_C.
A
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
3
Si9139
New Product
Vishay Siliconix
PIN CONFIGURATION
RESET
1
2
28
27
26
25
24
23
CS
A
FB
BST
DH
LX
FB
A
C
C
C
C
C
DH
3
A
4
LX
A
BST
5
A
DL
6
DL
A
CSP
CSN
7
22
V
V
IN
SSOP-28
Top View
8
21
L
COMP
GND
FB
B
9
20
19
18
17
16
15
10
11
12
13
14
PGND
REF
DL
B
ON
ON
CS
BST
A
B
B
B
LX
B
DH
B
PIN DESCRIPTION
Pin
Symbol
Description
Open drain NMOS output active-low timed reset output. RESET swings GND to V . Goes high after a fixed 32,000 clock
L
cycle delay following proper power-up of all supply outputs indicating Power_Good.
1
RESET
Feedback for Auxiliary controller C. Normally connected to an external resistor divider used to set the Auxiliary output
voltage.
2
FB
C
3
BST
Boost capacitor connection for Auxiliary SMPS controller C
Gate-drive output for Auxiliary SMPS controller C high-side MOSFET
Inductor connection for Auxiliary SMPS controller C
Gate-drive output for Auxiliary SMPS controller C low-side MOSFET
Current sense positive input for Auxiliary SMPS controller C
Current sense negative input for Auxiliary SMPS controller C
Auxiliary SMPS controller C compensation connection, if required
Analog ground
C
4
DH
C
5
LX
C
6
DL
C
7
CSP
CSN
8
9
COMP
GND
REF
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
3.3-V internal reference
ON
ON
Logic High enables the SMPS controller A
A
B
B
B
B
Logic High enables the SMPS controller B and the Auxiliary SMPS controller C adjustable SMPS controllers
Current sense input for SMPS controller B
CS
DH
Gate-drive output for SMPS controller B high-side MOSFET
Inductor connection for SMPS controller B
LX
BST
Boost capacitor connection for SMPS controller B
Gate-drive output for SMPS controller B low-side MOSFET
Power ground
B
DL
B
PGND
FB
Feedback for SMPS controller B
B
V
5-V logic supply voltage for internal circuitry
L
V
Input voltage
IN
DL
A
Gate-drive output for SMPS controller A low-side MOSFET
Boost capacitor connection for SMPS controller A
Gate-drive output for SMPS controller A high-side MOSFET
Inductor connection for SMPS controller A low-side MOSFET
Feedback for SMPS controller A
BST
A
LX
A
DH
A
A
FB
CS
Current sense input for SMPS controller A
A
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
4
Si9139
New Product
Vishay Siliconix
ORDERING INFORMATION
Temperature
Range
SMPSB, SMPSA
Output Voltages
Part Number
Si9139DG – 3328
Si9139DG – 3325
Si9139DG – 3322
Si9139DG – 3320
Si9139DG – 3318
Si9139DG – 3315
Si9139DG – 2825
Si9139DG – 2822
Si9139DG – 2820
Si9139DG – 2818
Si9139DG – 2815
Si9139DG – 2522
Si9139DG – 2520
Si9139DG – 2518
Si9139DG – 2515
Si9139DG – 2220
Si9139DG – 2218
Si9139DG – 2215
Si9139DG – 2018
Si9139DG – 2015
Si9139DG – 1815
3.3 V, 2.8 V
3.3 V, 2.5 V
3.3 V, 2.2 V
3.3 V, 2.0 V
3.3 V, 1.8 V
3.3 V, 1.5 V
2.8 V, 2.5 V
2.8 V, 2.2 V
2.8 V, 2.0 V
2.8 V, 1.5 V
2.8 V, 1.8 V
2.5 V, 2.2 V
2.5 V, 2.0 V
2.5 V, 1.8 V
2.5 V, 1.5 V
2.2 V, 2.0 V
2.2 V, 1.8 V
2.2 V, 1.5 V
2.0 V, 1.8 V
2.0 V, 1.5 V
1.8 V, 1.5 V
-40 to 85_C
Contact factory for other
voltages
Si9139DG
Evaluation
Board
Temperature
Range
Board Type
Si9139DB
-40 to 85_C
Surface Mount
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Efficiency vs. Auxiliary SMPS C Output Current
(Buck-Boost Configuration)
Efficiency vs. SMPS B Output Current
85
80
100
V
= 15 V
IN
Frequency = 300 kHz
V
= 5 V
IN
90
6 V
V
V
= 12 V
= 24 V
75
70
65
IN
IN
30 V
80
70
60
SMPS A No Load
= 2.5 V
SMPS A, B No Load
V = 12 V
OUT
V
OUT
60
55
50
0.001
0.01
0.1
1
0.1
1
Load Current (A)
10
Current (A)
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
5
Si9139
New Product
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
Efficiency vs. Auxiliary SMPS C Output Current
Efficiency vs. SMPS B Output Current
(Buck Configuration)
90
100
80
V
= 5 V
IN
V
= 5 V
75
60
45
30
IN
V
= 12 V
IN
V
= 12 V
IN
60
40
20
V
= 24 V
IN
SMPS A No Load
= 12.5 V
SMPS A, B No Load
V
OUT
V
= 2.1 V
OUT
15
0
0
0.01
0.1
Output Current (A)
1
10
0.01
0.1
Load Current (A)
1
TYPICAL WAVEFORMS
PWM Loading B Converter
PWM Unloading B Converter
(V = 5.0 V, V
= 2.5 V)
IN
OUT
(V = 5.0 V, V
= 2.5 V)
IN
OUT
V
V
OUT
(100 mV/div)
OUT
(100 mV/div)
Load
(1 A/div)
Load
(1 A/div)
20.0 ms/div
20.0 ms/div
PSM to PWM B Converter
PWM to PSM B Converter
(V = 5.0 V, V
= 2.5 V)
(V = 5.0 V, V
= 2.5 V)
IN
OUT
IN
OUT
V
V
OUT
OUT
(50 mV/div)
(50 mV/div)
Load
(1 A/div)
Load
(1 A/div)
(0.1 A to 1.8 A)
(0.1 A to 1.8 A)
50 ms/div
50 ms/div
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
6
Si9139
New Product
Vishay Siliconix
TYPICAL WAVEFORMS
PSM Operation B Converter
PSM Operation B Converter
V
V
OUT
(20 mV/div)
V(V = 5.0 V, V
= 2.5 V)
OUT
IN
OUT
(20 mV/div)
(V = 5.0 V, V
= 2.5 V)
IN
OUT
Inductor Node
(LXB)
(5 V/div)
Inductor Node
(LXB)
(5 V/div)
(I
OUT
= 1.2 A)
Inductor Current
(0.5 A/div)
Inductor Current
(0.5 A/div)
(I
OUT
= 100 mA)
10.0 ms/div
10.0 ms/div
PWM Loading B Converter
PWM Unloading A Converter
(V = 12.0 V, V
= 2.0 V)
IN
OUT
V
V
OUT
(20 mV/div)
OUT
(20 mV/div)
(V = 12.0 V, V
= 2.5 V)
IN
OUT
Load
(1 A/div)
Load
(1 A/div)
(1.5 A to 4.0 A )
(1.8 A to 4.3 A )
50 ms/div
50 ms/div
PSM to PWM A Converter
PWM to PSM A Converter
VV = 5.0 V, V
= 2.0 V
(V = 10.0 V, V
= 3.3 V)
V
OUT
IN
OUT
IN
OUT
(50 mV/div)
V
OUT
(50 mV/div)
Load
(1 A/div)
Load
(1 A/div)
(0.1 A to 3.0 A )
50 ms/div
50 ms/div
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
7
Si9139
New Product
Vishay Siliconix
TYPICAL WAVEFORMS
250-mA Transient Auxiliary Converter C
(Buck-Boost Mode—Output Set To 12 V)
VV = 10.0 V
IN
V
OUT
(100 mV/div)
Load Current
(100 mA/div)
200 ms/div
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
8
Si9139
New Product
Vishay Siliconix
STANDARD APPLICATION CIRCUIT (BUCK−BOOST AUXILIARY)
V
IN
4.5 ~ 30 V
+5 V
C7
33 mF
D1A
CMPD2836
C5
D1B
10 mF
C4
V
V
L
IN
33 mF
22
24
21
C1
0.1 mF
C2
0.1 mF
BST
BST
A
B
Q2
Si7888
L1, 10 mH
17
R
2
DH
B
0.02 W
Q1
Si7888
15
V
OUT
B
DH
A
LX
B
26
25
16
C3
330 mF
LX
A
Q4
Si7886
R
L2
10 mH
1
DL
18
B
0.02 W
SS34
V
OUT
A
Q3
Si7886
DL
A
CS
14
23
28
SS34
B
C6
330 mF
FB
B
20
D3
CS
A
CMPD2836
C8
C9
4.7 mF
BST
C
3
0.1 mF
Q5
DH
Si3456
C
V
L
4
L3, 10 mH
V
D4, BYS10-35
OUT
C
LX
C
1.24 to 20 V
500 mA
5
C10
100 mF
20 kW
D2, BYS10-35
FB
Q6
Si3456
A
27
1
DL
C
6
7
CSP
RESET
PGND*
0.2 W
R
3
R
5
ON
A
GND*
12
13
ON
B
CSN
8
2
FB
C
3.3 V
1 mA
REF
COMP
PGND
11
10
9
R
6
GND
C11
1 mF
C12
19
120 pF
*PGND and GND planes should be connected to a single point (star) ground.
Figure 1.A
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
9
Si9139
New Product
Vishay Siliconix
STANDARD APPLICATION CIRCUIT (5−V INPUT Ċ AUXILIARY IN BOOST MODE)
V
IN
4.5 ~ 5.5 V
C7
33 mF
D1A
CMPD2836
D1B
C4
V
V
L
IN
33 mF
22
24
21
C1
0.1 mF
C2
0.1 mF
BST
BST
A
B
Q2
17
Si7888
L1, 10 mH
R
2
DH
B
0.02 W
Q1
Si7888
V
15
OUT
B
DH
A
LX
B
26
25
16
C3
330 mF
LX
A
Q4
Si7886
R
L2
10 mH
1
DL
18
B
0.02 W
SS34
V
OUT
A
Q3
Si7886
DL
A
CS
14
23
28
SS34
B
C6
330 mF
FB
B
20
CS
A
V
L
L3, 10 mH
V
OUT
D4, BYS10-35
C
(V +0.5 V) to
IN
20 V
500 mA
20 kW
C10
100 mF
FB
Q6
Si3456
A
27
1
DL
C
6
7
CSP
RESET
PGND*
0.2 W
R
3
R
5
ON
A
GND*
12
13
ON
B
CSN
8
2
FB
C
3.3 V
1 mA
REF
COMP
PGND
11
10
9
R
6
GND
C11
1 mF
C12
19
120 pF
*PGND and GND planes should be connected to a single point (star) ground.
Figure 1.B
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
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Si9139
New Product
Vishay Siliconix
STANDARD APPLICATION CIRCUIT (5−V INPUT Ċ AUXILIARY IN BUCK MODE)
V
IN
4.5 ~ 5.5
V
C7
33 mF
D1A
CMPD2836
D1B
C4
V
V
L
IN
33 mF
22
24
21
C1
0.1 mF
C2
0.1 mF
BST
BST
A
B
Q2
17
Si7888
L1, 10 mH
R
2
DH
B
0.02 W
Q1
Si7888
15
V
OUT
B
DH
A
LX
B
26
25
16
C3
330 mF
LX
A
Q4
Si7886
R
L2
10 mH
1
DL
18
B
0.02 W
V
SS34
OUT
A
Q3
Si7886
DL
A
CS
14
23
28
SS34
B
C6
330 mF
FB
B
20
D3
CMPD2836
C8
CS
A
BST
C
3
0.1 mF
Q5
Si3456
DH
C
V
L
4
L3, 10 mH
R
3
V
OUT
1.24 tCo 2.1 V
500 mA
LX
C
5
C10
100 mF
20 kW
D2, BYS10-35
FB
A
27
1
CSP
CSN
RESET
PGND*
7
R
5
ON
A
GND*
12
13
ON
B
8
2
FB
C
3.3 V
1 mA
REF
COMP
PGND
11
10
9
C17
R
6
GND
C11
1 mF
C12
120 pF
19
R
4
*PGND and GND planes should be connected to a single point (star) ground.
Figure 1.C
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
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Si9139
New Product
Vishay Siliconix
TIMING DIAGRAMS
The converter is enabled
ON or ON
A
B
V
is applied
IN
V
IN
LDO is activated after V is
IN
applied
V
L
REF circuit is activated after V
becomes available
L
0.8 V
V
REF
After V
goes above 0.8 V,
REF
the converter is turned on
OSC EN
(Sysmon EN)
Oscillator is activated
OSC
Slow soft-start gradually increases
the maximum inductor current
4 ms
f
(SS)
DH
max
High-side gate drive duty ratio
gradually increases to maximum
t
BBM
Low-side gate drive
D
L
FIGURE 2. Converter is Enabled Before V is Applied, A or B controllers
IN
The converter is enabled
ON or ON
A
B
V
is applied
IN
V
IN
LDO is activated after V is
IN
applied
V
L
REF circuit is activated after V
becomes available
L
0.8 V
V
REF
After V
goes above 0.8 V,
REF
the converter is turned on
OSC EN
(Sysmon EN)
Oscillator is activated
OSC
4 ms
Slow soft-start gradually increases
the maximum inductor current
f
(SS)
DH
DL
max
FIGURE 3. Converter is Enabled After V is Applied, A or B Controllers
IN
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
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Si9139
New Product
Vishay Siliconix
TIMING DIAGRAMS
V
IN
[ V (V )
L
V
is removed
IN
V
L
4 V
3.4 V
LDO Deactivated after
is removed
V
IN
RESET
V
REF
OSC EN
(Sysmon EN)
Oscillator disabled
OSC
D
H
D
L
f
(SS)
max
FIGURE 4. Power Off Sequence
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
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Si9139
New Product
Vishay Siliconix
DETAILED FUNCTIONAL BLOCK DIAGRAMS
FB_
CS_
FB_
+
_
1X
R
R
X
Error
Amplifier
Y
-
ON or ON
A
B
Internal
Reference
BST_
PWMCMP
+
-
DH
DH
+
Logic
Control
Pulse
Skipping
Control
LX_
SLC
BBM
DL
20 mV
V
L
Current
Limit
DL
V
Soft-Start
SYNC
Rectifier Control
t
FIGURE 5. Buck Block Diagram (SMPS A and B Controllers)
FB
C
R
R
2
ON
B
3
Error
Amplifier
PWM
Comparator
BST
C
-
-
Logic
Control
DH
1.24-V
+
+
LX
C
COMP
SLC
DH
C
V
L
C/S
Amplifier
Pulse
DL
DL
C
CSP
CSN
-
Skipping
Control
+
-
100 mV
+
Current Limit
V
Soft-Start
t
FIGURE 6. Buck-Boost Block Diagram (Auxiliary SMPS Controller C)
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
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Si9139
New Product
Vishay Siliconix
DETAILED FUNCTIONAL BLOCK DIAGRAMS
5-V
Linear
Regulator
V
IN
Enable
FB
A
CS
A
BST
A
A
SMPS
Controller
DH
A
LX
A
V
L
DL
A
Good A
Enable
4 V
FB
B
3.3-V
Reference
CS
BST
DH
B
B
B
SMPS
Controller
2.4 V
B
LX
B
DL
B
Good B
ON
ON
A
Enable
FB
CSP
CSN
BST
DH
C
B
Auxiliary
1.2- to 20-V
Adjustable
Buck-Boost
Controller
C
C
Reset
Handler
C
LX
C
DL
C
RESET
FIGURE 7. Complete Si9139 Block Diagram
DESCRIPTION OF OPERATION
Shutdown Mode
RESET pin will go high, signifying that all converters are
operating correctly (see RESET Power Good Voltage
Monitor).
The logic threshold for the ONA and ONB pins is 1.6 V. Input
voltage must be 0.8 V or less for logic low and 2.4 V or higher
for logic high.
The Si9139 converts a 4.5-V to 30-V input voltage to five
different output voltages; two buck (step-down) high current,
PWM, switch-mode supplies of 1.5-V to 3.3-V, one
“Buck-Boost” PWM switch-mode supply adjustable from
1.24 V to 20 V, one precision 3.3-V reference and one 5-V low
drop out (LDO) linear regulator output. Switch-mode supply
output current capabilities depend on external components
(can be selected to exceed 10 A). In the standard application
circuit illustrated in Figure 1, each buck converter is capable of
delivering 5 A, with the buck-boost converter delivering
500 mA.
Start-up Sequence
Start-up is controlled by individual ON/OFF control. The A
output is controlled by ONA whilst the B and the C adjustable
outputs are both controlled by ONB.
When both the A and B SMPS outputs are within tolerance and
32,000 clock cycles (typically equal to 107 ms) have elapsed
since the second SMPS output went into regulation, the
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
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Si9139
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DESCRIPTION OF OPERATION (CONT’D)
Buck Converter Operation: Converters A and B
current limit threshold, causing the high-side MOSFET to be
turned off instantaneously regardless of the input, or output
condition. The Si9139 features clock cycle by clock cycle
current limiting capability.
The A and B buck converters are both current-mode PWM and
PSM (during light load operation) regulators using high-side
bootstrap n-channel and low-side n-channel MOSFETs. At
light load conditions, the converters switch at a lower
frequency than the clock frequency. This operating condition is
defined as pulse-skipping. The operation of the converter(s)
switching at clock frequency is defined as normal operation.
Auxiliary Converter C Operation: Buck-Boost Operation
The Si9139 has an auxiliary adjustable 1.24-V to 20-V output
non-isolated buck-boost converter, called for brevity a
Buck-Boost. The input voltage range can span above or below
the regulated output voltage. It consists of two n-channel
MOSFET switches that are turned on and off in phase, and two
diodes. Similar to the buck converter, during the light load
conditions, the Buck-Boost converter will switch at a frequency
lower than the internal clock frequency, which can be defined
as pulse skipping mode (PSM); otherwise, it operates in
normal PWM mode.
Normal Operation PWM: Buck Converters A and B
In normal operation, the buck converter high-side MOSFET is
turned on with a delay (known as break-before-make time -
tBBM), after the rising edge of the clock. After a certain on time,
the high-side MOSFET is turned off and then after a delay
(tBBM), the low-side MOSFET is turned on until the next rising
edge of the clock, or the inductor current reaches zero. The
tBBM (approximately 25 ns to 60 ns), has been optimized to
guarantee the efficiency is not adversely affected at the high
switching frequency and a specified minimum to account for
variations of possible MOSFET gate capacitances.
The output voltage of the Buck-Boost converter is set by two
resistors (R5 and R6, see Figure 1.A) where,
(R5 ) R6)
VOUT
+
VFB
R6
C
During the normal operation, the high-side MOSFET switch
on-time is controlled internally to provide excellent line and
load regulation over temperature. Both buck converters have
load, line, regulation to within 1.0% tolerance.
Auxiliary Converter C Normal Operation: Buck-Boost
Mode
Pulse Skipping Operation: Buck Converters A and B
In buck-boost operation mode, the two MOSFETs are turned
on at the rising edge of the clock, and then turned off. The on
time is controlled internally to provide excellent load, line, and
temperature regulation. The Buck-Boost converter has load,
line and temperature regulation well within 5%.
When the buck converter switching frequency is less than the
internal clock frequency, its operation mode is defined as pulse
skipping mode. During this mode, the high-side MOSFET is
turned on until VCS-VFB reaches 20 mV, or the on time reaches
its maximum duty ratio. After the high-side MOSFET is turned
off, the low-side MOSFET is turned on after the tBBM delay,
which will remain on until the inductor current reaches zero.
The output voltage will rise slightly above the regulation
voltage after this sequence, causing the controller to stay idle
for the next clock cycle, or several clock cycles. When the
output voltage falls slightly below the regulation level, the
high-side MOSFET will be turned on again at the next clock
cycle. With the converter remaining idle during some clock
cycles, the switching losses are reduced preserving
conversion efficiency during the light output current condition.
Auxiliary Converter
Buck-Boost Converter
C
Pulse Skipping Operation:
Under the light load conditions, similar to the buck converter,
the Buck-Boost converter will enter pulse skipping mode. The
MOSFETs will be turned on until the inductor current increases
to such a level that the voltage across the pin CSP and pin CSN
reaches 360 mV, or the on time reaches the maximum duty
cycle. After the MOSFETs are turned off, the inductor current
will conduct through two diodes until it reaches zero. At this
point, the Buck-Boost converter output will rise slightly above
the regulation level, and the converter will stay idle for one or
several clock cycle(s) until the output falls back slightly below
the regulation level. The switching losses are reduced by
skipping pulses preserving the efficiency during light load.
Current Limit: Buck Converters
When the buck converter inductor current is too high, the
voltage across pin CS3 and pin FB will exceed the 125 mV
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
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Si9139
New Product
Vishay Siliconix
DESCRIPTION OF OPERATION (CONT’D)
Auxiliary Converter C Normal Operation: Boost Mode
Output Overvoltage Protection
The A and B SMPS outputs are monitored for overvoltage. If
either output is more than 10% above the nominal regulation
point, all low-side gate drivers are latched high until ONA and
ONB are toggled. This action turns on the synchronous
rectifier MOSFETs with a 100% duty cycle, in turn rapidly
discharging the output capacitors and forcing all SMPS
outputs to ground.
The auxiliary converter may be operated in boost mode as
shown in Figure 1.B when operating from a 5 V"10% input
supply voltage. This ability reduces the component count of
the converter and provides a high efficiency output voltage of
in the range of 6 V to 20 V at up to10 W of power. Operation
is similar to the buck-boost mode described above.
Auxiliary Converter C Normal Operation: Buck Mode
Output Undervoltage Protection
The auxiliary converter may also be operated in buck mode as
shown in Figure 1.C when operating from a 5 V"10% input
supply voltage. This ability reduces the component count of
the converter and provides a high efficiency output voltage of
in the range of 1.24 V to 2.1 V with 1 W of power. Operation
is similar to the buck-boost mode described above.
In Si9139, each of the A and B SMPS outputs has an
undervoltage protection circuit that is activated 6,144 clock
cycles (20.48 ms) after the SMPS is enabled. If either SMPS
output is typically under 70% of the nominal value, all SMPSs
are latched off and their outputs are clamped to ground by the
synchronous rectifier MOSFETs. The SMPS will not restart
until both ONA and ONB are toggled.
Auxiliary Converter C Current Limit
Stability:
Similar to the buck converter; when the voltage across pin
CSP and pin CSN exceeds 360-mV typical, the two MOSFETs
will be turned off regardless of the input and output conditions.
Buck Converters:
In order to simplify designs, the A and B supplies do not require
external frequency compensation. Meanwhile, it achieves
excellent regulation and efficiency. The converters are current
mode control, with a bandwidth substantially higher than the
LC tank dominant pole frequency of the output filter. To ensure
stability, the minimum capacitance and maximum ESR values
are:
Grounding:
There are two separate grounds on the Si9139, analog signal
ground (GND) and power ground (PGND). The purpose of two
separate grounds is to prevent the high currents on the power
devices (both external and internal) from interfering with the
analog signals. The internal components of Si9139 have their
grounds tied (internally) together. These two grounds are then
tied together (externally) at a single point, to ensure Si9139
noise immunity.
VREF
V
OUT x Rcs
VREF
C
LOAD w
ESR v
2p xꢀVOUT x RCS x BW
where VREF = 3.3 V, VOUT is the output voltage (A or B), Rcs
is the current sensing resistor in ohms and BW = 50 khz. With
the components specified in the application circuit (L = 10 mH,
This separation of grounds should be maintained in the
external circuitry, with the power ground of all power devices
being returned directly to the input capacitors, and the small
signal ground being returned to the GND pin of Si9139.
RCS = 0.02 W, COUT = 330 mF, ESR approximately 0.1 W), the
converter has a bandwidth of approximately 50 kHz, with
minimum phase margin of 65_, and dc gain above 50 dB.
RESET Handler
Other Outputs
The power-good monitor generates a system RESET signal.
At first power-up (ONA/B going high), RESET is held low until
the A and B outputs are in regulation and beyond the UVLO
timer. At this point, an internal timer begins counting oscillator
pulses and RESET continues to be held low until 32,000
cycles have elapsed. After this timeout period, 107 ms @
300 kHz, RESET is actively pulled up to VL, when the
recommended 20-kW resistor to VL is on the RESET pin.
The Si9139 also provides a 3.3-V reference which can be
externally loaded up to 1 mA, as well as, a 5-V LDO output
which can be loaded up to 30 mA, or even more depending on
the system application. For stability, the 3.3-V reference output
requires a 1-mF capacitor, and the 5-V LDO output requires a
10-mF capacitor.
Document Number: 71841
S-22317—Rev. A, 16-Dec-02
www.vishay.com
17
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