SI9166BQ-T1 [VISHAY]
High Frequency Programmable Topology Controller; 高频可编程控制器拓扑型号: | SI9166BQ-T1 |
厂家: | VISHAY |
描述: | High Frequency Programmable Topology Controller |
文件: | 总11页 (文件大小:146K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si9166
Vishay Siliconix
High Frequency Programmable Topology Controller
FEATURES
D Buck or Boost Configuration
D Integrated UVLO and POR
D Integrated Soft-Start
D Synchronization
D Voltage Mode Control
D 2.7-V to 6-V Input Voltage Range for VDD and VS
D Programmable PWM/PSM Control
− Up to 2-MHz Switching Frequency in PWM
− Synchronous Rectification in PWM
− Less than 200-mA IDD in PSM
D Shutdown Current <1 mA
DESCRIPTION
The Si9166 is a programmable topology controller for today’s
continuous changing portable electronic market. Si9166
provides flexibility of utilizing various battery configurations
and chemistries such as NiCd, NiMhy, or Li+ with input voltage
range of 2.7 V to 6 V. An additional flexibility is provided with
topology programmability to power multiple loads such as
power amplifiers, microcontrollers, or baseband logic IC’s.
The converters can be programmed to be synchronous Buck
or Boost topology. For ultra-high efficiency, converters are
designed to operate in synchronous rectified PWM mode
under full load while transforming into externally controlled
pulse skipping mode (PSM) under light load. All these features
are provided by the Si9166 without sacrificing system
integration requirements of fitting these circuits into ever
demanding smaller and smaller space. The Si9166 is capable
of switching up to 2 MHz to minimize the output inductor and
capacitor size in order to decrease the overall converter size.
The Si9166 is available in both standard and lead (Pb)-free
TSSOP-16 pin packages and specified to operate over the
industrial temperature range of −25_C to 85_C.
TYPICAL APPLICATION CIRCUITS
V
IN
Si6803
V
OUT
Si6803
D
S
D
V
IN
V
OUT
D
S
D
S
1
2
2
2
S
S
1
S
1
2
2
2
S
1
S
G
G
1
G
G
1
SD
SD
Si9166
Si9166
V
S
MODE
V
S
MODE
N/C
DH
SD
DL
N/C
DH
SD
DL
N/C
N/C
PWM/PSM
SYNC
PWM/PSM
SYNC
PWM/PSM PGND
PWM/PSM PGND
SYNC
GND
REF
FB
V
SYNC
GND
REF
FB
V
O
O
V
DD
V
DD
R
R
OSC
OSC
COMP
COMP
Buck Configuration
Boost Configuration
Document Number: 70847
S-40701—Rev. C, 19-Apr-04
www.vishay.com
1
Si9166
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND
Peak Output Current (DH, DL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65_C to 150_C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
MODE, PWM/PSM, SYNC, SD, V
COMP, FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V
, R
REF OSC
a
+ 0.3 V
Power Dissipation (Package)
DD
b
16-Pin TSSOP (Q Suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 925 mW
V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
S
Thermal Impedance (q
)
JA
PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "0.3 V
16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135_C/W
Voltages Referenced to PGND
Notes
V
S.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 7.4 mW/_C above 25_C.
DH, DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to V + 0.3 V
S
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Voltages Referenced to AGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V
F
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 kHz to 2 MHz
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kW to 300 kW
Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF
osc
V
DD
R
osc
MODE, PWM/PSM, SYNC, SD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
Voltages Referenced to PGND
DD
V
REF
V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 V to 6 V
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
Parameter
Reference
Symbol
2.7 V v V , V v 6 V
Mina
Typb
Maxa
Unit
DD
S
I
= 0A
1.268
1.280
1.3
1.3
3
1.332
1.320
REF
Output Voltage
V
V
REF
I
= 0, T = 25°C
A
REF
Load Regulation
DV
V
DD
= 3.3 V, −500 µA < I <0
REF
mV
dB
REF
Power Supply Rejection
P
SRR
60
UVLO
Under Voltage Lockout (turn-on)
Hysteresis
V
2.3
2.4
0.1
2.5
UVLOLH
V
V
HYS
V
− V
UVLOLH UVLOHL
Soft-Start Tim
SS time
tss
6
mS
Mode
Logic High
Logic Low
V
0.7 V
DD
IH
V
V
0.3 V
DD
IL
L
Input Current
I
−1.0
1.0
mA
SD, SYNC, PWM/PSM
Logic High
Logic Low
V
2.4
IH
V
V
0.8
1.0
IL
L
Input Current
I
−1.0
mA
Document Number: 70847
S-40701—Rev. C, 19-Apr-04
www.vishay.com
2
Si9166
Vishay Siliconix
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
Limits
Mina
Typb
Maxa
Unit
2.7 V v V , V v 6 V
Parameter
Oscillator
Symbol
DD
S
Maximum Frequency
Accuracy
F
2
MHz
%
OSC
Nominal 1.60 MHz, R
= 30 kW
−20
75
20
OSC
Maximum Duty Cycle—Buck
Maximum Duty Cycle—Boost
SYNC Range
F
= 2 MHz (non LDO mode)
85
65
sw
D
MAX
F
= 2 MHz
52
sw
F
/F
1.2
50
1.5
SYNC OSC
SYNC Low Pulse Width
SYNC High Pulse Width
50
ns
SYNC t , t
50
1
r
f
Error Amplifier
Input Bias Current
I
V
= 1.4 V
−1
50
mA
BIAS
FB
Open Loop Voltage Gain
A
60
1.30
1.30
2
dB
VOL
T
= 25_C
1.270
1.258
1.330
1.342
A
FB Threshold
Unity Gain BW
V
V
FB
BW
MHz
Source (V = 1.05 V), V
= 0.75 V
−3
−1
FB
COMP
Output Current
I
mA
dB
EA
Sink (V = 1.55 V), V
= 0.75 V
1
3
FB
COMP
Power Supply Rejection
PSRR
60
Output Drive (DH and DL)
Output High Voltage
Output Low Voltage
Peak Output Source
Peak Output Sink
V
V
= 3.3 V, I = −20 mA
OUT
3.18
500
3.24
0.06
−750
750
30
OH
S
V
V
V
= 3.3 V, I = 20 mA
OUT
0.12
OL
SOURCE
S
I
−500
V
S
= 3.3 V, DH = DL = V /2
mA
ns
S
I
SINK
Break-Before-Make
t
V = V = 3.3 V
S DD
BBM
Supply
Normal Mode
PSM Mode
V
= 3.3 V, F
= 2 MHz
500
180
750
250
1
DD
OSC
V
DD
= 3.3 V
I
mA
DD
Shutdown Mode
V
= 3.3 V, SD = 0 V
DD
Notes
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
Document Number: 70847
S-40701—Rev. C, 19-Apr-04
www.vishay.com
3
Si9166
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED)
V
REF
vs. Temperature
V
vs. V
REF
DD
1.32
1.31
1.30
1.29
1.28
1.310
1.305
1.300
1.295
1.290
−50
0
50
100
150
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Temperature (_C)
V
DD
− (V)
Frequency vs. Temperature
Frequency vs. R
OSC
10000
1000
100
2.00
1.95
1.90
1.85
1.80
1.75
1.70
R
OSC
= 25 kW
−100
−50
0
50
100
150
10
100
1000
Temperature (_C)
R
OSC
(kW)
Buck Mode Efficiency, V = 2.7 V
Boost Mode Efficiency, V = 3.6 V
O
O
100
90
100
90
PWM−3.3 V
PSM−3 V
PSM−3.3 V
PSM−2.7 V
PSM−3.3 V
PSM−3.6 V
PSM−3 V
80
80
PWM−3.3 V
PWM−3.6 V
PWM−2.7 V
PWM−3 V
PWM−3 V
70
60
70
60
50
50
1
10
100
1000
1
10
100
1000
Load Current (mA)
Load Current (mA)
Document Number: 70847
S-40701—Rev. C, 19-Apr-04
www.vishay.com
4
Si9166
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED)
PWM Supply Current
PSM Supply Current
800
700
600
500
400
300
200
250
200
150
100
50
2
3
4
5
6
7
2
3
4
5
6
7
V
DD
− (V)
V
DD
− (V)
PIN CONFIGURATION
TSSOP-16
ORDERING INFORMATION
V
MODE
SD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
Part Number
Temperature Range
Package
N/C
DH
DL
Si9166BQ-T1
−25 to 85_C
Tape and Reel
PWM/PSM
SYNC
PGND
Si9166BQ-T1—E3
V
O
GND
V
DD
Eval Kit
Temperature Range
Board Type
V
R
OSC
REF
Si9166DB
−25 to 85_C
Surface Mount
FB
COMP
Top View
PIN DESCRIPTION
Pin
Symbol
Description
1
2
V
Input supply voltage for the output driver section. Input voltage range is 2.7 V to 6V
Not Used
S
N/C
DH
The gate drive output for the high-side p-channel MOSFET. The p-channel MOSFET is the main switch for buck topology
and the synchronous rectifier for the boost topology.
3
4
5
PWM/PSM
SYNC
GND
Logic high = PWM mode, logic low = PSM mode. In PSM mode, synchronous rectification is disabled.
Externally controlled synchronization signal. Logic high to low transition forces the clock synchronization. If not used, the
pin must be connected to V , or logic high.
DD
6
7
Low power controller ground
V
REF
1.3-V reference. Decoupled with 0.1-mF capacitor
Output voltage feedback connected to the inverting input of an error amplifier.
Error amplifier output for external compensation network.
External resistor to determine the switching frequency.
Input supply voltage for the analog circuit. Input voltage range is 2.7 V to 6 V.
Direct output voltage sense
8
FB
9
COMP
10
11
12
13
R
OSC
V
DD
V
O
PGND
DL
Power ground for output drive stage
The gate drive output for the low-side n-channel MOSFET. The n-channel MOSFET is the synchronous rectifier for the buck
topology and the main switch for the boost topology.
14
15
16
SD
Shuts down the IC completely and decreases current consumed by the IC to < 1 mA.
MODE
Determines the converter topology. Connect to AGND for Buck or V for Boost.
DD
Document Number: 70847
S-40701—Rev. C, 19-Apr-04
www.vishay.com
5
Si9166
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
V
DD
SD
Positive
Supply
1.3 V
Reference
Bias
Soft-Start
Timer
UVLO
POR
Generator
Threshold
Generator
SYSTEM MONITOR
V
REF
V
S
FB
COMP
PWM
Modulator
PWM
IN
DH
1.0 V
Ramp
PWM
EN
0.5 V
Drivers
PSM
SYNC
PWM/PSM
Select
Oscillator
OSC
DL
IN
R
OSC
PSM
EN
C
PSM
Modulator
PGND
V
O
PWM/PSM
MODE
Negative
Return and
Substrate
GND
DETAIL OPERATIONAL DESCRIPTION
Start-Up
will always soft start in the PWM mode regardless of the
voltage level on the PWM/PSM pin.
The UVLO circuit prevents the controller output driver and
oscillator circuit from turning on, if the voltage on VDD pin is less
than 2.5 V. With typical UVLO hysteresis of 0.1 V, controller is
continuously powered on until the VDD voltage drops below
2.4 V. This hysteresis prevents the converter from oscillating
during the start-up phase and unintentionally locking up the
system. Once the VDD voltage exceeds the UVLO threshold,
and with no other shutdown condition detected, an internal
power-on-reset timer is activated while most circuitry, except
the output driver, are turned on. After the POR time-out of
about 1 ms, the internal soft-start capacitor is allowed to
charge. When the soft-start capacitor voltage reaches 0.5 V,
the PWM circuit is enabled. Thereafter, the constant current
charging the soft-start capacitor will force the converter output
voltage to rise gradually without overshooting. To prevent
negative undershoot, the synchronous switch is tri-stated until
the duty cycle reaches about 10%. See start-up timing
diagram. In tri-state, the high-side p-channel MOSFET is
turned off by pulling up the gate voltage (DH) to VS potential.
The low-side n-channel MOSFET is turned off by pulling down
the gate voltage (DL) to PGND potential. Note that the Si9166
Shutdown
The Si9166 is designed to conserve battery life by decreasing
current consumption of IC during normal operation as well as
the shutdown mode. With logic low-level on the SD pin, current
consumption of the Si9166 decreases to less than 1 mA by
shutting off most of the circuits. The logic high enables the
controller and starts up as described in Start-Up section
above.
MODE Selection
The Si9166 can be programmed to operate as Buck or Boost
converter. If the MODE pin is connected to AGND, it operates
in buck mode. If the MODE pin is connected to VDD, it operates
in boost mode. The DH gate drive output is designed to drive
high-side p-channel MOSFET, acting as the main switch in
buck topology and the synchronous rectifier in boost topology.
The DL gate drive output is designed to drive low-side
n-channel MOSFET, acting as the synchronous rectifier in
buck topology and the main switch in boost topology.
Document Number: 70847
S-40701—Rev. C, 19-Apr-04
www.vishay.com
6
Si9166
Vishay Siliconix
PWM Mode
Pulse Skipping Mode
With PWM/PSM mode pin in logic high condition, the Si9166
operates in constant frequency (PWM) mode. As the load and
line varies, switching frequency remain constant. The
switching frequency is programmed by the ROSC value. In the
PWM mode, the synchronous drive is always enabled, even
when the output current reaches 0 A. Therefore, the converter
always operates in continuous conduction mode (CCM) if a
synchronous switch is used. In CCM, transfer function of the
converter remains almost constant, providing fast transient
The gate charge losses produced from the Miller capacitance
of MOSFETs are the dominant power dissipation parameter
during light load (i.e. < 10 mA). Therefore, less gate switching
will improve overall converter efficiency. This is exactly why
the Si9166 is designed with pulse skipping mode. If the
PWM/PSM pin is connected to logic low level, converter
operates in pulse skipping modulation (PSM) mode. During
the pulse skipping mode, quiescent current of the controller is
decreased to approximately 200 mA, instead of 500 mA during
the PWM mode. This is accomplished by turning off most of
internal control circuitry and utilizing a simple constant on-time
control with feedback comparator. The controller is designed
to have a constant on-time and a minimum off-time acting as
the feedback comparator blanking time. If the output voltage
drops below the desired level, the main switch is first turned on
and then off. If the applied on-time is insufficient to provide the
desired voltage, the controller will force another on and off
sequence, until the desired voltage is accomplished. If the
applied on-time forces the output to exceed the desired level,
as typically found in the light load condition, the converter stays
off. The excess energy is delivered to the output slowly, forcing
the converter to skip pulses as needed to maintain regulation.
The on-time and off-time are set internally based on inductor
used (1.5-mH typical), MODE pin selection and maximum load
current. Therefore, with this control method, duty cycle
ranging from 0 to near 100% is possible depending on whether
buck or boost is chosen. In pulse skipping mode, synchronous
rectifier drive is also disabled to further decrease the gate
charge loss and increase overall converter efficiency.
response.
If the converter operates in discontinuous
conduction mode (DCM), overall loop gain decreases and
transient response time can be ten times longer than if the
converter remain in continuous current mode. This transient
response time advantage can significantly decrease the
hold-up capacitors needed on the output of dc/dc converter to
meet the transient voltage regulation. The PWM/PSM pin is
available to dynamically program the controller. If the
synchronous rectifier switch is not used, the converter will
operate in DCM at light load.
The maximum duty cycle of the Si9166 can reach 100% in
buck mode. The duty cycle will continue to increase as the
input voltage decreases until it reaches 100%. This allows the
system designers to extract the maximum stored energy from
the battery. Once the controller delivers 100% duty cycle, the
converter operates like a saturated linear regulator. At 100%
duty cycle, synchronous rectification is completely turned off.
Up to 80% maximum duty cycle at 2-MHz switching frequency,
the controller maintains perfect output voltage regulation. If the
input voltage drops below the level where the converter
requires greater than 80% duty cycle, the controller will deliver
100% duty cycle. This instantaneous jump in duty cycle is due
to fixed BBM time, MOSFET delay/rise/fall time, and the
internal propagational delays. In order to maintain regulation,
controller might fluctuate its duty cycle back and forth from
100% to something lower than 80% while the converter is
operating in this input voltage range. If the input voltage drops
further, controller will remain on 100%. If the input voltage
increases to a point where it’s requiring less than 80% duty
cycle, synchronous rectification is once again activated.
Reference
The reference voltage for the Si9166 is set at 1.3 V. The
reference voltage is internally connected to the non-inverting
inputs of the error amplifier. The reference pin requires 0.1-mF
decoupling capacitor.
Error Amplifier
The maximum duty cycle under boost mode is internally limited
to 70% to prevent inductor saturation. If the converter is turned
on for 100% duty cycle, inductor never gets a chance to
discharge its energy and eventually saturate. In boost mode,
synchronous rectifier is always turned on for minimum or
greater duration as long as the switch has been turned on. The
controller will deliver 0% duty cycle, if the input voltage is
greater than the programmed output voltage. Because of
signal propagation time and MOSFET delay/rise/fall time,
controller will not transition smoothly from minimum
controllable duty cycle to 0% duty cycle. For example,
controller may decrease its duty cycle from 5% to 0% abruptly,
instead of gradual decrease you see from 70% to 5%.
The error amplifier gain-bandwidth product and slew rate are
critical parameters which determines the transient response of
converter. The transient response is function of both small and
large signal responses. The small signal response is
determined by the feedback compensation network while the
large signal is determined by the error amplifier dv/dt and the
inductor di/dt slew rate. Besides the inductance value, error
amplifier determines the converter response time. In order to
minimize the response time, the Si9166 is designed with
2-MHz error amplifier gain-bandwidth product to generate the
widest converter bandwidth and 3.5 V/msec slew rate for
ultra-fast large signal response.
Document Number: 70847
S-40701—Rev. C, 19-Apr-04
www.vishay.com
7
Si9166
Vishay Siliconix
break-before-make time is set internally at 20 to 60 ns @
VS = 3.6 V. The high- and low-side gate drive voltages are
monitored and when the gate to source voltage reaches
1.75 V above or below the initial starting voltage, 20 to 60 ns
BBM time is set before the other gate drive transitions to its
proper state. The maximum and minimum duty cycle is limited
by the BBM time. Since the BBM time is fixed, controllable
maximum duty cycle will vary depending on the switching
frequency.
Oscillator
The oscillator is designed to operate up to 2-MHz minimal. The
2-MHz operating frequency allows the converter to minimize
the inductor and capacitor size, improving the power density
of the converter. Even with 2-MHz switching frequency,
quiescent current is only 500 mA with unique power saving
circuit design. The switching frequency is easily programmed
by attaching resistor to ROSC pin. See oscillator frequency
versus ROSC curve to select the proper timing values for
desired operating frequency. The tolerance on the operating
frequency is (20% with 1% tolerance resistor).
Synchronization
Output Driver Stage
The synchronization to external clock is easily accomplished
by connecting the external clock into the SYNC pin. The logic
high-to-low transition synchronizes the clock. The external
clock frequency must be within 1.2 to 1.5 times the internal
clock frequency.
The DH pin is designed to drive the high-side p-channel
MOSFET, independent of topology. The DL pin is designed to
drive the low-side n-channel MOSFET, independent of
topology. The driver stage is sized to sink and source peak
currents up to 450 mA with VS = 3.3 V. The ringing from the
gate drive output trace inductance can produce negative
voltage on the DH and DL respect to PGND. The gate drive
circuit is capable of withstanding these negative voltages
without any functional defects.
Break-Before-Make Timing
A proper BBM time is essential in order to prevent
shoot-through current and to maintain high efficiency. The
Document Number: 70847
S-40701—Rev. C, 19-Apr-04
www.vishay.com
8
Legal Disclaimer Notice
Vishay
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc.,
or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's
terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express
or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness
for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000
Revision: 08-Apr-05
www.vishay.com
1
Package Information
Vishay Siliconix
TSSOP: 16-LEAD
DIMENSIONS IN MILLIMETERS
Symbols
Min
-
Nom
1.10
0.10
1.00
0.28
0.127
5.00
6.40
4.40
0.65
0.60
1.00
-
Max
1.20
0.15
1.05
0.38
-
A
A1
A2
B
0.05
-
0.22
-
C
D
4.90
6.10
4.30
-
5.10
6.70
4.50
-
E
E1
e
L
0.50
0.90
-
0.70
1.10
0.10
6°
L1
y
θ1
0°
3°
ECN: S-61920-Rev. D, 23-Oct-06
DWG: 5624
Document Number: 74417
23-Oct-06
www.vishay.com
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Legal Disclaimer Notice
Vishay
Disclaimer
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Document Number: 91000
Revision: 11-Mar-11
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