SI9434ADY [VISHAY]
Transistor,;
| 型号： | SI9434ADY |
| 厂家： | 
VISHAY |
| 描述： | Transistor, |
| 文件： | 总3页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model Si9434BDY
Vishay Siliconix
P-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0 to 5V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 73104
12-Aug-04
www.vishay.com
1
SPICE Device Model Si9434BDY
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated Measured
Parameter
Symbol
Test Conditions
Unit
Data
Data
Static
Gate Threshold Voltage
On-State Drain Current a
VGS(th)
ID(on)
0.80
156
V
A
V
DS = VGS, ID = −250 µA
VDS = −5 V, VGS = −4.5 V
0.034
0.043
15
0.033
0.044
10
VGS = −4.5 V, ID = −6.3 A
VGS = −2.5 V, ID = −5.1 A
Drain-Source On-State Resistance a
rDS(on)
Ω
Forward Transconductance a
Diode Forward Voltage a
gfs
S
V
VDS = −5 V, ID = −6.3 A
VSD
I
S = −2.6 A, VGS = 0 V
−0.80
−0.80
Dynamic b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Qg
Qgs
Qgd
td(on)
tr
11.6
1.7
3.5
16
12
1.7
3.5
15
45
80
60
nC
ns
V
DS = −10 V, VGS = −4.5 V, ID = −6.3 A
13
VDD = −10 V, RL = 10 Ω
I
D ≅ −1 A, VGEN = −4.5 V, RG = 6 Ω
Turn-Off Delay Time
Fall Time
td(off)
tf
83
9
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
www.vishay.com
2
Document Number: 73104
12-Aug-04
SPICE Device Model Si9434BDY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 73104
12-Aug-04
www.vishay.com
3
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