SIC639_技术文档

SiC639, SiC639A

www.vishay.com

Vishay Siliconix

50 A VRPower^®Integrated Power Stage

DESCRIPTION

FEATURES

• Thermally enhanced PowerPAK^®MLP55-31L

package

The SiC639 are integrated power stage solutions optimized

for synchronous buck applications to offer high current, high

efficiency, and high power density performance. Packaged

in Vishay’s proprietary 5 mm x 5 mm MLP package, SiC639

enables voltage regulator designs to deliver up to 50 A

continuous current per phase.

• Vishay’s Gen IV MOSFET technology and a low

side MOSFET with integrated Schottky diode

• Delivers up to 50 A continuous current

• High efficiency performance

The internal power MOSFETs utilizes Vishay’s

state-of-the-art Gen IV TrenchFET^®technology that delivers

industry benchmark performance to significantly reduce

switching and conduction losses.

• High frequency operation up to 1.5 MHz

• Power MOSFETs optimized for 19 V input stage

• 3.3 V, 5 V PWM logic with tri-state and hold-off

• Zero current detect control for light load efficiency

improvement

The SiC639 incorporate an advanced MOSFET gate driver

IC that features high current driving capability, adaptive

dead-time control, an integrated bootstrap Schottky diode,

a thermal warning (THWn) that alerts the system of

excessive junction temperature, and zero current detection

to improve light load efficiency. The drivers are also

compatible with a wide range of PWM controllers and

supports tri-state PWM, 3.3 V, 5 V PWM logic.

• Low PWM propagation delay (< 20 ns)

• Faster disable

• Thermal monitor flag

• Under voltage lockout for V_CIN

• Material categorization: for definitions of compliance

please see www.vishay.com/doc?99912

APPLICATIONS

• Multi-phase VRDs for computing, graphics card and

memory

• Intel IMVP-8/9 VRPower delivery

- V_CORE, V_GRAPHICS, V_SYSTEM

platforms

Skylake, Kabylake

AGENT

- V_CCGIfor Apollo Lake platforms

• Up to 24 V rail input DC/DC VR modules



TYPICAL APPLICATION DIAGRAM

5 V

Input

BOOT

PHASE

V_CIN

ZCD_EN#

Output

SW

DSBL#

Gate

PWM

controller

driver

PWM

THWn

Fig. 1 - SiC639 and SiC639A Typical Application Diagram

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PINOUT CONFIGURATION

33

GL

31 30 29 28 27 26 25 24

24 25 26 27 28 29 30 31

1

PWM

23 V_SWH

22 V_SWH

V_SWH23

V_SWH22

V_SWH21

GL

ZCD_EN# 2

2 ZCD_EN#

32

C_GND

CGND

V_CIN

3

4

3

4

21 V_SWH

20 V_SWH

C_GND

BOOT

C_GND

V

_SWH20

35

P_GND

BOOT 5

5

6

19 V_SWH

18 V_SWH

17 V_SWH

16 V_SWH

V_SWH19

PGND

6

7

8

N.C.

PHASE

V_IN

N.C.

V

_SWH18

_SWH17

34

V_IN

VIN

7

PHASE

V_SWH16

8 V_IN

9

10 11

12 13 14 15

15 14 13 12

11 10

9

Top view

Bottom view

Fig. 2 - SiC639 Pin Configuration

PIN CONFIGURATION

PIN NUMBER

NAME

FUNCTION

1

PWM

PWM input logic

The ZCD_EN# pin enables or disables zero cross detection on inductor current when it detects

PWM = mid.

When ZCD_EN# is LOW, GL stays on until ZCD detected when it detects PWM = mid.

When ZCD_EN# is HIGH, GL turns off when it detects PWM = mid.or PWM = 1

2

ZCD_EN#

3

V_CIN

C_GND

BOOT

N.C.

Supply voltage for internal logic circuitry

Signal ground

4, 32

5

High side driver bootstrap voltage

Not connected internally, can be left floating or connected to ground

Return path of high side gate driver

Power stage input voltage. Drain of high side MOSFET

Power ground

6

7

8 to 11, 34

12 to 15, 28, 35

16 to 26

27, 33

PHASE

V_IN

P_GND

V_SWH

GL

Phase node of the power stage

Low side MOSFET gate signal

29

V_DRV

Supply voltage for internal gate driver

Thermal warning open drain output

Disable pin. Active low

30

THWn

DSBL#

31

ORDERING INFORMATION

PART NUMBER

SiC639CD-T1-GE3

SiC639ACD-T1-GE3

SiC639DB

PACKAGE

MARKING CODE

SiC639

OPTION

PowerPAK MLP55-31L

5 V PWM optimized

3.3 V PWM optimized

SiC639A

Reference board

S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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SiC639, SiC639A

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PART MARKING INFORMATION

=

pin 1 indicator

P/N

part number code

Siliconix logo

ESD symbol

P/N

LL

F

assembly factory code

year code

Y

F Y W W

WW

LL

week code

lot code

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL PARAMETER

CONDITIONS

LIMIT

-0.3 to +30

-0.3 to +7

-0.3 to +30

-7 to +35

35

UNIT

Input voltage

V_IN

V_CIN

V_DRV

Control logic supply voltage

Drive supply voltage

Switch node (DC voltage)

Switch node (AC voltage) ⁽¹⁾

BOOT voltage (DC voltage)

BOOT voltage (AC voltage) ⁽²⁾

BOOT to PHASE (DC voltage)

BOOT to PHASE (AC voltage) ⁽³⁾

V_SWH

V_BOOT

V

40

-0.3 to +7

-0.3 to +8

V_BOOT-PHASE

All logic inputs and outputs

(PWM, DSBL#, and THWn)

-0.3 to V_CIN+ 0.3

Max. operating junction temperature

Ambient temperature

T_J

T_A

150

-40 to +125

-65 to +150

3000

°C

V

Storage temperature

T_stg

Human body model, JESD22-A114

Charged device model, JESD22-C101

Electrostatic discharge protection

1000

Notes

•

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability

The specification values indicated “AC” is V_SWHto P_GND-8 V (< 20 ns, 10 μJ), min. and 35 V (< 50 ns), max.

The specification value indicates “AC voltage” is V_BOOTto P_GND, 40 V (< 50 ns) max.

(1)

(2)

(3)

The specification value indicates “AC voltage” is V_BOOTto V_PHASE, 8 V (< 20 ns) max.

RECOMMENDED OPERATING RANGE

ELECTRICAL PARAMETER

MINIMUM

TYPICAL

MAXIMUM

UNIT

Input voltage (V_IN)

2.7

4.5

4

-

5

24

5.5

-

Drive supply voltage (V_DRV

)

V

Control logic supply voltage (V_CIN

)

5

BOOT to PHASE (V_BOOT-PHASE, DC voltage)

Thermal resistance from junction to ambient

Thermal resistance from junction to case

4.5

10.6

1.6

-

°C/W

-

S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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ELECTRICAL SPECIFICATIONS

(DSBL# = ZCD_EN# = 5 V, V_IN= 12 V, V_DRVand V_CIN= 5 V, T_A= 25 °C)

LIMITS

UNIT

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

POWER SUPPLY

V_DSBL#= 0 V, no switching, V_PWM= FLOAT

-

5

300

350

9

-

Control logic supply current

Drive supply current

I_VCIN

V_DSBL#= 5 V, no switching, V_PWM= FLOAT

μA

V

_DSBL#= 5 V, f_S= 300 kHz, D = 0.1

f_S= 300 kHz, D = 0.1

-

14

-

mA

μA

f_S= 1 MHz, D = 0.1

30

15

55

I_VDRV

V_DSBL#= 0 V, no switching

-

V_DSBL#= 5 V, no switching

-

BOOTSTRAP SUPPLY

Bootstrap diode forward voltage

PWM CONTROL INPUT (SiC639)

Rising threshold

V_F

I_F= 2 mA

0.4

V

V_{TH_PWM_R}

V_{TH_PWM_F}

V_{TRI_FLOAT}

V_{TRI_WINDOW}

V_{HYS_TRI_R}

-

4.2

Falling threshold

0.72

-

2.3

-

V

Tri-state voltage

V_PWM= FLOAT

-

Tri-state window

1.38

3

Tri-state rising threshold hysteresis

-

225

325

-

mV

μA

Tri-state falling threshold hysteresis V_{HYS_TRI_F}

-

V_PWM= 5 V, DSBL# = high

350

1

V

_PWM= 5 V, DSBL# = low

_PWM= 0 V, DSBL# = high

_PWM= 0 V, DSBL# = low

-

PWM input current

I_PWM

V

-

-350

-1

V

-

PWM CONTROL INPUT (SiC639A)

Rising threshold

V_{TH_PWM_R}

V_{TH_PWM_F}

V_{TRI_FLOT}

-

2.7

Falling threshold

0.72

-

1.8

-

V

Tri-state voltage

V_PWM= FLOAT

-

Tri-state window

V_{TRI_WINDOW}

V_{HYS_TRI_R}

1.38

1.95

-

Tri-state rising threshold hysteresis

-

250

300

-

mV

μA

Tri-state falling threshold hysteresis V_{HYS_TRI_F}

-

V_PWM= 3.3 V, DSBL# = high

_PWM= 3.3 V, DSBL# = low

_PWM= 0 V, DSBL# = high

_PWM= 0 V, DSBL# = low

225

1

V

-

PWM input current

I_PWM

V

-

-225

-1

V

-

TIMING SPECIFICATIONS

Tri-state to GH/GL rising

propagation delay

t_{PD_TRI_R}

-

30

-

Tri-state GH hold-off time

Tri-state GL hold-off time

GH - turn off propagation delay

t_{TSHO_GH}

t_{TSHO_GL}

-

35

130

15

-

t_{PD_OFF_GH}

No load, see Fig. 4

GH - turn on propagation delay

(dead time rising)

t_{PD_ON_GH}

t_{PD_OFF_GL}

t_{PD_ON_GL}

-

10

13

10

-

ns

GL - turn off propagation delay

GL - turn on propagation delay

(dead time falling)

DSBL# Lo to GH/GL falling

propagation delay

t_{PD_DSBL#_F}

Fig. 5

-

15

-

PWM minimum on-time

t_{PWM_ON_MIN}

30

S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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SiC639, SiC639A

www.vishay.com

Vishay Siliconix

ELECTRICAL SPECIFICATIONS

(DSBL# = ZCD_EN# = 5 V, V_IN= 12 V, V_DRVand V_CIN= 5 V, T_A= 25 °C)

LIMITS

UNIT

PARAMETER

SYMBOL

TEST CONDITION

MIN.

TYP.

MAX.

DSBL# ZCD_EN# INPUT

DSBL# logic input voltage

V_{IH_DSBL#}

V_{IL_DSBL#}

V_{IH_ZCD_EN#}

V_{IL_ZCD_EN#}

Input logic high

Input logic low

Input logic high

Input logic low

2

-

0.8

-

V

2

-

ZCD_EN# logic input voltage

PROTECTION

0.8

V_CINrising, on threshold

-

2.7

-

3.7

3.1

4.1

Under voltage lockout

V_UVLO

V

V_CINfalling, off threshold

-

Under voltage lockout hysteresis

THWn flag set ⁽²⁾

THWn flag clear ⁽²⁾

V_{UVLO_HYST}

T_{THWn_SET}

T_{THWn_CLEAR}

T_{THWn_HYST}

V_{OL_THWn}

575

160

135

25

mV

-

°C

V

THWn flag hysteresis ⁽²⁾

-

THWn output low

I_THWn= 2 mA

-

0.02

Notes

(1)

Typical limits are established by characterization and are not production tested

Guaranteed by design

(2)

DETAILED OPERATIONAL DESCRIPTION

PWM Input with Tri-State Function

Diode Emulation Mode (ZCD_EN#)

The PWM input receives the PWM control signal from the VR

controller IC. The PWM input is designed to be compatible

with standard controllers using two state logic (H and L) and

advanced controllers that incorporate tri-state logic (H, L

and tri-state) on the PWM output. For two state logic, the

PWM input operates as follows. When PWM is driven above

V_{PWM_TH_R}the low side is turned off and the high side is

turned on. When PWM input is driven below V_{PWM_TH_F}the

high side is turned off and the low side is turned on. For

tri-state logic, the PWM input operates as previously stated

for driving the MOSFETs when PWM is logic high and logic

low. However, there is a third state that is entered as the

PWM output of tri-state compatible controller enters its high

impedance state during shut-down. The high impedance

state of the controller’s PWM output allows the SiC639 and

SiC639A to pull the PWM input into the tri-state region (see

definition of PWM logic and tri-state, Fig. 4). If the PWM

input stays in this region for the tri-state hold-off period,

tTSHO, both high side and low side MOSFETs are turned

off. The function allows the VR phase to be disabled without

negative output voltage swing caused by inductor ringing

and saves a Schottky diode clamp. The PWM and tri-state

regions are separated by hysteresis to prevent false

triggering.

When ZCD_EN# pin is driven below V_{IL_ZCD_EN#}diode

emulation mode is enabled. If the PWM input is wi thin the

tri-state window for longer than the tri-state hold off time,

then the low side MOSFET is under control of the ZCD (zero

crossing detect) comparator. In this mode, the LS MOSFET

is turned off if the inductor current is < or = 0. Light load

efficiency is improved by avoiding discharge of output

capacitors. If ZCD_EN# is high, diode emulation mode is

disabled. In this mode if PWM enters tri-state, the device will

go into tri-state mode after tri-state delay and both the high

side and low side MOSFETs will be turned off.

Thermal Shutdown Warning (THWn)

The THWn pin is an open drain signal that flags the presence

of excessive junction temperature. Connect with

a

maximum of 20 k, to V_CIN. An internal temperature sensor

detects the junction temperature. The temperature

threshold is 160 °C. When this junction temperature is

exceeded the THWn flag is set. When the junction

temperature drops below 135 °C the device will clear the

THWn signal. The SiC639 and SiC639A do not stop

operation when the flag is set. The decision to shutdown

must be made by an external thermal control function.

Voltage Input (V_IN)

Disable (DSBL#)

This is the power input to the drain of the high side power

MOSFET. This pin is connected to the high power

intermediate BUS rail.



In the low state, the DSBL# pin shuts down the driver IC

and disables both high-side and low side MOSFETs.

WhenDSBL# is low, the PWM resistor divider is also

disconnected. In this state, standby current is minimized. If

DSBL# is left unconnected, an internal pull-down resistor

will pull the pin to C_GNDand shut down the IC.



S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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SiC639, SiC639A

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Switch Node (V_SWHand PHASE)

Bootstrap Circuit (BOOT)

The switch node, V_SWH, is the circuit power stage output.

This is the output applied to the power inductor and output

filter to deliver the output for the buck converter. The PHASE

pin is internally connected to the switch node V_SWH. This pin

is to be used exclusively as the return pin for the BOOT

capacitor. A 20 k resistor is connected between GH

(the high side gate) and PHASE to provide a discharge path

for the HS MOSFET in the event that V_CINgoes to zero while

The internal bootstrap diode and an external bootstrap

capacitor form a charge pump that supplies voltage to the

BOOT pin. An integrated bootstrap diode is incorporated so

that only an external capacitor is necessary to complete the

bootstrap circuit. Connect a boot strap capacitor with one

leg tied to BOOT pin and the other tied to PHASE pin.

Shoot-Through Protection and Adaptive Dead Time

The SiC639 and SiC639A have an internal adaptive logic to

avoid shoot through and optimize dead time. The shoot

through protection ensures that both high side and low side

MOSFETs are not turned on at the same time. The adaptive

dead time control operates as follows. The high side and low

side gate voltages are monitored to prevent the MOSFET

turning on from tuning on until the other MOSFET’s gate

voltage is sufficiently low (< 1 V). Built in delays also ensure

that one power MOSFET is completely off, before the other

can be turned on. This feature helps to adjust dead time as

gate transitions change with respect to output current and

temperature.

V

_INis still applied.

Ground Connections (C_GNDand P_GND

)

P_GND(power ground) should be externally connected

to C_GND(signal ground). The layout of the printed circuit

board should be such that the inductance separating C_GND

and P_GNDis minimized. Transient differences due to

inductance effects between these two pins should not

exceed 0.5 V

Control and Drive Supply Voltage Input (V_DRV, V_CIN

)

V

_CINis the bias supply for the gate drive control IC. V_DRVis

the bias supply for the gate drivers. It is recommended to

separate these pins through a resistor. This creates a low

pass filtering effect to avoid coupling of high frequency gate

drive noise into the IC.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate

drive holding high side and low side MOSFET gates low

until the supply voltage rail has reached a point at which

the logic circuitry can be safely activated. The SiC639,

SiC639A also incorporates logic to clamp the gate drive

signals to zero when the UVLO falling edge triggers the

shutdown of the device. As an added precaution, a 20 k

resistor is connected between GH (the high side gate) and

PHASE to provide a discharge path for the HS MOSFET.



FUNCTIONAL BLOCK DIAGRAM

THWn

BOOT

V_IN

V_DRV

Thermal monitor

& warning

V_CIN

UVLO

DISB#

V_CIN

-

+

GL

20K

PHASE

SW

PWM logic

control &

state

Anti-cross

conduction

control

V_ref= 1 V

DISB

-

+

machine

logic

V

_ref= 1 V

PWM

C_GND

V_DRV

SW

P_GND

ZCD_EN#

GL

Fig. 3 - SiC639 Functional Block Diagram

S20-0485-Rev. B, 29-Jun-2020

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DEVICE TRUTH TABLE

DSBL#

ZCD_EN#

PWM

GH

GL

H

L

H

L

H, I_L> 0 A

L, I_L< 0 A

H

L

H to mid

L

H

L

L to mid

L

H

L

H

L

X

H

L

H

L

H

mid

L



PWM TIMING DIAGRAM

Fig. 4 - Timing Diagram



DSBL# PROPAGATION DELAY

PWM

Disable

DSBL#

GH

GL

GH

GL

t

DSBL#Low to GH Falling Propagation Delay

DSBL# Low to GL Falling Propagation Delay

Fig. 5 - DSBL# Falling Propagation Delay

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ELECTRICAL CHARACTERISTICS

Test condition: V_IN= 13 V, DSBL# = V_DRV= V_CIN= 5 V, ZCD_EN# = 5 V, V_OUT= 1 V, L_OUT= 250 nH (DCR = 0.32 m), T_A= 25 °C,

natural convection cooling (All power loss and normalized power loss curves show SiC639 and SiC639A losses only unless otherwise stated)

55

50

45

40

35

30

25

20

15

94

90

86

82

78

74

70

66

62

500 kHz

750 kHz

500 kHz

1 MHz

Complete converter efﬁciency

_IN= [(V_INx I_IN) + 5 V x (I_VDRV+ I_VCIN)]

_OUT= V_OUTx I_OUT, measured at output capacitor

P

0

15 30 45 60 75 90 105 120 135 150

0

5

10 15 20 25 30 35 40 45 50

Output Current, I_OUT(A)

PCB Temperature, T_PCB(°C)

Fig. 6 - Efficiency vs. Output Current (V_IN= 12.6 V)

Fig. 9 - Safe Operating Area

5.0

16.0

14.0

12.0

10.0

8.0

I_OUT= 25A

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

1 MHz

750 kHz

6.0

4.0

500 kHz

2.0

0.0

0

5

10

15

20

25

30

35

40

45

200 300 400 500 600 700 800 900 1000 1100

Output Current, I_OUT(A)

Switching Frequency, fs (KHz)

Fig. 7 - Power Loss vs. Switching Frequency (V_IN= 12.6 V)

Fig. 10 - Power Loss vs. Output Current (V_IN= 12.6 V)

94

98

500 kHz

94

90

86

90

86

82

750 kHz

82

750 kHz

1 MHz

78

1 MHz

78

74

70

Complete converter efﬁciency

P

_IN= [(V_INx I_IN) + 5 V x (I_VDRV+ I_VCIN)]

_OUT= V_OUTx I_OUT, measured at output capacitor

P_IN= [(V_INx I_IN) + 5 V x (I_VDRV+ I_VCIN)]

66

62

66

P

_OUT= V_OUTx I_OUT, measured at output capacitor

62

0

5

10 15 20 25 30 35 40 45 50

Output Current, I_OUT(A)

0

5

10 15 20 25 30 35 40 45 50

Output Current, I_OUT(A)

Fig. 8 - Efficiency vs. Output Current (V_IN= 9 V)

Fig. 11 - Efficiency vs. Output Current (V_IN= 19 V)

S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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SiC639, SiC639A

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ELECTRICAL CHARACTERISTICS

Test condition: V_IN= 13 V, DSBL# = V_DRV= V_CIN= 5 V, ZCD_EN# = 5 V, V_OUT= 1 V, L_OUT= 250 nH (DCR = 0.32 m), T_A= 25 °C,

natural convection cooling (All power loss and normalized power loss curves show SiC639 and SiC639A losses only unless otherwise stated)

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

4.2

4.0

3.8

3.6

3.4

3.2

3.0

2.8

2.6

I_F= 2 mA

V_{UVLO_RISING}

V_{UVLO_FALLING}

-60 -40 -20

0

20 40 60 80 100 120 140

-60 -40 -20

0

20 40 60 80 100 120 140

Temperature (°C)

Fig. 12 - UVLO Threshold vs. Temperature

Fig. 15 - Boot Diode Forward Voltage vs. Temperature

3.20

2.85

2.50

2.15

1.80

1.45

1.10

0.75

0.40

2.85

2.50

2.15

1.80

1.45

1.10

0.75

0.40

V_{TH_PWM_R}

V_{TRI_TH_F}

V_{TH_PWM_R}

V_{TRI_TH_F}

V_TRI

V_{TRI_TH_R}

V_{TH_PWM_F}

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

-60 -40 -20

0

20 40 60 80 100 120 140

Temperature (°C)

Driver Supply Voltage, V_CIN(V)

Fig. 13 - PWM Threshold vs. Temperature (SiC639A)

Fig. 16 - PWM Threshold vs. Driver Supply Voltage (SiC639A)

5.00

5.0

4.50

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_{TH_PWM_R}

4.00

3.50

V_{TRI_TH_F}

3.00

V_TRI

2.50

2.00

1.50

V_{TRI_TH_R}

1.00

V_{TH_PWM_F}

0.50

0

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

-60 -40 -20

0

20 40 60 80 100 120 140

Driver Supply Voltage, V_CIN(V)

Temperature (°C)

Fig. 14 - PWM Threshold vs. Temperature (SiC639)

Fig. 17 - PWM Threshold vs. Driver Supply Voltage (SiC639)

S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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ELECTRICAL CHARACTERISTICS

Test condition: V_IN= 13 V, DSBL# = V_DRV= V_CIN= 5 V, ZCD_EN# = 5 V, V_OUT= 1 V, L_OUT= 250 nH (DCR = 0.32 m), T_A= 25 °C,

natural convection cooling (All power loss and normalized power loss curves show SiC639 and SiC639A losses only unless otherwise stated)

2.20

2.00

1.80

1.60

1.40

1.20

1.00

0.80

0.60

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

V_{IH_DSBL#}

V_{IH_ZCD_EN#_R}

V_{IL_ZCD_EN#_F}

V_{IL_DSBL#}

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

-60 -40 -20

0

20 40 60 80 100 120 140

Temperature (°C)

Driver Supply Voltage, V_CIN(V)

Fig. 18 - DSBL# Threshold vs. Temperature

Fig. 21 - ZCD_EN# Threshold vs. Driver Supply Voltage

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

8

V_DSBL#= 0 V

V_{IH_DSBL#}

7

6

5

4

3

2

1

0

V_{IL_DSBL#}

4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5

-60 -40 -20

0

20 40 60 80 100 120 140

Driver Supply Voltage, V_CIN(V)

Temperature (°C)

Fig. 19 - DSBL# vs. Driver Input Voltage

Fig. 22 - Driver Shutdown Current vs. Temperature

10.8

10.7

10.6

10.5

10.4

10.3

10.2

10.1

10.0

340

330

320

310

300

290

280

270

260

V_PWM= FLOAT

-60 -40 -20

0

20 40 60 80 100 120 140

-60 -40 -20

0

20 40 60 80 100 120 140

Temperature (°C)

Fig. 20 - DSBL# Pull-Down Current vs. Temperature

Fig. 23 - Driver Supply Current vs. Temperature

Document Number: 76585

S20-0485-Rev. B, 29-Jun-2020

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SiC639, SiC639A

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Vishay Siliconix

PCB LAYOUT RECOMMENDATIONS

Step 1: V_IN/GND Planes and Decoupling

Step 3: V_CIN/V_DRVInput Filter

V_SWH

C_VDRV

P

G

N

D

P_GND

C_VCIN

V_IN

C_GND

V_INplane

P_GNDplane

1. Layout V_INand P_GNDplanes as shown above

1. The V_CIN/V_DRVinput filter ceramic cap should be placed

very close to IC. It is recommended to connect two caps

separately

2. Ceramic capacitors should be placed right between V_IN

and P_GND, and very close to the device for best

decoupling effect

2. C_VCINcap should be placed between pin 3 and pin 4

(C_GNDof driver IC) to achieve best noise filtering

3. Difference values / packages of ceramic capacitors

should be used to cover entire decoupling spectrum e.g.

1210, 0805, 0603, and 0402

3. C_VDRVcap should be placed between pin 28 (P_GNDof

driver IC) and pin 29 to provide maximum instantaneous

driver current for low side MOSFET during switching

cycle

4. Smaller capacitance value, closer to device V_INpin(s)

- better high frequency noise absorbing

4. For connecting C_VCINanalog ground, it is recommended

to use large plane to reduce parasitic inductance

Step 2: V_SWHPlane

Step 4: BOOT Resistor and Capacitor Placement

V

VSWH

SWH

C_BOOT

R_BOOT

P_GNDplane

PGND Plane

1. Connect output inductor to DrMOS with large plane to

lower the resistance

1. These components need to be placed very close to IC,

right between PHASE (pin 7) and BOOT (pin 5)

2. If any snubber network is required, place the

components as shown above and the network can be

placed at bottom

2. To reduce parasitic inductance, chip size 0402 can be

used

S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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SiC639, SiC639A

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Step 5: Signal Routing

Vishay Siliconix

1. Thermal relief vias can be added on the V_INand P_GND

pads to utilize inner layers for high current and thermal

dissipation

C_GND

2. To achieve better thermal performance, additional vias

can be put on V_INplane and P_GNDplane.

C_GND

3. V_SWHpad is a noise source and not recommended to put

vias on this plane

4. 8 mil drill for pads and 10 mils drill for plane can be the

optional via size. Vias on pad may drain solder during

assembly and cause assembly issue. Please consult

with the assembly house for guideline



Step 7: Ground Connection

C_GND

P_GND

V_SWH

1. Route the PWM / ZCD_EN# / DSBL# / THWn signal

traces out of the top left corner next DrMOS pin 1

P_GND

2. PWM signal is very important signal, both signal and

return traces need to pay special attention of not letting

this trace cross any power nodes on any layer

3. It is best to “shield” traces form power switching nodes,

e.g. V_SWH, to improve signal integrity

4. GL (pin 27) has been connected with GL pad internally

and does not need to connect externally

1. It is recommended to make single connection between

_GNDand P_GNDand this connection can be done on top



C

Step 6: Adding Thermal Relief Vias

layer

2. It is recommended to make the whole inner 1 layer (next

to top layer) ground plane and separate them into C_GND

and P_GNDplane

3. These ground planes provide shielding between noise

source on top layer and signal trace on bottom layer

V_SWH

C_GND

P_GND

V_IN

plane

V_INplane



S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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SiC639, SiC639A

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Vishay Siliconix

Multi-Phases VRPower PCB Layout

Following is an example for 6 phase layout. As can be seen, all the VRPower stages are lined in X-direction compactly with

decoupling caps next to them. The inductors are placed as close as possible to the SiC639 and SiC639A to minimize the PCB

copper loss. Vias are applied on all PADs (V_IN, P_GND, C_GND) of the SiC639 and SiC639A to ensure that both electrical and thermal

performance are excellent. Large copper planes are used for all the high current loops, such as V_IN, V_SWH, V_OUTand P_GND. These

copper planes are duplicated in other layers to minimize the inductance and resistance. All the control signals are routed from

the SiC639 and SiC639A to a controller placed to the north of the power stage through inner layers to avoid the overlap of high

current loops. This achieves a compact design with the output from the inductors feeding a load located to the south of the

design as shown in the figure.

V_IN

P_GND

V_OUT

Fig. 24 - Multi-Phase VRPower Layout Top View

V_IN

P_GND

V_OUT

Fig. 25 - Multi-Phase VRPower Layout Bottom View

S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiC639, SiC639A

www.vishay.com

Vishay Siliconix

PRODUCT SUMMARY

Part number

SiC639

SiC639A

50 A power stage, 2.7 V_INto 24 V_IN, 5 V PWM

with ZCD mode

50 A power stage, 2.7 V_INto 24 V_IN, 3.3 V

PWM with ZCD mode

Description

Input voltage min. (V)

Input voltage max. (V)

Continuous current rating max. (A)

Switch frequency max. (kHz)

Enable (yes / no)

2.7

24

50

1500

Yes

Monitoring features

Protection

-

UVLO, THDN

Light load mode

ZCD

3.3

Pulse-width modulation (V)

Package type

5

PowerPAK MLP55-31L

5.0 x 5.0 x 0.75

PowerPAK MLP55-31L

5.0 x 5.0 x 0.75

2

Package size (W, L, H) (mm)

Status code

2

Product type

VRPower (DrMOS)

Computer, industrial, networking

VRPower (DrMOS)

Computer, industrial, networking

Applications

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?76585.

S20-0485-Rev. B, 29-Jun-2020

Document Number: 76585

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information

www.vishay.com

Vishay Siliconix

PowerPAK^®MLP55-31L Case Outline

0.08 C

D2-5

K12

5

6

K7

2 x

A

Pin 1 dot

K1 D2- 1

by marking

A1

A2

0.10 C A

A

K4

D

2 x

D2-4

24

0.10 C B

31

1

23

MLP55-31L

(5 mm x 5 mm)

8

16

B

15

9

K2

C

D2- 3

D2- 2

K9

(Nd-1) x e

ref.

Top view

Side view

Bottom view

MILLIMETERS

NOM.

0.75

INCHES

NOM.

DIM.

MIN.

0.70

0.00

MAX.

0.80

MIN.

0.027

0.000

MAX.

0.031

0.002

A ⁽⁸⁾

A1

0.029

-

0.05

-

A2

b ⁽⁴⁾

0.20 ref.

0.25

0.008 ref.

0.010

0.20

4.90

0.30

5.10

0.008

0.193

0.012

0.200

D

5.00

0.196

e

0.50 BSC

5.00

0.019 BSC

0.196

E

4.90

0.35

5.10

0.45

0.193

0.013

0.200

0.017

L

0.40

0.015

N ⁽³⁾

Nd ⁽³⁾

Ne ⁽³⁾

D2-1

D2-2

D2-3

D2-4

D2-5

E2-1

E2-2

E2-3

E2-4

F1

32

8

0.98

1.87

1.03

1.08

1.97

0.039

0.074

0.041

0.043

0.078

1.03

0.041

1.92

0.076

0.30 BSC

1.05

0.012 BSC

0.041

1.00

1.27

1.93

3.75

1.10

1.37

2.03

3.82

0.039

0.050

0.076

0.148

0.043

0.054

0.080

0.152

1.32

0.052

1.98

0.078

3.80

0.150

0.45 BSC

0.20 BSC

0.67 BSC

0.22 BSC

1.25 BSC

0.05 BSC

0.38 BSC

0.12 BSC

0.018 BSC

0.008 BSC

0.026 BSC

0.008 BSC

0.049 BSC

0.002 BSC

0.015 BSC

0.005 BSC

F2

K1

K2

K3

K4

K5

K6

Revision: 24-Oct-16

Document Number: 64909

1

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Package Information

www.vishay.com

Vishay Siliconix

MILLIMETERS

NOM.

INCHES

DIM.

MIN.

MAX.

MIN.

NOM.

MAX.

K7

K8

0.40 BSC

0.85 BSC

0.40 BSC

0.016 BSC

0.033 BSC

0.016 BSC

K9

K10

K11

K12

ECN: T16-0644-Rev. E, 24-Oct-16

DWG: 6025

Notes

1. Use millimeters as the primary measurement

2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994

3. N is the number of terminals,

Nd is the number of terminals in X-direction, and

Ne is the number of terminals in Y-direction

4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip

5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body

6. Exact shape and size of this feature is optional

7. Package warpage max. 0.08 mm

8. Applied only for terminals

Revision: 24-Oct-16

Document Number: 64909

2

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

PAD Pattern

Vishay Siliconix

www.vishay.com

Recommended Land Pattern

PowerPAK^®MLP55-31L

Top side transparent view

(not bottom view)

Land pattern for MLP55-31L

(D2-4)

3.4

5

1.35

1

0.57

(D2-1)

1.03

(D2-5)

1.05

0.5

31

24

31

0.75

(D3) 0.3

1.13

0.3

1

23

1

1.15

2.02

1.75

(K2) 0.22

0.3

(K1) 0.67

8

16

8

16

0.35

0.18

9

15

(L)

0.4

(L)

0.4

0.3

(D2-2)

1.03

(D2-3)

1.92

9

0.5

15

0.35

0.65

0.75

0.5

All dimensions in millimeters

24

31

1

23

33

Component for MLP55-31L

Land pattern for MLP55-31L

32

33

35

8

16

9

15

Revision: 18-Oct-2019

Document Number: 66944

1

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Legal Disclaimer Notice

www.vishay.com

Vishay

Disclaimer

ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE

RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,

“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other

disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or

the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all

liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,

consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular

purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of

typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding

statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a

particular product with the properties described in the product specification is suitable for use in a particular application.

Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over

time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s

technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,

including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining

applications or for any other application in which the failure of the Vishay product could result in personal injury or death.

Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.

Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for

such applications.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document

or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.

Revision: 01-Jan-2019

Document Number: 91000

1


型号：	SIC639
厂家：	VISHAY
描述：	50 A VRPowerÂ® Integrated Power Stage
文件：	总18页 (文件大小：345K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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