SIC778ACD-T1-GE3 [VISHAY]
High Performance DrMOS â Integrated Power Stage;
| 型号： | SIC778ACD-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | High Performance DrMOS â Integrated Power Stage 服务器主板节能技术 |
| 文件： | 总13页 (文件大小：719K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiC778A
Vishay Siliconix
High Performance DrMOS – Integrated Power Stage
DESCRIPTION
FEATURES
•
The SiC778 is an integrated power stage solution optimized
for synchronous buck applications offering high current, high
efficiency and high power density. Packaged in Vishay’s
proprietary 6 mm x 6 mm MLP package, SiC778 enables
voltage regulator designs to deliver in excess of 40 A per
phase current with 91 % peak efficiency.
The internal Power MOSFETs utilize Vishay’s state-of-the-art
TrenchFET Gen III technology that delivers industry
bench-mark performance by significantly reducing switching
and conduction losses.
The SiC778 incorporates an advanced MOSFET gate driver
IC that features high current driving capability, adaptive
dead-time control, an integrated bootstrap Schottky diode,
and a thermal warning (THDN) that alerts the system of
excessive junction temperature. The driver is also compatible
with a wide range of PWM controllers and supports tri-state
PWM, 3.3 V (SiC778ACD) PWM logic, and skip mode
(SMOD) to improve light load efficiency.
Thermally enhanced PowerPAK® MLP6x6-40L
package
•
Industry benchmark MOSFET with integrated
Schottky diode
•
•
•
•
•
•
•
•
•
•
•
•
Delivers in excess of 40 A continuous current
91 % peak efficiency
High frequency operation up to 1 MHz
Power MOSFETs optimized for 12 V input stage
3.3 V PWM logic with tri-state and hold-off
SMOD logic for light load efficiency boost
Low PWM propagation delay (< 20 ns)
Thermal monitor flag
Enable feature
VCIN UVLO
Compliant with Intel DrMOS 4.0 specification
Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
•
•
•
Synchronous buck converters
Multi-phase VRDs for CPU, GPU, and memory
DC/DC POL modules
TYPICAL APPLICATION DIAGRAM
Figure 1: SiC778 Typical Application Diagram
Document Number: 63808
S12-1132-Rev. B, 21-May-12
For technical support, please contact: powerictechsupport@vishay.com
This document is subject to change without notice.
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
PIN CONFIGURATION
Figure 2 - SiC778 Pin Configuration (Bottom View)
PIN DESCRIPTION
Pin Number
Symbol
SMOD#
VCIN
Description
LS FET turn-off logic. Active low
Supply voltage for internal logic circuitry
Supply voltage for internal gate driver
High side driver bootstrap voltage
Analog ground for the driver IC
High side gate signal
1
2
3
VDRV
BOOT
CGND
GH
4
5, 37, P1
6
7
PHASE
VIN
Return path of HS gate driver
Power stage input voltage. Drain of high side MOSFET
Phase node of the power stage
Power ground
8 to 14, P2
15, 29 to 35, P3
VSWH
PGND
GL
16 to 28
36
Low side gate signal
38
THDN
DSBL#
PWM
Thermal shutdown open drain output
Disable pin. Active low
39
40
PWM input logic
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Document Number: 63808
S12-1132-Rev. B, 21-May-12
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
ORDERING INFORMATION
Part Number
Package
Marking Code
SiC778ACD-T1-GE3
SiC778DB
PowerPAK MLP66-40L
SiC778A
Reference board
(1)
ABSOLUTE MAXIMUM RATINGS
Electrical Parameter
Symbol
VIN
Limits
Unit
Input Voltage
- 0.3 to 20
- 0.3 to 7
- 0.3 to 7
- 0.3 to 20
- 0.3 to 27
- 0.3 to 7
VCIN
Control Input Voltage
VDRV
VSW
Drive Input Voltage
Switch Node (DC)
V
VBS
Boot Voltage (DC Voltage)
Boot to Switching Node (DC Voltage)
VBS_SW
- 0.3 to VCIN + 0.3
All Logic Inputs and Outputs (PWM, DSBL, SMOD and THDN)
Max. Operating Junction Temperature
Ambient Temperature
TJ
150
TA
°C
- 40 to 125
- 65 to 150
Storage Temperature
Note:
1. Stresses beyond those listed under ’’Absolute Maximum Ratings’’ may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Min.
Typ.
Max.
18
Unit
Input Voltage (VIN
)
4.5
Drive Input Voltage (VDRV
)
4.5
5
5
5.5
5.5
19
Control Input Voltage (VCIN
)
4.5
V
Switching Node (LX, DC Voltage)
BOOT-SW
4
4.5
5.5
THERMAL RESISTANCE RATINGS
Parameter
Min.
Typ.
2.5
5
Max.
Unit
°C/W
Thermal Resistance from Junction to Case (to P3 PAD VSWP signal)
Thermal Resistance from Junction to PCB
ELECTRICAL SPECIFICATIONS
Test Conditions Unless Specified
DSBL# = 5 V, VSMOD = 5 V,
V
Parameter
Symbol
Min.(2) Typ.(1) Max.(2) Unit
V
IN = 12 V, VDRV = VCIN = 5 V,
TA = 25 °C
Power Supplies
VDSBL# = 0 V, no switching
VDSBL# = 5 V, no switching
100
Control Logic Input Current
IVCIN
300
300
16
µA
VDSBL# = 5 V, fs = 300 kHz, D = 0.1
fs = 300 kHz, D = 0.1
25
Drive Input Current (Dynamic)
mA
µA
fs = 1 MHz, D = 0.1
60
IVDRV
VDSBL# = 0 V, no switching
30
Drive Input Current (No Switching)
V
DSBL# = 5 V, no switching
60
Document Number: 63808
S12-1132-Rev. B, 21-May-12
For technical support, please contact: powerictechsupport@vishay.com
This document is subject to change without notice.
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Test Conditions Unless Specified
DSBL# = 5 V, VSMOD = 5 V,
V
Parameter
Symbol
Min.(2) Typ.(1) Max.(2) Unit
V
IN = 12 V, VDRV = VCIN = 5 V,
TA = 25 °C
Bootstrap Supply
Bootstrap Switch Forward Voltage
PWM Control Input (SiC778ACD)
Rising Threshold
VF
VCIN = 5 V, forward bias current 2 mA
0.4
V
V
Vth_pwm_r
Vth_pwm_f
Vtri
2.1
0.7
2.4
0.9
1.8
2.8
1.2
Falling Threshold
Tri-state Voltage
PWM pin floating
Tri-state Rising Threshold
Tri-state Falling Threshold
Tri-state Rising Threshold Hysteresis
Tri-state Falling Threshold Hysteresis
Vth_tri_r
Vth_tri_f
Vhys_tri_r
Vhys_tri_f
0.9
1.9
1.5
2.6
2.2
225
275
mV
µA
VPWM = 3.3 V
VPWM = 0 V
300
PWM Input Current
IPWM
- 300
Timing Specifications
Tri-State to GH/GL Rising Propagation
Delay
TPD_R_Tri
TTSHO
20
Tri-state Hold-Off Time
150
20
GH - Turn Off Propagation Delay
TPD_OFF_GH
TPD_ON_GH
TPD_OFF_GL
TPD_ON_GL
No load, see fig. 4.
GH - Turn ON Propagation Delay
(Dead Time Rising)
10
20
10
ns
GL - Turn Off Propagation Delay
GL - Turn On Propagation Delay
(Dead Time Falling)
DSBL# High to GH/GL Rising Propagation
Delay
TPD_R_DSBL
TPD_F_DSBL
22
10
DSBL# Low to GH/GL Falling Propagation
Delay
DSBL#, SMOD INPUT
Enable
2
2
DSBL# Logic Input Voltage
VDSBL
Disenable
High State
Low State
0.8
0.8
4.3
V
SMOD Logic Input Voltage
Protection
VSMOD
Rising, On Threshold
Falling, Off Threshold
3.7
3.2
Under Voltage Lockout
VUVLO
V
2.7
Under Voltage Lockout Hysteresis
THDn Flag Set
550
160
135
25
mV
Note 3
THDn Flag Clear
°C
V
THDn Flag Hysteresis
THDn Output Low
0.02
Notes:
1.Typical limits are established by characterization and are not production tested.
2.Min. and max. not 100 % production tested.
3.Guaranteed by design.
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This document is subject to change without notice.
Document Number: 63808
S12-1132-Rev. B, 21-May-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.
The PWM input receives the PWM control signal from the
VR controller IC. The PWM input is designed to be
compatible with standard controllers using two state logic
(H and L) and advanced controllers that incorporate tri-state
logic (H, L, and tri-state) on the PWM output. For two state
logic, the PWM input operates as follows. When PWM is
Voltage Input (VIN)
This is the power input to the drain of the high-side
power MOSFET. This pin is connected to the high
power intermediate BUS rail.
driven above Vth
the low side is turned OFF and the
_pwm_r
high side is turned ON. When PWM input is driven below
Vth the high side turns off and the low side turns on.
Switch Node (VSWH and PHASE)
The Switch node VSWH is the circuit PWM regulated output.
This is the output applied to the filter circuit to deliver
the regulated high output for the buck converter. The PHASE
pin is internally connected to the switch node VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20.2 k resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that VCIN goes to zero while VIN is still applied.
_pwm_f
For tri-state logic, the PWM input operates as above for
driving the MOSFETs. However, there is an third state
that is entered into as the PWM output of tri-state
compatible controller enters its high impedance state during
shut-down. The high impedance state of the controller's
PWM output allows the SiC778A to pull the PWM input
into the tri-state region (see the tri-state Voltage
Threshold diagram below). If the PWM input stays in this
region for the tri-state hold-off period, tTSHO, both high side
and low side MOSFETs are turned off. This function allows
the VR phase to be disabled without negative output voltage
swing caused by inductor ringing and saves a schottky diode
clamp. The PWM and tri-state regions are separated
by hysteresis to prevent false triggering. The SiC778ACD
incorporates PWM voltage thresholds that are compatible
with 3.3 V logic.
Ground Connections (CGND and PGND
)
PGND (power ground) should be externally connected
to CGND (control signal ground). The layout of the
printed circuit board should be such that the inductance
separating the CGND and PGND should be a minimum.
Transient differences due to inductance effects between
these two pins should not exceed 0.5 V.
Control and Drive Supply Voltage Input (VDRV, VCIN
)
Disable (DSBL#)
VCIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
In the low state, the DSBL# pin shuts down the driver IC
and disables both high-side and low-side MOSFET. In this
state, the standby current is minimized. If DSBL# is
left unconnected an internal pull-down resistor will pull the
pin down to CGND and shut down the IC.
Bootstrap Circuit (BOOT)
Diode Emulation Mode (SMOD) Skip
When SMOD pin is low the diode emulation mode is enabled
and GL is turned off. This is a non-synchronous conversion
The internal bootstrap switch and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one leg
tied to BOOT pin and the other tied to PHASE pin.
shoot-through protection and adaptive dead time
mode
that
improves
light
load
efficiency
by
reducing switching losses. Conducted losses that occur in
synchronous buck regulators when inductor current
is negative can also be reduced. Circuitry in the external
controller IC detects when inductor current crosses zero and
drive SMOD Lo turning the low side MOSFET off. See SMOD
operation diagram for additional details. This function can be
also be used for a pre-biased output voltage. If SMOD is left
unconnected, an internal pull up resistor will pull the pin up to
VCIN (logic high) to disable the SMOD function.
Shoot-Through Protection and Adaptive Dead Time
(AST)
The SiC778A has an internal adaptive logic to avoid shoot
through
and
optimize
dead
time.
The
shoot
through protection ensures that both high-side and low-side
MOSFET are not turned on the same time. The adaptive
dead time control operates as follows. The HS and LS gate
voltages are monitored to prevent the one turning on until the
other’s gate voltage is sufficiently low (1 V), that and built in
delays ensure the one power MOS is completely off, before
the other can be turned on. This feature helps to adjust dead
time as gate transitions change with respect to output current
and temperature.
Thermal Shutdown Warning (THDN)
The THDN pin is an open drain signal that flags the
presence of excessive junction temperature. Connect a
maximum of 20 k to pull this pin up to VCIN. An internal
temperature sensor detects the junction temperature.
The temperature threshold is 160 °C. When this
junction temperature is exceeded the THDN flag is set.
When the junction temperature drops below 135 °C the
device will clear the THDN signal. The SiC778 does not stop
Document Number: 63808
S12-1132-Rev. B, 21-May-12
For technical support, please contact: powerictechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
Under Voltage Lockout (UVLO)
incorporates logic to clamp the gate drive signals to zero
when the UVLO falling edge triggers the shutdown of
the device. As an added precaution, a 20.2 k resistor
is connected between GH and PHASE to provide
a discharge path for the HS MOSFET.
During the start up cycle, the UVLO disables the gate drive
holding high-side and low-side MOSFET gate low until the
input voltage rail has reached a point at which the
logic circuitry can be safely activated. The SiC778A also
FUNCTIONAL BLOCK DIAGRAM
Figure 3: SiC778 Functional Block Diagram
DEVICE TRUTH TABLE
DSBL#
SMOD
PWM
GH
L
GL
L
Open
L
X
X
L
X
X
L
L
H
L
L
L
H
L
H
H
H
H
L
L
H
H
H
L
L
H
L
H
L
H
Tri-state
Tri-state
L
H
H
L
L
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Document Number: 63808
S12-1132-Rev. B, 21-May-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
DEFINITION OF PWM LOGIC AND TRI-STATE
Figure 4: Definition of PWM Logic and Tri-state
SMOD OPERATION DIAGRAM
PWM
PWM
0V
0V
GH
GH
IL
IL
0A
0A
GL
GL
10nS
SMOD#
SMOD#
Figure 5: CCM Operation with SMOD# = High
Figure 6: DCM Operation with SMOD# = Active Toggle
Document Number: 63808
S12-1132-Rev. B, 21-May-12
For technical support, please contact: powerictechsupport@vishay.com
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Start-up with VIN Ramping up
IN = 12 V, VOUT = 1.2 V, fSW = 500 kHz
Power Off with VIN Ramping down
VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz
V
Start-up with DSBL# Toggle High
VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz
Shut-down with DSBL# Toggle Low
VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz
Start-up with PWM existing Tri-state
IN = 12 V, VOUT = 1.2 V, fSW = 500 kHz
Shut-down with PWM entreing Tri-state
VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz
V
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Document Number: 63808
S12-1132-Rev. B, 21-May-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Start-up with VDRV/VCIN Ramping Up
Power Off with VDRV/VCIN Ramping Down
VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz, IOUT = 1.2 A
V
IN = 12 V, VOUT = 1.2 V, fSW = 500 kHz
Switching waveform at PWM Rising Edge
IN = 12 V, VOUT = 1.2 V, fSW = 500 kHz, IOUT = 0 A
Switching Waveform at PWM Falling Edge
IN = 12 V, VOUT = 1.2 V, fSW = 500 kHz
V
V
Switching Waveform at PWM Rising Edge
Switching Waveform at PWM Falling Edge
VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz, IOUT = 30 A
VIN = 12 V, VOUT = 1.2 V, fSW = 500 kHz, IOUT = 30 A
Document Number: 63808
S12-1132-Rev. B, 21-May-12
For technical support, please contact: powerictechsupport@vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Fsw = 300KHz
Fsw = 400KHz
Fsw = 500KHz
Fsw = 300KHz
Fsw = 400KHz
Fsw = 500KHz
10
8
94
92
90
88
86
84
82
80
78
76
6
4
2
0
0
3
6
9
12
15
18
21
24
27
30
33
0
3
6
9
12
15
18
21
24
27
30
33
Output Load (A)
Output Load (A)
Typical Efficiency
Typical Power Loss
V
IN = 12 V, VOUT = 1.2 V, VDRV = VCIN; No Air Flow,
O/P Inductance = 0.33 µH
V
IN = 12 V, VOUT = 1.2 V, VDRV = VCIN; No Air Flow,
O/P Inductance = 0.33 µH
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This document is subject to change without notice.
Document Number: 63808
S12-1132-Rev. B, 21-May-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC778A
Vishay Siliconix
PACKAGE DIMENSIONS
K1
K2
2 x
0.08 C
A1
A2
A
5
6
0.10 C A
D
Pin #1 dent
A
Pin 1 dot
by marking
0.41
30
D2-1
31
40
2 x
1
0.10 C B
MLP66-40
(6 mm x 6 mm)
10
21
B
20
11
D2-2
D2-3
C
(Nd-1)X
ref.
e
Top View
Bottom View
Side View
MILLIMETERS
Nom.
0.75
INCHES
DIM
Min.
0.70
0
Max.
Min.
0.027
0
Nom.
0.029
Max.
0.031
0.002
A(8)
A1
0.80
0.05
-
-
A2
b(4)
0.20 ref.
0.25
0.008 ref.
0.098
0.20
0.30
0.45
0.078
0.011
D
6.00 BSC
0.50 BSC
6.00 BSC
0.40
0.236 BSC
0.019 BSC
0.236 BSC
0.015
e
E
L
0.35
0.013
0.017
N (3)
Nd (3)
Ne (3)
D2-1
D2-2
D2-3
E2-1
E2-2
E2-3
K1
40
40
10
10
10
10
1.45
1.45
2.35
4.35
1.95
1.95
1.50
1.55
1.55
2.45
4.45
2.05
2.05
0.057
0.057
0.095
0.171
0.076
0.076
0.059
0.061
0.061
0.096
0.175
0.080
0.080
1.50
0.059
2.40
0.094
4.40
0.173
2.00
0.078
2.00
0.078
0.73 BSC
0.21 BSC
0.028 BSC
0.008 BSC
K2
Notes:
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y14.5M-1994.
3. N is the number of terminals.
Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction .
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body .
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63808.
Document Number: 63808
S12-1132-Rev. B, 21-May-12
For technical support, please contact: powerictechsupport@vishay.com
This document is subject to change without notice.
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
PowerPAK® MLP66-40 CASE OUTLINE
K1
K2
2 x
0.08 C
A1
A2
A
5
6
0.10 C A
D
Pin #1 dent
D2-1
A
Pin 1 dot
by marking
0.41
30
31
40
2 x
1
0.10 C B
MLP66-40
(6 mm x 6 mm)
10
21
B
20
11
D2-2
D2-3
C
(Nd-1)X
ref.
e
Top View
Bottom View
Side View
MILLIMETERS
INCHES
DIM.
MIN.
0.70
0.00
NOM.
0.75
MAX.
0.80
0.05
MIN.
0.027
0.000
NOM.
0.029
MAX.
0.031
0.002
A (8)
A1
A2
b (4)
D
-
-
0.20 ref.
0.25
0.008 ref.
0.098
0.20
0.30
0.078
0.011
6.00 BSC
0.50 BSC
6.00 BSC
0.40
0.236 BSC
0.019 BSC
0.236 BSC
0.015
e
E
L
0.35
0.45
0.013
0.017
N (3)
40
40
Nd (3)
Ne (3)
D2-1
D2-2
D2-3
E2-1
E2-2
E2-3
K1
10
10
10
10
1.45
1.45
2.35
4.35
1.95
1.95
1.50
1.55
1.55
2.45
4.45
2.05
2.05
0.057
0.057
0.095
0.171
0.076
0.076
0.059
0.061
0.061
0.096
0.175
0.080
0.080
1.50
0.059
2.40
0.094
4.40
0.173
2.00
0.078
2.00
0.078
0.73 BSC
0.21 BSC
0.028 BSC
0.008 BSC
K2
ECN: T09-0195-Rev. A, 04-May-09
DWG: 5986
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
Document Number: 64846
04-May-09
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Revision: 12-Mar-12
Document Number: 91000
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