SIHB28N60EF-GE3 [VISHAY]
Power Field-Effect Transistor, 28A I(D), 600V, 0.123ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, D2PAK-3/2;
| 型号： | SIHB28N60EF-GE3 |
| 厂家： | 
VISHAY |
| 描述： | Power Field-Effect Transistor, 28A I(D), 600V, 0.123ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-263AB, D2PAK-3/2 开关 脉冲 晶体管 |
| 文件： | 总9页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiHB28N60EF
Vishay Siliconix
www.vishay.com
EF Series Power MOSFET with Fast Body Diode
FEATURES
PRODUCT SUMMARY
• Fast body diode MOSFET using E series
technology
• Reduced trr, Qrr, and IRRM
• Low figure-of-merit (FOM): Ron x Qg
• Low input capacitance (Ciss
• Low switching losses due to reduced Qrr
• Ultra low gate charge (Qg)
• Avalanche energy rated (UIS)
VDS (V) at TJ max.
DS(on) max. at 25 °C ()
Qg (Max.) (nC)
650
R
VGS = 10 V
0.123
120
17
)
Q
gs (nC)
gd (nC)
Q
33
Configuration
Single
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
D
D2PAK (TO-263)
APPLICATIONS
• Telecommunications
- Server and telecom power supplies
• Lighting
G
- High intensity discharge (HID)
- Light emitting diodes (LEDs)
• Consumer and computing
- ATX power supplies
• Industrial
D
G
S
S
N-Channel MOSFET
- Welding
- Battery chargers
• Renewable energy
- Solar (PV inverters)
• Switch mode power suppliers (SMPS)
• Applications using the following topologies
- LLC
- Phase shifted bridge (ZVS)
- 3-level inverter
- AC/DC bridge
ORDERING INFORMATION
Package
D2PAK (TO-263)
Lead (Pb)-free and Halogen-free
SiHB28N60EF-GE3
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
600
V
VGS
30
T
C = 25 °C
28
Continuous Drain Current (TJ = 150 °C)
VGS at 10 V
ID
TC = 100 °C
18
A
Pulsed Drain Current a
IDM
75
Linear Derating Factor
Single Pulse Avalanche Energy b
2
691
W/°C
mJ
W
EAS
PD
Maximum Power Dissipation
250
Operating Junction and Storage Temperature Range
Drain-Source Voltage Slope
Reverse Diode dV/dt d
TJ, Tstg
-55 to +150
70
°C
TJ = 125 °C
for 10 s
dV/dt
V/ns
°C
50
Soldering Recommendations (Peak Temperature) c
300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature
b. VDD = 50 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 , IAS = 7 A
c. 1.6 mm from case
d. ISD ID, dI/dt = 900 A/μs, starting TJ = 25 °C
S17-0294-Rev. C, 27-Feb-17
Document Number: 91601
1
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB28N60EF
Vishay Siliconix
www.vishay.com
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
RthJA
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
Maximum Junction-to-Case (Drain)
-
-
62
°C/W
RthJC
0.5
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-Source Breakdown Voltage
VDS
VGS = 0 V, ID = 250 μA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 μA
600
-
-
V
V/°C
V
VDS Temperature Coefficient
VDS/TJ
VGS(th)
-
2.0
-
0.76
-
4.0
100
1
Gate-Source Threshold Voltage (N)
-
VGS
VGS
=
=
20 V
30 V
-
nA
μA
μA
mA
Gate-Source Leakage
IGSS
IDSS
-
-
-
VDS = 480 V, VGS = 0 V
-
1
Zero Gate Voltage Drain Current
V
DS = 480 V, VGS = 0 V, TJ = 125 °C
-
-
2
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
VGS = 10 V
ID = 14 A
-
0.107
9.7
0.123
-
VDS = 30 V, ID = 14 A
-
S
Input Capacitance
Ciss
Coss
Crss
-
-
-
2714
123
6
-
-
-
VGS = 0 V,
VDS = 100 V,
f = 1 MHz
Output Capacitance
Reverse Transfer Capacitance
pF
nC
Effective output capacitance, energy
related a
Co(er)
Co(tr)
-
-
98
-
-
VGS = 0 V, VDS = 0 V to 480 V
Effective output capacitance, time
related b
356
Total Gate Charge
Qg
Qgs
Qgd
td(on)
tr
-
-
80
17
33
24
40
82
39
0.5
120
-
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
V
GS = 10 V
ID = 14 A, VDS = 480 V
-
-
-
48
80
123
78
1.0
-
VDD = 480 V, ID = 14 A
ns
Rg = 9.1 , VGS = 10 V
Turn-Off Delay Time
Fall Time
td(off)
tf
-
-
Gate Input Resistance
Drain-Source Body Diode Characteristics
Rg
f = 1 MHz, open drain
0.2
D
MOSFET symbol
showing the
Continuous Source-Drain Diode Current
Pulsed Diode Forward Current
IS
-
-
-
-
28
70
A
G
integral reverse
p - n junction diode
ISM
S
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Current
VSD
trr
TJ = 25 °C, IS = 11 A, VGS = 0 V
-
-
-
-
0.9
142
0.97
13.2
1.2
284
1.94
-
V
ns
μC
A
TJ = 25 °C, IF = IS = 14 A,
dI/dt = 100 A/μs, VR = 400 V
Qrr
IRRM
Notes
a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS
b. Coss(tr) is a fixed capacitance that gives the charging time as Coss while VDS is rising from 0 % to 80 % VDS
S17-0294-Rev. C, 27-Feb-17
Document Number: 91601
2
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB28N60EF
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
80
3.0
2.5
2.0
1.5
1.0
0.5
0
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
TJ = 25 °C
ID = 14 A
60
40
20
0
BOTTOM 5 V
VGS = 10 V
0
5
10
15
20
25
30
-60 -40 -20
0
20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
TJ, Junction Temperature (°C)
Fig. 1 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
10 000
TOP
15 V
14 V
13 V
12 V
11 V
10 V
9 V
8 V
7 V
6 V
TJ = 150 °C
Ciss
45
30
15
0
VGS = 0 V, f = 1 MHz
1000
100
10
C
C
iss = Cgs + Cgd, Cds shorted
rss = Cgd
Coss = Cds + Cgd
BOTTOM 5 V
Coss
Crss
1
0
100
200
300
400
500
600
0
5
10
15
20
25
30
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
80
18
16
5000
TJ = 25 °C
14
12
10
60
40
20
0
TJ = 150 °C
Coss
Eoss
8
6
4
2
0
500
VDS = 28 V
50
0
5
10
15
20
25
0
100
200
300
VDS
400
500
600
VGS, Gate-to-Source Voltage (V)
Fig. 3 - Typical Transfer Characteristics
Fig. 6 - Coss and Eoss vs. VDS
S17-0294-Rev. C, 27-Feb-17
Document Number: 91601
3
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB28N60EF
Vishay Siliconix
www.vishay.com
30
24
18
12
6
24
20
16
12
8
VDS = 480 V
VDS = 300 V
DS = 120 V
V
4
0
0
25
50
75
100
125
150
0
40
80
120
160
TC, Case Temperature (°C)
Qg, Total Gate Charge (nC)
Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage
Fig. 10 - Maximum Drain Current vs. Case Temperature
750
725
700
675
650
625
600
100
TJ = 150 °C
10
TJ = 25 °C
1
VGS = 0 V
1.4 1.6
ID = 250 μA
0.1
575
-60 -40 -20
0.2
0.4
0.6
0.8
1.0
1.2
0
20 40 60 80 100 120 140 160
TJ, Junction Temperature (°C)
VSD, Source-Drain Voltage (V)
Fig. 8 - Typical Source-Drain Diode Forward Voltage
Fig. 11 - Typical Drain-to-Source Voltage vs. Temperature
Operation in this Area
Limited by RDS(on)
IDM Limited
100
10
100 μs
Limited by RDS(on)
*
1
1 ms
0.1
0.01
10 ms
TC = 25 °C
TJ = 150 °C
Single Pulse
BVDSS Limited
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Fig. 9 - Maximum Safe Operating Area
S17-0294-Rev. C, 27-Feb-17
Document Number: 91601
4
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB28N60EF
Vishay Siliconix
www.vishay.com
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
0.0001
0.001
0.01
0.1
1
Pulse Time (s)
Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case
RD
VDS
VDS
tp
VGS
VDD
D.U.T.
RG
+
V
-
DD
VDS
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
IAS
Fig. 13 - Switching Time Test Circuit
Fig. 16 - Unclamped Inductive Waveforms
VDS
QG
10 V
90 %
QGS
QGD
10 %
VGS
VG
td(on) tr
td(off) tf
Charge
Fig. 14 - Switching Time Waveforms
Fig. 17 - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
L
VDS
Vary tp to obtain
required IAS
50 kΩ
12 V
0.2 µF
D.U.T
IAS
0.3 µF
RG
+
-
VDD
+
-
VDS
D.U.T.
10 V
VGS
0.01 Ω
tp
3 mA
Fig. 15 - Unclamped Inductive Test Circuit
IG
ID
Current sampling resistors
Fig. 18 - Gate Charge Test Circuit
Document Number: 91601
S17-0294-Rev. C, 27-Feb-17
5
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiHB28N60EF
Vishay Siliconix
www.vishay.com
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T.
• Low leakage inductance
current transformer
-
+
-
-
+
Rg
• dV/dt controlled by Rg
• Driver same type as D.U.T.
• ISD controlled by duty factor “D”
• D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
P.W.
D =
Period
Period
V
GS = 10 Va
D.U.T. lSD waveform
D.U.T. VDS waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
Diode recovery
dV/dt
VDD
Re-applied
voltage
Body diode forward drop
Inductor current
ISD
Ripple ≤ 5 %
Note
a. VGS = 5 V for logic level devices
Fig. 19 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91601.
S17-0294-Rev. C, 27-Feb-17
Document Number: 91601
6
For technical questions, contact: hvm@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
Vishay Siliconix
TO-263AB (HIGH VOLTAGE)
A
B
(Datum A)
3
4
A
A
E
c2
H
L1
4
Gauge
plane
0° to 8°
4
B
5
Detail A
Seating plane
D
H
L
C
C
A1
L3
L4
Detail “A”
1
2
3
L2
Rotated 90° CW
B
B
scale 8:1
A
2 x b2
2 x b
c
E
M
M
B
0.010
A
M
0.004
B
2 x e
Base
metal
5
D1
4
Plating
(c)
b1, b3
5
c1
(b, b2)
Lead tip
4
E1
Section B - B and C - C
Scale: none
View A - A
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
A
MIN.
4.06
0.00
0.51
0.51
1.14
1.14
0.38
0.38
1.14
8.38
MAX.
4.83
0.25
0.99
0.89
1.78
1.73
0.74
0.58
1.65
9.65
MIN.
0.160
0.000
0.020
0.020
0.045
0.045
0.015
0.015
0.045
0.330
MAX.
0.190
0.010
0.039
0.035
0.070
0.068
0.029
0.023
0.065
0.380
DIM.
D1
E
MIN.
6.86
MAX.
MIN.
MAX.
-
10.67
-
0.270
0.380
0.245
-
0.420
-
A1
b
9.65
6.22
E1
e
b1
b2
b3
c
2.54 BSC
0.100 BSC
H
14.61
15.88
2.79
1.65
1.78
0.575
0.625
0.110
0.066
0.070
L
1.78
0.070
L1
L2
L3
L4
-
-
-
-
c1
c2
D
0.25 BSC
0.010 BSC
4.78
5.28
0.188
0.208
ECN: S-82110-Rev. A, 15-Sep-08
DWG: 5970
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the
outmost extremes of the plastic body at datum A.
4. Thermal PAD contour optional within dimension E, L1, D1 and E1.
5. Dimension b1 and c1 apply to base metal only.
6. Datum A and B to be determined at datum plane H.
7. Outline conforms to JEDEC outline to TO-263AB.
Document Number: 91364
Revision: 15-Sep-08
www.vishay.com
1
AN826
Vishay Siliconix
2
RECOMMENDED MINIMUM PADS FOR D PAK: 3-Lead
0.420
(10.668)
0.145
(3.683)
0.135
(3.429)
0.200
0.050
(5.080)
(1.257)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 73397
11-Apr-05
www.vishay.com
1
Legal Disclaimer Notice
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Vishay
Disclaimer
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RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
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Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
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© 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED
Revision: 08-Feb-17
Document Number: 91000
1
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