SIHFB11N50A [VISHAY]
Power MOSFET; 功率MOSFET型号: | SIHFB11N50A |
厂家: | VISHAY |
描述: | Power MOSFET |
文件: | 总8页 (文件大小:160K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
Power MOSFET
FEATURES
• Low Gate Charge Qg Results in Simple Drive
Requirement
PRODUCT SUMMARY
VDS (V)
500
Available
R
DS(on) (Ω)
VGS = 10 V
0.52
RoHS*
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
Qg (Max.) (nC)
52
13
COMPLIANT
Q
Q
gs (nC)
gd (nC)
• Fully
Characterized
Capacitance
and
18
Avalanche Voltage and current
Configuration
Single
• Lead (Pb)-free Available
D
APPLICATIONS
TO-220
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• High Speed Power Switching
G
APPLICABLE OFF LINE SMPS TOPOLOGIES
• Two Transistor Forward
S
D
G
S
N-Channel MOSFET
• Half and Full Bridge
• Power Factor Correction Boost
ORDERING INFORMATION
Package
TO-220
IRFB11N50APbF
SiHFB11N50A-E3
IRFB11N50A
Lead (Pb)-free
SnPb
SiHFB11N50A
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
500
V
VGS
30
T
C = 25 °C
11
Continuous Drain Current
VGS at 10 V
ID
TC =100°C
7.0
A
Pulsed Drain Currenta
IDM
44
Linear Derating Factor
1.3
W/°C
mJ
A
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
EAS
IAR
275
11
EAR
17
170
mJ
W
Maximum Power Dissipation
TC = 25 °C
PD
Peak Diode Recovery dV/dtc
dV/dt
TJ, Tstg
6.9
V/ns
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
- 55 to + 150
300d
°C
for 10 s
10
lbf · in
N · m
Mounting Torque
6-32 or M3 screw
1.1
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 4.5 mH, RG = 25 Ω, IAS = 11 A (see fig. 12).
c. ISD ≤ 11 A, dI/dt ≤ 140 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91094
S-81243-Rev. B, 21-Jul-08
www.vishay.com
1
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
THERMAL RESISTANCE
PARAMETER
SYMBOL
RthJA
TYP.
MAX.
62
UNIT
Maximum Junction-to-Ambient
Case-to-Sink, Flat, Greased Surface
Maximum Junction-to-Case (Drain)
-
0.50
-
RthCS
-
°C/W
RthJC
0.75
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS
VGS(th)
IGSS
VGS = 0 V, ID = 250 µA
VDS = VGS, ID = 250 µA
500
-
-
-
-
-
-
-
-
V
V
2.0
4.0
100
25
VGS
VDS = 500 V, VGS = 0 V
DS = 400 V, VGS = 0 V, TJ = 150 °C
VGS = 10 V
ID = 6.6 Ab
=
30 V
-
nA
-
-
Zero Gate Voltage Drain Current
IDSS
µA
V
250
0.52
-
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
-
Ω
VDS = 50 V, ID = 6.6 A
6.1
S
VGS = 0 V,
VDS = 25 V,
Input Capacitance
Ciss
Coss
Crss
-
-
-
-
-
-
1423
208
8.1
-
-
-
-
-
-
Output Capacitance
Reverse Transfer Capacitance
f = 1.0 MHz, see fig. 5
pF
V
DS = 1.0 V, f = 1.0 MHz
2000
55
Output Capacitance
Coss
V
GS = 0 V
VDS = 400 V, f = 1.0 MHz
VDS = 0 V to 400 V
Effective Output Capacitance
Total Gate Charge
C
oss eff.
Qg
97
-
-
-
-
52
13
ID = 11 A, VDS = 400 V
see fig. 6 and 13b
Gate-Source Charge
Qgs
VGS = 10 V
nC
ns
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Qgd
td(on)
tr
-
-
-
-
-
-
18
-
14
35
32
28
-
V
DD = 250 V, ID = 11 A
Turn-Off Delay Time
Fall Time
td(off)
tf
-
R
G = 9.1 Ω, RD = 22 Ω, see fig. 10b
-
Drain-Source Body Diode Characteristics
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
IS
-
-
-
-
11
44
A
G
ISM
S
Body Diode Voltage
VSD
trr
TJ = 25 °C, IS = 11 A, VGS = 0 Vb
-
-
-
-
1.5
770
5.1
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
510
3.4
ns
µC
TJ = 25 °C, IF = 11 A, dI/dt = 100 A/µsb
Qrr
ton
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss effective is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS
.
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2
Document Number: 91094
S-81243-Rev. B, 21-Jul-08
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
10
1
100
VGS
15V
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
10
°
T = 150 C
J
°
T = 25 C
J
1
4.5V
V
= 50V
20µs PULSE WIDTH
DS
20µs PULSE WIDTH
°
T = 25 C
J
0.1
4.0
0.1
0.1
5.0
6.0
7.0 8.0
9.0
1
10
100
V
, Gate-to-Source Voltage (V)
V
, Drain-to-Source Voltage (V)
GS
Fig. 3 - Typical Transfer Characteristics
DS
Fig. 1 - Typical Output Characteristics
100
10
1
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VGS
11A
=
I
D
TOP
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
20µs PULSE WIDTH
J
4.5V
V
=10V
°
T = 150 C
GS
-60 -40 -20
0
20 40 60 80 100 120 140 160
1
10
100
°
T , Junction Temperature ( C)
V
, Drain-to-Source Voltage (V)
J
DS
Fig. 2 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91094
S-81243-Rev. B, 21-Jul-08
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3
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
2400
100
10
1
V
C
C
C
= 0V,
f = 1MHz
GS
iss
rss
oss
= C + C
,
C
SHORTED
gs
gd
gd
ds
= C
2000
1600
1200
800
400
0
= C + C
ds
gd
iss
oss
°
T = 150 C
J
°
T = 25 C
J
rss
V
= 0 V
GS
0.1
0.0
A
0.4
0.8
1.2
1.6
1
10
100
1000
V
,Source-to-Drain Voltage (V)
SD
V
, Drain-to-Source Voltage (V)
DS
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 7 - Typical Source-Drain Diode Forward Voltage
20
1000
I
D
=
OPERATION IN THIS AREA LIMITED
BY R
V
V
V
= 400V
= 250V
= 100V
DS(on)
DS
DS
DS
16
12
8
100
10us
10
100us
1ms
1
10ms
4
°
T = 25 C
C
°
T = 150 C
Single Pulse
J
FOR TEST CIRCUIT
SEE FIGURE 13
0.1
0
10
100
1000
10000
0
10
20
30
40
50
V
, Drain-to-Source Voltage (V)
DS
Fig. 8 - Maximum Safe Operating Area
Q , Total Gate Charge (nC)
G
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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4
Document Number: 91094
S-81243-Rev. B, 21-Jul-08
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
R
D
V
12
10
8
DS
V
GS
D.U.T.
R
G
+
-
V
DD
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
6
Fig. 10a - Switching Time Test Circuit
4
V
DS
90 %
2
0
25
50
75
100
125
150
°
T , Case Temperature ( C)
10 %
C
V
GS
t
t
t
t
d(off) f
d(on)
r
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
1
D = 0.50
0.20
0.1
0.10
P
2
DM
0.05
t
1
0.02
t
2
SINGLE PULSE
(THERMAL RESPONSE)
0.01
Notes:
1. Duty factor D =
t / t
1
2. Peak T =P
x Z
+ T
C
J
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (s)
1
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
V
DS
t
15 V
p
Driver
L
VDS
D.U.T.
IAS
RG
+
-
V
A
DD
A
20 V
I
0.01
Ω
tp
AS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91094
S-81243-Rev. B, 21-Jul-08
www.vishay.com
5
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
600
I
D
TOP
4.9A
7.0A
500
400
300
200
100
0
Q
Q
BOTTOM 11A
G
10 V
Q
GS
GD
V
G
Charge
Fig. 13a - Basic Gate Charge Waveform
25
50
75
100
125
150
Current regulator
°
Same type as D.U.T.
Starting T , Junction Temperature ( C)
J
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
50 kΩ
12 V
0.2 µF
0.3 µF
+
660
640
620
600
V
DS
D.U.T.
-
V
GS
3 mA
I
I
D
G
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
580
A
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
I
, Avalanche Current (A)
av
Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche
Current
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Document Number: 91094
S-81243-Rev. B, 21-Jul-08
IRFB11N50A, SiHFB11N50A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
Low stray inductance
D.U.T
•
• Ground plane
• Low leakage inductance
current transformer
-
+
-
-
+
RG
• dV/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Driver gate drive
P.W.
P.W.
Period
Period
D =
V
= 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode
forward drop
Inductor current
I
SD
Ripple ≤ 5 %
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91094.
Document Number: 91094
S-81243-Rev. B, 21-Jul-08
www.vishay.com
7
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
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information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
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Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
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