SIP12108中文资料_数据手册_规格书

SiP12108, SiP12108A

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Vishay Siliconix

2.8 V to 5.5 V Input

5 A Synchronous Buck Regulator

DESCRIPTION

FEATURES

• 2.8 V to 5.5 V input voltage

The SiP12108 is a high frequency current-mode constant

on-time (CM-COT) synchronous buck regulator with

integrated high-side and low-side power MOSFETs. Its

power stage is capable of supplying 5 A continuous current

at 4 MHz switching frequency. This regulator produces an

adjustable output voltage down to 0.6 V from 2.8 V to 5.5 V

input rail to accommodate a variety of applications,

including computing, consumer electronics, telecom, and

industrial.

• Adjustable output voltage down to 0.6 V

• 5 A continuous output current

• Programmable switching frequency up to 4 MHz

• 95 % peak efficiency

• Stable with any capacitor. No external ESR

network required.

• Ultrafast transient response

• Selectable power saving (PSM) mode or forced

continuous mode

SiP12108’s CM-COT architecture delivers ultra-fast

transient response with minimum output capacitance and

tight ripple regulation at very light load. The part is stable

with any capacitor type and no ESR network is required for

loop stability. The device also incorporates a power saving

scheme that significantly increases light load efficiency.

•

1 % accuracy of V_OUTsetting

• Pulse-by-pulse current limit

• Scalable with SiP12107 - 3 A

• SiP12108 is fully protected with OTP, SCP, UVP, OVP

• SiP12108A is fully protected with OTP, SCP, OVP

• PGOOD Indicator

The SiP12108 integrates a full protection feature set,

including output overvoltage protection (OVP), output under

voltage protection (UVP) and thermal shutdown (OTP). The

“A” version of the device, SiP12108A, does not have the

UVP feature. They also incorporate UVLO for the input rail

and an internal soft-start ramp.

• PowerCAD Simulation software available at

vishay.transim.com/login.aspx

• Material categorization: For definitions of compliance

please see www.vishay.com/doc?99912

The SiP12108 is available in lead (Pb)-free power enhanced

3 mm x 3 mm QFN-16 package.

APPLICATIONS

• Point of load regulation for low-power processors,

network processors, DSPs, FPGAs, and ASICs

• Low voltage, distributed power architectures with

3.3 V or 5 V rails

• Computing, broadband, networking, LAN/WAN, optical,

test and measurement

• A/V, high density cards, storage, DSL, STB, DVR, DTV,

Industrial PC

TYPICAL APPLICATION CIRCUIT

POWER SAVE MODE

ENABLE

POWER GOOD

PGOOD EN AUTO

V_OUT

INPUT = 2.8 V to 5.5 V

V_IN

LX

V_OUT

V_FB

AV_IN

GMO

R_ON

P_GND

A_GND

Fig. 1 - Typical Application Circuit for SiP12108

S13-2257-Rev. B, 11-Nov-13

Document Number: 62699

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SiP12108, SiP12108A

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ABSOLUTE MAXIMUM RATINGS

ELECTRICAL PARAMETER

CONDITIONS

Reference to P_GND

Reference to A_GND

Reference to P_GND

LIMIT

-0.3 to 6

UNIT

V_IN

AV_IN

LX

-0.3 to 6

V

A

_GNDto P_GND

-0.3 to +0.3

-0.3 to AV_IN+ 0.3

All Logic Inputs

Reference to A_GND

TEMPERATURE

Max. Operating Junction Temperature

Storage Temperature

150

°C

-65 to 150

POWER DISSIPATION

Junction to Ambient Thermal Impedance

36.3

°C/W

W

(R_thJA

)

Ambient temperature = 25 °C

Ambient temperature = 100 °C

3.4

1.3

Maximum Power Dissipation

ESD PROTECTION

HBM

4

kV

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation

of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING RANGE

ELECTRICAL PARAMETER

MINIMUM

TYPICAL

MAXIMUM

5.5

UNIT

V

V_IN

2.8

-1

-

AV_IN

-

5.5

LX

-

5.5

V_OUT

0.6

-

0.85 x V_IN

Ambient Temperature

-40 to 85

°C

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SiP12108, SiP12108A

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ELECTRICAL SPECIFICATIONS

TEST CONDITION

UNLESS OTHERWISE SPECIFIED

_IN= AV_IN= 3.3 V, T_A= -40 °C to 85 °C

LIMITS

UNIT

PARAMETER

SYMBOL

MIN.

TYP.

MAX.

V

POWER SUPPLY

Power Input Voltage Range

Bias Input Voltage Range

V_IN

2.8

-

5.5

V

AV_IN

Non- switching, I_O= 0 A,

Input Current

I_{IN_NOLOAD}

-

1200

-

R

_on= 100 k, AUTO = Low

μA

Shutdown Current

I_{IN_SHDN}

AV_{IN_UVLO}

EN = 0 V

-

2.3

-

6

9.5

2.8

-

AV_INUVLO Threshold

AV_INUVLO Hysteresis

PWM CONTROLLER

AV_INrising

2.55

300

V

AV_{IN_UVLO_HYS}

mV

T_A= 0 °C to +70 °C

0.594

0.600

2

0.606

Feedback Reference

V_FB

V

T_A= -40 °C to +85 °C

0.591

0.609

V_FBInput Bias Current

I_FB

g_m

-

200

nA

Transconductance

1

-

4

-

mS

GMO Source Current

GMO Sink Current

I_{GMO_SOURCE}

I_{GMO_SINK}

f_SW

-

50

μA

MHz

ns

-

50

Switching Frequency Range

Minimum On-Time

Guaranted by design

0.2

-

t_{ON_MIN}

t_{OFF_MIN}

t_SS

50

Minimum Off-Time

V_OUT= 1.2 V, R_ON= 100 k

-

125

1.5

Soft Start Time

-

ms

INTEGRATED MOSFETS

High-Side On Resistance

Low-Side On Resistance

FAULT PROTECTIONS

Over Current Limit

R_{ON_HS}

R_{ON_LS}

-

35

23

51

35

V_IN= AV_IN= 5 V

m

I_OCP

Inductor valley current

-

7.5

21

-

A

Output OVP Threshold

Output UVP Threshold

V_{FB_OVP}

V_{FB_UVP}

V_FBwith respect to 0.6 V reference

%

-25

160

30

Rising temperature

Hysteresis

Over Temperature Protection

POWER GOOD

°C

%

V_{FB_RISING_VTH_OV}

V_{FB_FALLING_VTH_UV}

R_{ON_PGOOD}

V_FBrising above 0.6 V reference

V_FBfalling below 0.6 V reference

-

21

-12.5

30

-

Power Good Output Threshold

Power Good On Resistance

Power Good Delay Time

ENABLE THRESHOLD

Logic High Level

60

-



t_{DLY_PGOOD}

4

μs

V_{EN_H}

V_{EN_L}

1.5

-

V

Logic Low Level

0.4

S13-2257-Rev. B, 11-Nov-13

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SiP12108, SiP12108A

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FUNCTIONAL BLOCK DIAGRAM

7

2

6

5

3

1,16

V_IN

AV_IN

PGOOD

EN

GMO

AUTO

AGND

8

OTP

V_IN

0.6 V

REFERENCE

UVLO

SOFT

START

V_IN

LX

+

ANTI-XCOND

CONTROL

LOGIC

SECTION

11,12,13

+ OTA

+

-

ON-TIME

GENERATOR

9

-

V_IN

V_FB

PWM COMPARATOR

I-V

Converter

I_sense

ZCD

OCP

P_GND

14,15

R_ON

4

-

+

V_OUT

UV Comparator

(SiP12108 only)

0.45 V

10

Current

Mirror

+

-

V_FB

0.72 V

OV Comparator

I_sense

PAD

Fig. 2 - SiP12108 Functional Block Diagram

ORDERING INFORMATION

MARKING

(LINE 2: P/N)

PART NUMBER

PACKAGE

SiP12108DMP-T1GE4

SiP12108ADMP-T1GE4⁽¹⁾

SiP12108DB

QFN16 3x3

2108

108A

N/A

SiP12108ADB⁽¹⁾

Note

(1)

Output undervoltage protection (UVP) disabled

P/N

FYWLL

Format:

Line 1: Dot

Line 2: P/N

Line 3: Siliconix Logo + ESD Symbol

Line 4: Factory Code + Year Code + Work Week Code + LOT Code

S13-2257-Rev. B, 11-Nov-13

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SiP12108, SiP12108A

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PIN CONFIGURATION

Vishay Siliconix

16 15 14 13

V_IN

AV_IN

EN

LX

1

2

3

4

12

11

10

9

LX

V_OUT

V_FB

R_ON

7

8

5

6

QFN16 3x3

Fig. 3 - SiP12108 Pin Configuration (Top View)



PIN CONFIGURATION

PIN NUMBER

NAME

FUNCTION

1, 16

V_IN

Input supply voltage for power MOS. V_IN= 2.8 V to 5.5 V

2

3

4

AV_IN

EN

Input supply voltage for internal circuitry. AV_IN= 2.8 V to 5.5 V

Enable pin. Pull enable above 1.5 V to enable the part and below 0.4 V to disable. Do not float this pin.

An external resistor between R_ONand GND sets the switching on time.

R_ON

Sets switching mode. Connect AUTO to AV_INfor forced continuous mode and AUTO to GND for power

save mode. Do not float.

5

AUTO

6

PGOOD

GMO

A_GND

V_FB

Power good output. Open drain.

7

Connect to an external RC network for loop compensation and droop function

Analog ground

8

9

Feedback voltage. 0.6 V (typ.). Use a resistor divider between V_OUTand A_GNDto set the output voltage.

V_OUT, output voltage sense connection

10

V_OUT

LX

11, 12, 13

14, 15

EP

Switching output, inductor connection point

P_GND

Power ground

Exposed paddle (bottom). Connect to a good PCB thermal ground plane.

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SiP12108, SiP12108A

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ELECTRICAL CHARACTERISTICS (V_IN= 3.3 V, L = 1 μH, C = 3 x 22 μF, f_SW= 1.2 MHz unless noted otherwise)

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

Vo - 1.8V

Vo- 1.8V

Vo - 1.2V

Vo -1.2V

0.01

0.1

1

10

0.01

0.1

1

10

I_OUT(A)

Fig. 4 - Efficiency - PWM Mode

Fig. 7 - Efficiency - PSM Mode

0.12

0.1

0.08

0.06

0.04

0.02

0

0.1

0.08

0.06

0.04

0.02

0

Vo - 1.2V

Vo - 1.8V

Vo - 1.2V

-0.02

-0.04

-0.02

-0.04

0.01

0.1

1

10

0.01

0.1

1

10

I_OUT(A)

Fig. 5 - Load Regulation - PWM Mode

Fig. 8 - Load Regulation - PSM Mode

1.2

1

1.2

1

Vo - 1.2V

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

Vo - 1.8V

0.01

0.1

1

10

0.01

0.1

1

10

I_OUT(A)

Fig. 6 - F_SWVariation - PWM Mode

Fig. 9 - F_SWVariation - PSM Mode

S13-2257-Rev. B, 11-Nov-13

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SiP12108, SiP12108A

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ELECTRICAL CHARACTERISTICS (V_IN= 3.3 V, L = 1 μH, C = 3 x 22 μF, f_SW= 1.2 MHz unless noted otherwise)

CH1

CH2

Fig. 10 - PWM Mode- Steady - State Ripple and LX, 5 A Load

CH1 = V_OUT, 20 mV/div, CH2 = LX, 2 V/div, Time = 1 μs/div

Fig. 13 - PWM Mode- Steady - State Ripple and LX, 0 A Load

CH1 = V_OUT, 20 mV/div, CH2 = LX, 2 V/div, Time = 1 μs/div

CH1

CH2

Fig. 11 - PSM Mode- Steady - State Ripple and LX, 0 A Load

CH1 = V_OUT, 20 mV/div, CH2 = LX, 2 V/div, Time = 10 ms/div

Fig. 14 - PSM Mode- Steady - State Ripple and LX, 0 A Load

CH1 = V_OUT, 20 mV/div, CH2 = LX, 2 V/div, Time = 1 μs/div

CH1

CH2

CH1

CH2

CH4

Fig. 12 - Load Step 0 A to 5 A to 0 A

CH1 = I_load, CH2 = V_OUT, 500 mV/div,

CH4 = I_coil, 5 A/div, Time = 100 μs/div

Fig. 15 - Load Step 0 A to 5 A, Rising Edge

CH1 = I_load, CH2 = V_OUT, 200 mV/div,

CH4 = I_coil, 5 A/div, Time = 20 μs/div

S13-2257-Rev. B, 11-Nov-13

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ELECTRICAL CHARACTERISTICS (V_IN= 3.3 V, L = 1 μH, C = 3 x 22 μF, f_SW= 1.2 MHz unless noted otherwise)

CH1

CH2

CH3

CH2

CH1

CH4

Fig. 16 - Load Step 0 A to 5 A, Falling Edge

CH1 = I_load, CH2 = V_OUT, 200 mV/div,

CH4 = I_coil, 5 A/div, Time = 20 μs/div

Fig. 19 - Turn-On Time PSM Mode, 0 A Load

CH1 = V_OUT, 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD,

5 V/div, CH4 = I_coil, 2 A/div, Time = 500 μs/div

CH2

CH3

CH1

CH2

CH3

CH1

CH4

Fig. 17 - Turn-Off Time PSM Mode, 0 A Load

CH1 = V_OUT, 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD,

5 V/div, CH4 = I_coil, 2 A/div, Time = 500 μs/div

Fig. 20 - Turn-On Time PWM Mode, 5 A Load

CH1 = V_OUT, 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD,

5 V/div, CH4 = I_coil, 2 A/div, Time = 500 μs/div

CH2

CH3

CH1

CH4

Fig. 18 - Turn-Off Time PWM Mode, 5 A Load

CH1 = V_OUT, 500 mV/div, CH2 = EN, 2 V/div, CH3 = PGOOD,

5 V/div, CH4 = I_coil, 2 A/div, Time = 500 μs/div

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OPERATIONAL DESCRIPTION

Device Overview

Power Stage

SiP12108 is a high-efficiency monolithic synchronous buck

regulator capable of delivering up to 5 A continuous current.

The device has programmable switching frequency up to

4 MHz. The control scheme is based on current-mode

constant-on-time architecture, which delivers fast transient

response and minimizes external components. Thanks to

the internal current ramp information, no high-ESR output

bulk or virtual ESR network is required for the loop stability.

This device also incorporates a power saving feature by

enabling diode emulation mode and frequency foldback as

load decreases.

SiP12108 integrated synchronous MOSFETs . The MOSFETs

are optimized to achieve 95 % efficiency at 2 MHz switching

frequency.

The power input voltage (V_IN) can go up to 5.5 V and as low

as 2.8 V for power conversion. The logic bias voltage (AV_IN)

ranges from 2.8 V to 5.5 V.

PWM Control Mechanism

SiP12108 employs a state-of-the-art current-mode COT

control mechanism. During steady-state operation, output

voltage is compared with internal reference (0.6 V typ.) and

the amplified error signal (V_COMP) is generated on the COMP

pin. In the meantime, inductor valley current is sensed, and

its slope (I_sense) is converted into a voltage signal (V_current) to

SiP12108 has a full set of protection and monitoring

features:

- Over current protection in pulse-by-pulse mode

- Output over voltage protection

be compared with V_COMP. Once V_currentis lower than V_COMP

,

a single shot on-time is generated for a fixed time

programmed by the external R_ON. Figure 4 illustrates the

basic block diagram for CM-COT architecture and figure 5

demonstrates the basic operational principle:



- Output under voltage protection with device latch

- Over temperature protection with hysteresis

- Dedicated enable pin for easy power sequencing

- Power Good open drain output

This device is available in QFN16 3x3 package to deliver

high power density and minimize PCB area.

R_ON

Bandgap

V_OUT

V_ref

HG

+

R1

R2

OTA

Control

V_IN

ON-TIME

Generator

Logic &

MOSFET

Driver

-

V_IN

LG

V_comp

+

-

HG

+

V_current

PWM

COMPARATOR

Current

Mirror

I_senseI-AMP

-

LS FET

LG

Fig. 21 - CM-COT Block Diagram

S13-2257-Rev. B, 11-Nov-13

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V_current

v_comp

Fixed ON-time

PWM

Fig. 22 - CM-COT Operational Principle

The following equation illustrates the relationship between

on-time, V_IN, V_OUTand R_ONvalue:

Once on-time is set, the pseudo constant frequency is then

determined by the following equation:

V_OUT

T_ON= R_ONx K x

, where K = 10.45 x 10^-12a constant set internally

D

V_IN

1

V_IN

¼ sw =

=

T_ON

V_OUT

V_IN

R

_ONx K

x R_ONx K



Loop Stability and Compensator Design

Due to the nature of current mode control, a simple RC network (type II compensator) is required between COMP and A_GNDfor

loop stability and transient response purposes. The general concept of this loop design is to introduce a single zero through the

compensator to determine the crossover frequency of overall close loop system.

The overall loop can be broken down into following segments.

Output feedback divider transfer function H_fb:

R_fb2

-----------------------------

=

H_fb

R_fb1x R_fb2

Voltage compensator transfer function G_COMP(s):

G_COMP(s) =

R_Ox 1 + sC_COMPR_COMP



-------------------------------------------------------------------------

gm

1 + sR_OC_COMP



Modulator transfer function H_mod(s):

R_loadx 1 + sC_OR_ESR



1

----------------------------------- -------------------------------------------------------------

H_mod(s) =

x

AV₁x R_DS(on)

1 + sC_OR_load

The complete loop transfer function is given by:

R_fb2R_Ox 1 + sC_COMPR_COMP



R_loadx 1 + sC_OR_ESR

1

----------------------------- -------------------------------------------------------------------------

----------------------------------- -------------------------------------------------------------

H_mod(s) =

x

gm x

x

R_fb1x R_fb2

1 + sR_OC_COMP



AV₁x R_DS(on)

1 + sC_OR_load

When:

C_COMP= Compensation capacitor

R_COMP= Compensation resistor

R_DS(on)= LS switch resistance

R_fb1

R_fb2

R_O

= Feedback resistor connect to LX

= Feedback resistor connect to ground

= Output impedance of error amplifier = 20 M

= Voltage to current gain = 3

gm

R_load= Load resistance

C_O= Output capacitor

= Error amplifier transconductance

AV₁

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SiP12108, SiP12108A

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Power Save Mode using AUTO Pin

To further improve efficiency at light loads, SiP12108

provides a set of innovative implementations to eliminate LS

recirculating current and switching losses. The internal Zero

Crossing Detector (ZCD) monitors LX node voltage to

determine when inductor current starts to flow negatively. In

power saving mode (PSM), as soon as inductor valley

current crosses zero, the device first deploys diode

emulation mode by turning off LS FET. If load further

decreases, switching frequency is further reduced

proportional to load condition to save switching losses. The

switching frequency is set by the controller to maintain

regulation. At zero load this frequency can go as low as

hundreds of Hz.

Whenever fixed frequency PWM operation is required over

the entire load span, the power saving mode feature can be

disabled by connecting AUTO pin to V_INor AV_IN.

OUTPUT MONITORING AND PROTECTION FEATURES

Output Over-Current Protection (OCP)

SiP12108 has pulse-by-pulse over-current limit control. The

inductor valley current is monitored during LS FET turn-on

period through R_DS(on)sensing. After a pre-defined time, the

valley current is compared with internal threshold (7.5 A typ.)

to determine the threshold for OCP. If monitored current is

higher than threshold, HS turn-on pulse is skipped and LS

FET is kept on until the valley current returns below OCP

limit.

In the severe over-current condition, pulse-by-pulse current

limit eventually triggers output under-voltage protection

(UVP), which latches the device off to prevent catastrophic

thermal-related failure. UVP is described in the next section.

OCP is enabled immediately after AV_INpasses UVLO level.

Figure 6 illustrates the OCP operation.

OCP_threshold

I_load

I_inductor

GH

Skipped GH Pulse

Fig. 23 - Over-Current Protection Illustration

Output Under-Voltage Protection (UVP)

UVP is implemented by monitoring output through V_FBpin.

Once the voltage level at V_FBis below 0.45 V for more than

20 μs, then UVP event is recognized and both HS and LS

MOSFETs are turned off. UVP latches the device off until

either AV_INor EN is recycled.

Over-Temperature Protection (OTP)

SiP12108 has internal thermal monitor block that turns off

both HS and LS FETs when junction temperature is above

160 °C (typ.). A hysteresis of 30 °C is implemented, so when

junction temperature drops below 130 °C, the device

restarts by initiating the soft-start sequence again.

UVP is only active after the completion of soft-start

sequence. This function only exists on SiP12108. On the “A”

version of the device, SiP12108A, this feature is disabled.

Soft Startup

SiP12108 deploys an internally regulated soft-start

sequence to realize a monotonic startup ramp without any

output overshoot. Once AV_INis above UVLO level (2.55 V

typ.). Both the reference and V_OUTwill ramp up slowly to

regulation in 1 ms (typ.) with the reference going from 0 V to

0.6 V and V_OUTrising monotonically to the programmed

output voltage.

Output Over-Voltage Protection (OVP)

For OVP implementation, output is monitored through V_FB

pin. After soft-start, if the voltage level at V_FBis above 21 %

(typ.), OVP is triggered with HS FET turning off and LS FET

turning on immediately to discharge the output. Normal

operation is resumed once V_FBdrops back to 0.6 V.

OVP is active immediately after AV_INpasses UVLO level.



During soft-start period, OCP is activated. OVP and

short-circuit protection are not active until soft-start is

complete.

S13-2257-Rev. B, 11-Nov-13

Document Number: 62699

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SiP12108, SiP12108A

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Pre-bias Startup

Vishay Siliconix

Power Good (PGOOD)

In case of pre-bias startup, output is monitored through V_FB

pin. If the sensed voltage on V_FBis higher than the internal

reference ramp value, control logic prevents HS and LS FET

from switching to avoid negative output voltage spike and

excessive current sinking through LS FET.

SiP12108’s Power Good is an open-drain output. Pull

PGOOD pin high up to 5 V through a 10K resistor to use this

signal. Power Good window is shown in the below diagram.

If voltage level on V_FBpin is out of this window, PGOOD

signal is de-asserted by pulling down to GND.

VFB_Rising_Vth_OV

(Typ. = 0.725 V)

VFB_Falling_Vth_OV

(Typ. = 0.675V)

Vref (0.6V)

VFB_Rising_Vth_UV

(Typ. = 0.575V)

VFB_Falling_Vth_UV

(Typ. = 0.525V)

V_FB

Pull-high

PGOOD

Pull-low

Fig. 24 - PGOOD Window and Timing Diagram

DESIGN PROCEDURE

The design process of the SiP12108 is quite straight

forward. Only few passive components such as output

capacitors, inductor and R_onresistor need to be selected.

Setting the Output Voltage

The output voltage is set by using a resistor divider on the

feedback (V_FB) pin. The V_FBpin is the negative input of the

internal error amplifier.

The following paragraph describes the selection procedure

for these peripheral components for a given operating

conditions.

When in regulation the V_FBvoltage is 0.6 V. The output

voltage V_Ois set based on the following formula.

In the next example the following definitions apply:

V_O= V_FB(1 + R1/R2)

V

_INmax.: the highest specified input voltage

where R1 and R2 are shown in figure 21.

_INmin.: the minimum effective input voltage subject to

voltage drops due to connectors, fuses, switches,

and PCB traces

Setting Switching Frequency

Selection of the switching frequency requires making a

trade-off between the size and cost of the external filter

components (inductor and output capacitor) and the power

conversion efficiency. The desired switching frequency,

1 MHz was chosen based on optimizing efficiency while

maintaining a small footprint and minimizing component

cost.

There are two values of load current to evaluate - continuous

load current and peak load current.

Continuous load current relates to thermal stress

considerations which drive the selection of the inductor and

input capacitors.

Peak load current determines instantaneous component

stresses and filtering requirements such as inductor

saturation, output capacitors, and design of the current limit

circuit.

In order to set the design for 1 MHz switching frequency,

(R_ON) resistor which determines the on-time (indirectly

setting the frequency) needs to be calculated using the

following equation.

The following specifications are used in this design:

• V_IN= 3.3 V 10 %

1

---------------------

--------------------------------------------------------------

R_ON

=

 105 k

1 x 10⁶x 10.45 x 10^-12

F_SWx K

• V_OUT= 1.2 V 1 %

• F_SW= 1 MHz

• Load = 5 A maximum

S13-2257-Rev. B, 11-Nov-13

Document Number: 62699

12

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SiP12108, SiP12108A

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INDUCTOR SELECTION

Vishay Siliconix

STABILITY CONSIDERATIONS

In order to determine the inductance, the ripple current must

first be defined. Cost, PCB size, output ripple, and efficiency

are all used in the selection process. Low inductor values

result in smaller size and allow faster transient performance

but create higher ripple current which can reduce efficiency.

Higher inductor values will reduce the ripple current while

compromising the efficiency (higher DCR) and transient

response.

Using the output capacitance as a starting point for

compensation values. Then, taking Bode plots and transient

response measurements we can fine tune the compensation

values.

Setting the crossover frequency to 1/5 of the switching

frequency: 

F₀= F_sw/5 = 1 MHz/5 = 200 kHz

Setting the compensation zero at 1/5 to 1/10 the crossover

The ripple current will also set the boundary for power-save

operation. The switcher will typically enter power-save

mode when the load current decreases to 1/2 of the ripple

current. For example, if ripple current is 1 A then power-save

operation will typically start at loads approaching 0.5 A.

Alternatively, if ripple current is set at 40 % of maximum load

current, then power-save will start for loads less than

~ 20 % of maximum current.

frequency for the phase boost:

F₀

5

1

F_Z

=

2π x R_Cx C_C

Setting C_C= 0.47 nF and solve for R_C

5

R_C=

=

= 8.469K

2π x C_Cx F₀

2π x 0.47 nF x 200K

Inductor selection for the SiP12108 should be designed

where the ripple current is ~ 50 % in all situations with V_IN

3.6 V and less.

SWITCHING FREQUENCY VARIATIONS

The switching frequency variation in COT can be mainly

attributed to the increase in conduction losses as the load

increases. The on time is “ideally constant” so the controller

must account for losses by reducing the off time which

increases the overall duty cycle. Hence the F_SWwill tend to

increase with load.

For example 3.3 V_INto 1.2 V_OUTat 1 MHz.

dI = V/L x dt = ((3.3 - 1.2)/0.33) x 0.36 = 2.3 A, %dI = 2.3/5

= 46 %.

For higher V_IN> 3.6 V ripple current should be set to less

then 40 %.

For 5 V_INto 1.2 V_OUTat 1 MHz dI = ((5 - 1.2)/0.68) x 0.36)

= 2 A, %dI = 2/5 = 40 %.

In power save mode (PSM) the IC will run in pulse skip mode

at light loads. As the load increases the F_SWwill increase

until it reaches the nominal set F_SW. This transition occurs

approximately when the load reaches to 20 % of the full load

current.

Output Capacitance Calculation

The output capacitance is usually chosen to meet transient

requirements. A worst-case load release, from maximum

load to no load at the exact moment when inductor current

is at the peak, determines the required capacitance. If the

load release is instantaneous (load changes from maximum

to zero in < 1/F_SWμs), the output capacitor must absorb all

the inductor’s stored energy. This will approximately cause

a peak voltage on the capacitor according to the following

equation.

DESIGN CONSIDERATION

For V_OUThigher then UVLO (2.55 V typ) and/or very slow V_IN

slew rates. The IC may have difficulty in starting-up because

V_INlevel is limiting how fast V_OUTcan rise. In these situations

a divider for EN pin threshold (~1.15 V) derived from V_IN

can be used. Allowing a higher V_INlevel before switching

begins and a smooth start-up. For example R_top= 60K and

R_bot= 25K when V_IN=4 V, EN level will be 1.18 V.

2

1

2





--

L x I_OUT

+

x I



^RIPPLEmax.

-------------------------------------------------------------------------

C_OUTmin.

=

V_peak²- V_OUT²

THERMAL DESIGN

The 16 pin package includes a thermal pad for much

better thermal performance when incorporated in the PCB

footprint. As shown in the PCB layout at the end of this

document. There are four vias evenly placed on the pad that

help transfer the heat to other layers. Tying the paddle to the

bottom layer through vias will provide the best thermal

performance.

Assuming a peak voltage V_PEAKof 1.3 V (100 mV rise upon

load release), and a 5 A load release, the required

capacitance is shown by the next equation.

1 μH x (5 A + 0.5 x (0.81 A))²

C_OUTmin.

=

= 116.8 μF

(1.3 V)²- (1.2 V)²

If the load release is relatively slow, the output capacitance

can be reduced. Using MLCC ceramic capacitors we will

use 5 x 22 μF or 110 μF as the total output capacitance.



S13-2257-Rev. B, 11-Nov-13

Document Number: 62699

13

For technical questions, contact: analogswitchtechsupport@vishay.com

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

SiP12108, SiP12108A

www.vishay.com

Vishay Siliconix

1

RON

1

MODE

PGOOD

COMP

5

6

AUTO

16

VIN2

PGND2

PGND1

LX1

PGOOD

COMP

15

14

13

7

8

AGND

17

AGND-PAD

Fig. 25 - Reference Board Schematic

14

S13-2257-Rev. B, 11-Nov-13

Document Number: 62699

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SiP12108, SiP12108A

www.vishay.com

Vishay Siliconix

BILL OF MATERIALS

ITEM QTY.

REFERENCE

VALUE

0.1 μF

22 μF

0.1 μF

470 pF

DNP

VOLTAGE

PCB FOOTPRINT

C0402-TDK

C0805-TDK

C0603-TDK

C0402-TDK

C0603-TDK

TP30

PART NUMBER

VJ0402Y104MXQCW1BC

LMK212BJ226MG-T

GRM188R71C104KA01D

VJ0402A471JXACW1BC

-

MANUFACTURER

Vishay

1

2

1

4

1

C1, C5

50 V

C2, C3, C4

10 V

Murata

4

C6

10 V

Murata

5

C7

50 V

TDK

6

C8 ⁽¹⁾

-

7

J1

VIN

-

5002K-ND

Keystone

Vishay

8

J2

VO

-

TP30

5002K-ND

9

J3

VO_GND

VIN_GND

MODE

PGOOD

EN

-

TP30

5002K-ND

10

11

12

13

14

15

16

17

18

19

J4

TP30

5002K-ND

J5

-

TP30

5002K-ND

J6

-

TP30

5002K-ND

J7

-

TP30

5002K-ND

L1

0.47 μH

100K

-

IHLP1616

R0402-Vishay

IHLP1616BZERR47M11

CRCW0402100KFKED

TNPW04026K04BETD

CRCW04025K11FKED

TNPW04022K55BETD

RC0402FR-071RL

R1, R2, R3, R4

50 V

Vishay

R5

R6

R7

R8

6K04

Vishay

5K11

Vishay

2K55

Vishay

1

Yageo

SiP12107,

SiP12108

20

1

U1

-

MLP33-16

SiP1210x

Vishay

S13-2257-Rev. B, 11-Nov-13

Document Number: 62699

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SiP12108, SiP12108A

www.vishay.com

Vishay Siliconix

PCB LAYOUT OF REFERENCE BOARD

Fig. 26 - Top Layer

Fig. 27 - Bottom Layer

S13-2257-Rev. B, 11-Nov-13

Document Number: 62699

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SiP12108, SiP12108A

www.vishay.com

Vishay Siliconix

MLP33-16L CASE OUTLINE

(5)

(4)

(1)

INCHES

MILLIMETERS

NOM.

DIMENSION

MIN.

0.75

0

MAX.

MIN.

0.029

0

NOM.

0.033

MAX.

0.037

0.002

A

A1

A3

b

0.85

-

0.95

0.05

-

0.20 REF

0.25

0.001 REF

0.010

0.18

1.5

0.30

1.7

0.007

0.059

0.012

0.067

D

3.00 BSC

1.6

0.118 BSC

0.063

D2

e

0.50 BSC

0.020 BSC

E

3.00 BSC

0.118 BSC

1.6

0.4

16

4

1.7

0.5

0.063

0.016

16

0.067

0.020

E2

L

1.5

0.3

0.059

0.012

N ⁽³⁾

Nd ⁽³⁾

Ne ⁽³⁾

4

Notes

(1)

(2)

(3)

(4)

(5)

(6)

Use millimeters as the primary measurement.

Dimensioning and tolerances conform to ASME Y14.5M. - 1994.

N is the number of terminals. Nd and Ne is the number of terminals in each D and E site respectively.

Dimensions b applies to plated terminal and is measured between 0.15 mm and 0.30 mm from terminal tip.

The pin 1 identifier must be existed on the top surface of the package by using identification mark or other feature of package body.

Package warpage max. 0.05 mm.



Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon

Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and

reliability data, see www.vishay.com/ppg?62699.

S13-2257-Rev. B, 11-Nov-13

Document Number: 62699

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Legal Disclaimer Notice

www.vishay.com

Vishay

Disclaimer



ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE

RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.

Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,

“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other

disclosure relating to any product.

Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or

the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all

liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,

consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular

purpose, non-infringement and merchantability.

Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of

typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding

statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a

particular product with the properties described in the product specification is suitable for use in a particular application.

Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over

time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s

technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,

including but not limited to the warranty expressed therein.

Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining

applications or for any other application in which the failure of the Vishay product could result in personal injury or death.

Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.

Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for

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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document

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Revision: 13-Jun-16

Document Number: 91000

1

型号	制造商	描述	价格	文档
SiP12108A	VISHAY	Adjustable output voltage down to 0.6 V	获取价格
SIP12108ADB	VISHAY	Switching Regulator	获取价格
SiP12108ADMP-T1GE4	VISHAY	Adjustable output voltage down to 0.6 V	获取价格
SIP12108DB	VISHAY	Switching Regulator,	获取价格
SIP12108DMP-T1GE4	VISHAY	Switching Regulator, Current-mode, 4000kHz Switching Freq-Max, QFN-16	获取价格
SIP12109	VISHAY	4 A continuous output current	获取价格
SiP12109DB	VISHAY	4 A continuous output current	获取价格
SiP12109DMP-T1-GE4	VISHAY	4 A continuous output current	获取价格
SIP12110	VISHAY	6 A, 4.5 V to 15 V Input Synchronous Buck Regulator	获取价格
SiP12110DB	VISHAY	6 A, 4.5 V to 15 V Input Synchronous Buck Regulator	获取价格

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