SIP43101DQ-T1-E3 [VISHAY]

IC 1.1 A BUF OR INV BASED PRPHL DRVR, PDSO16, LEAD FREE, TSSOP-16, Peripheral Driver;
SIP43101DQ-T1-E3
型号: SIP43101DQ-T1-E3
厂家: VISHAY    VISHAY
描述:

IC 1.1 A BUF OR INV BASED PRPHL DRVR, PDSO16, LEAD FREE, TSSOP-16, Peripheral Driver

驱动 光电二极管 接口集成电路
文件: 总6页 (文件大小:100K)
中文:  中文翻译
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SiP43101  
Vishay Siliconix  
Dual Output Power Switch with Inverting Input  
FEATURES  
D Two Output Power Switches  
D Current Limit Protection  
D Total Output Drive — 200 mA Continuous  
D 9-V to 35-V Supply Voltage Range  
D Low Side or High Side Switch Configuration  
D Thermal Shutdown Protection  
D UVLO With User Programmable Time Delay  
Pb-free  
Available  
D User Programmable Phasing of Output Switches  
APPLICATIONS  
D Internal Output Over Voltage Clamp For Driving Inductive  
D Optical Detectors for Factory Automation  
Loads  
DESCRIPTION  
SiP43101 is a dual power switch IC which contains all control  
and power switching circuitry required to drive resistive and  
inductive loads in industrial applications. The output switches  
are NPN power transistors which can be configured as either  
high-side or low-side switches. These switches can operate  
from voltages as high as 35 V and have a continuous output  
current rating of 200 mA, combined or individually. Internal  
zener diodes are provided to clamp the power switch voltages  
to safe levels when driving inductive loads. The IN1 pin is a  
non-inverting input which controls the output of switch 1.  
A 2-input Exclusive OR gate input controls switch 2, allowing  
switch 2 to be controlled by either an inverting or non-inverting  
control signal. SiP43101 contains under voltage lockout,  
UVLO, a user definable turn on delay, current limit, short  
circuit protection, and thermal shutdown.  
The SiP43101 is available in both standard and lead (Pb)-free  
16-pin TSSOP and PowerPAKr MLP-44 packages, which are  
specified over the industrial, D suffix (–40 to 85_C) tem–  
perature range.  
TYPICAL APPLICATION CIRCUIT  
+10 to 30 V  
5 V  
100 nF  
Load  
Load  
SiP43101  
V
CC  
1 k  
R1  
C
2
FAULT  
E
2
IN  
1
INPUT  
IN  
2A  
IN  
C
C
2B  
1
E
DEL  
1
R2  
GND  
100 nF  
GND  
Both Switches Configured as Low-Side, Switch 2 Inverted With Respect to Switch 1, R1 +R2 Set Logic High  
Document Number: 72640  
S-51493, Rev. D—15-Aug-05  
www.vishay.com  
1
SiP43101  
Vishay Siliconix  
ABSOLUTE MAXIMUM RATINGS  
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V  
Power Dissipation  
CC  
a
TSSOP-16 @ 85_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 mW  
C1, E1, C2, E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 V  
C1-E1, C2-E2 (clamped by internal circuitry) . . . . . . . . . . . . . . . . . . . . . . 52 V  
b
PowerPAK MLP44-16 @ 85_C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 mW  
Thermal Impedance (  
c
)
Output Current  
JA  
TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90_C/W  
Continuous for one Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA  
Peak for one Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 A  
d
PowerPAK MLP44-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47_C/W  
FAULT Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA  
FAULT Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V t0 V + 0.3 V  
CC  
Notes  
a. Derate 11.1 mW/_C  
c. Device mounted on JEDEC compliant two layer test board.  
d. Device mounted on JEDEC compliant four layer test board.  
IN , IN , IN  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V t0 V + 0.3 V  
CC  
1
2A  
2B  
b. Derate 21.3 mW/_C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150_C  
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C  
Currents are positive into, negative out of the specificed terminal.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
RECOMMENDED OPERATING RANGE  
V
CC  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 to 32 V  
Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 to 85_C  
SPECIFICATIONS  
Test Conditions Unless Specified  
Limits  
V
CC  
= 25 V,IN1, IN2 = 0 V, IN1, IN2, INV2 = 5 V  
Parameter  
Symbol  
Mina  
Typb Maxa  
Unit  
C
DEL  
= 10 nF, T = T  
A J  
Power Supply  
Supply Voltage  
Supply Current  
V
I
9
32  
V
CC  
–40 to 85_C, Both Inputs Enabled  
6
9
mA  
CC  
Logic Inputs (IN1, IN2A, IN2B  
)
Digital Input High Level  
V
3.5  
IH  
V
A
Digital Input Low Level  
V
1.5  
IL  
Input Bias Current, Low Level  
Input Bias Current, High Level  
I
IL  
IN , IN , IN = 0 V  
–0.40  
0.02  
1
2A  
2B  
I
IH  
IN , IN , IN = 5 V  
1 2A 2B  
Switches 1&2 – High Side Configuration  
Rise Time (Off to On)  
Rise Tiem (On to Off)  
t
300  
300  
r
R
= 250 to GND, C , C = 25 V  
ns  
V
LOAD  
1
2
t
f
T
= 25 _C  
1.3  
1.5  
A
Saturation Voltage  
V
I
R
LOAD  
= 125 to GND  
SATHS  
T
A
= –40 _C  
Current Limit  
R
= 0.25 to GND, T = 25 _C  
1.1  
52  
A
A
V
LIMHS  
LOAD  
A
Leakage Current  
Voltabe Clamp  
I
E , E = GND, C , C = 25 V,IN , IN , IN = 0 V  
5
LHS  
1
2
1
2
1
2A  
2B  
V
Measure (V – V ) or (V – V  
C1 E1 C2 E2  
)
CLHS  
Switches 1&2 – Low Side Configuration  
Rise Time (On to Off)  
Rise Tiem (Off to On)  
t
400  
350  
r
R
= 250 to V , L  
= 25 V to C , C  
2
ns  
V
LOAD  
CC OAD  
1
t
f
T
= 25 _C  
1.3  
1.5  
A
Saturation Voltage  
V
I
R
= 125 to V  
CC  
SATLS  
LOAD  
T
A
= –40 _C  
Current Limit  
R
= 0.25 to V , T = 25 _C  
1.1  
52  
A
A
V
LIMLS  
LOAD  
CC  
A
Leakage Current  
Voltabe Clamp  
I
E , E = GND, C , C = 25 V,IN , IN , IN = 0 V  
1
5
LLS  
2
1
2
1
2A  
2B  
V
Measure (V – V ) or (V – V  
C1 E1 C2 E2  
)
CLLS  
Document Number: 72640  
S-51493, Rev. D—15-Aug-05  
www.vishay.com  
2
SiP43101  
Vishay Siliconix  
SPECIFICATIONS  
Test Conditions Unless Specified  
Limits  
V
CC  
= 25 V,IN1, IN2 = 0 V, IN1, IN2, INV2 = 5 V  
Parameter  
Symbol  
Mina  
Typb Maxa  
Unit  
C
DEL  
= 10 nF, T = T  
A J  
Turn-On Delay  
C
C
Maximum Voltage  
Threshold  
V
4.7  
4
DEL  
DEL  
V
A
V
DELTH  
DEL  
I
I
2.5  
CDEL  
CDEL  
FAULT Output  
V
CESAT  
Conducting State (On)  
V
SDON  
Load on FAULT v 10 mA  
0.4  
V
Operating Frequency  
Switching Frequency  
f
25  
kHz  
SW  
Under Voltage Lockout  
UVLO Threshold  
UVLO Hysteresis  
V
7.5  
0.4  
8
8.5  
0.6  
UVLO  
V
V
0.5  
HYS  
Thermal Shutdown  
Thermal Shutdown Threshold  
Hysteresis  
T
160  
20  
_C  
T
HYS  
Notes  
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (–40_ to 85_C).  
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing and are measured at V = 12 V unless otherwise noted.  
CC  
PIN CONFIGURATION  
TSSOP-16  
C
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
2
V
CC  
NC  
FAULT  
E
2
C
DEL  
TSSOPĆ16  
ORDERING INFORMATION  
NC  
NC  
Top View  
NC  
GND  
E
1
Standard  
Part Number  
Lead (Pb)-Free  
Part Number  
Temperature  
Range  
IN  
IN  
2B  
2A  
Marking  
NC  
SiP43101DQ-T1  
SiP43101DQ-T1—E3  
–40 to 85_C  
43101  
IN  
C
1
1
PowerPAK MLP-44  
C
2
NC  
V
CC  
FAULT  
13  
14  
15  
16  
E
C
DEL  
2
12  
11  
10  
9
1
PowerPAK MLPĆ44  
ORDERING INFORMATION  
NC  
NC  
GND  
NC  
2
3
4
Standard  
Lead (Pb)-Free  
Part Number  
Temperature  
Range  
Marking  
Part Number  
SiP43101DLP-T1  
SiP43101DLP-T1–E3  
–40 to 85_C  
43101  
E
IN2B  
1
8
7
6
5
C
1
NC  
IN  
1
IN  
2A  
Bottom View  
Document Number: 72640  
S-51493, Rev. D—15-Aug-05  
www.vishay.com  
3
SiP43101  
Vishay Siliconix  
PIN DESCRIPTION  
Pin Number  
TSSOP-16  
MLP44-16  
Name  
Function  
1
V
Positive Supply Voltage  
15  
16  
1
CC  
2
3
FAULT  
Open collector output that is switched low on in the event of Short Circuit or Thermal Shut Down.  
Connection for the external capacitor controlling the turn on delay.  
C
DEL  
4, 10, 12, 13,  
15  
3, 7, 10, 11, 14  
NC  
No connection  
5
6
2
4
GND  
Ground Pin.  
IN  
2B  
IN  
2A  
Input to the Exclusive OR controlling power switch 2.  
Input to the Exclusive OR controlling power switch 2.  
Input controlling power switch 1.  
Collector of power switch 1.  
7
5
8
6
IN  
1
9
8
C
1
11  
14  
16  
9
E
E
Emitter of power switch 1.  
1
2
12  
13  
Emitter of power switch 2.  
C
Collector of power switch 2.  
2
DETAILED PIN DESCRIPTION  
CDEL  
E1  
This pin is the emitter of Switch 1. This pin is connected to the  
load in the High-Side Switch configuration, and is connected  
to Ground in the Low-Side configuration.  
A capacitor connected to this pin is used to set the duration  
the turn on delay. The delay starts after the UVLO threshold  
has been reached.  
E2  
IN1  
This pin is the emitter of switch 2. This pin is connected to the  
load in the High-Side switch configuration, and is connected  
to Ground in the Low-Side configuration.  
This pin controls the state of the output NPN switch 1. A  
Logic 0 holds the switch off while a Logic 1 turns the switch on.  
C1  
IN2A, IN2B  
This pin is the collector of switch 1. This pin is connected to the  
VCC in the High-Side switch configuration, and is connected  
to the load in the Low-Side configuration.  
These pins are the inputs to the Exclusive OR gate that  
controls the state of the output NPN switch 2. This allows the  
use of either a non-inverting or an inverted signal to control the  
switch. Refer to the truth table for the logic function  
description.  
C2  
This pin is the collector of switch 2. This pin is connected to the  
VCC in the High-Side switch configuration, and is connected  
to the load in the Low-Side configuration.  
IN2A  
IN2B  
SWITCH 2  
FAULT  
Low  
Low  
High  
High  
Low  
High  
Low  
High  
Off  
On  
On  
Off  
This pin is an open collector output that is pulled to Ground in  
the event of a short circuit, an overcurrent, or a thermal shut  
down  
Document Number: 72640  
S-51493, Rev. D—15-Aug-05  
www.vishay.com  
4
SiP43101  
Vishay Siliconix  
FUNCTIONAL BLOCK DIAGRAM  
V
CC  
Reference  
C
2
C
DEL  
UVLO  
Reset  
E
2
Control  
Logic  
C
1
FAULT  
Short Citcuit  
Thermal Shut Down  
E
1
IN  
IN  
2B  
2A  
IN  
1
GND  
DETAILED OPERATION  
Turn On Delay  
Short Circuit and Overcurrent indication  
When an overcurrent or short circuit condition occurs on  
either switch, the SiP43101 enters a hiccup current limiting  
mode. In this mode, the capacitor on CDEL is discharged  
down to 3 V, thus turning off the output switches, and then is  
charged up to 4 V by a 2.5- A internal current source, thus  
turning the switches on again. If the overcurrent or short circuit  
condition remains this cycle will continue. The switches are  
enabled at a very low duty cycle, minimizing the power  
dissipation and protecting the switches from damage.  
The turn on delay prohibits the output switches from being  
turned on for a period of time after VCC has passed through  
8 V and the undervoltage condition no longer exists. The  
UVLO function keeps the external CDEL capacitor discharged  
until VCC is greater than 8 V. Subsequently, an internal 2.5- A  
current source charges the capacitor from GND to 4.7 V. A  
comparator detects when the voltage on CDEL passes  
through 4 V and enables the output switches. The delay time  
is a function of the capacitor value and is defined as  
1.6 ms/nF.  
The FAULT output will switch to GND, indicating that an  
overload condition or short circuit condition exists.  
An external switch can be connected across the capacitor to  
disable the output switches and reset the time delay.  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and  
Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see  
http://www.vishay.com/ppg?72640.  
Document Number: 72640  
S-51493, Rev. D—15-Aug-05  
www.vishay.com  
5
Legal Disclaimer Notice  
Vishay  
Disclaimer  
All product specifications and data are subject to change without notice.  
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf  
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein  
or in any other disclosure relating to any product.  
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any  
information provided herein to the maximum extent permitted by law. The product specifications do not expand or  
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed  
therein, which apply to these products.  
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this  
document or by any conduct of Vishay.  
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless  
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such  
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting  
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding  
products designed for such applications.  
Product names and markings noted herein may be trademarks of their respective owners.  
Document Number: 91000  
Revision: 18-Jul-08  
www.vishay.com  
1

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