SQS850EN [VISHAY]
Automotive N-Channel 60 V (D-S) 175 °C MOSFET;
| 型号： | SQS850EN |
| 厂家： | 
VISHAY |
| 描述： | Automotive N-Channel 60 V (D-S) 175 °C MOSFET |
| 文件： | 总14页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SQS850EN
Vishay Siliconix
www.vishay.com
Automotive N-Channel 60 V (D-S) 175 °C MOSFET
FEATURES
• TrenchFET® power MOSFET
PRODUCT SUMMARY
VDS (V)
60
• AEC-Q101 qualified
R
DS(on) (Ω) at VGS = 10 V
DS(on) (Ω) at VGS = 4.5 V
0.0215
0.0261
12
• 100 % Rg and UIS tested
R
• Material categorization:
ID (A)
for definitions of compliance please see
www.vishay.com/doc?99912
Configuration
Single
PowerPAK® 1212-8 Single
D
D
D
7
8
D
6
D
5
G
1
2
S
S
3
S
4
G
1
N-Channel MOSFET
Top View
Bottom View
S
Marking Code: Q019
ORDERING INFORMATION
Package
PowerPAK 1212-8
SQS850EN-T1-GE3
Lead (Pb)-free and Halogen-free
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
60
V
VGS
20
TC = 25 °C
12
Continuous Drain Current a
ID
T
C = 125 °C
12
Continuous Source Current (Diode Conduction) a
Pulsed Drain Current b
IS
12
A
IDM
IAS
48
Single Pulse Avalanche Current
Single Pulse Avalanche Energy
23
L = 0.1 mH
EAS
26
33
mJ
W
TC = 25 °C
Maximum Power Dissipation b
PD
TC = 125 °C
11
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature) d, e
TJ, Tstg
-55 to +175
260
°C
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
RthJA
LIMIT
81
UNIT
Junction-to-Ambient
PCB Mount c
°C/W
Junction-to-Case (Drain)
RthJC
4.5
Notes
a. Package limited.
b. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
c. When mounted on 1" square PCB (FR4 material).
d. See solder profile (www.vishay.com/doc?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed
and is not required to ensure adequate bottom side solder interconnection.
e. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
S14-2054-Rev. B, 20-Oct-14
Document Number: 62855
1
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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SQS850EN
Vishay Siliconix
www.vishay.com
SPECIFICATIONS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX. UNIT
Static
Drain-Source Breakdown Voltage
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS
VGS(th)
IGSS
VGS = 0 V, ID = 250 μA
VDS = VGS, ID = 250 μA
60
1.5
-
-
2.0
-
-
V
2.5
VDS = 0 V, VGS
VGS = 0 V
=
20 V
100
1
nA
μA
A
VDS = 60 V
-
-
Zero Gate Voltage Drain Current
On-State Drain Current a
IDSS
V
GS = 0 V
GS = 0 V
VDS = 60 V, TJ = 125 °C
VDS = 60 V, TJ = 175 °C
VDS ≥ 5 V
-
-
50
150
-
V
-
-
ID(on)
VGS = 10 V
20
-
-
V
V
V
GS = 10 V
GS = 10 V
GS = 10 V
ID = 6.1 A
0.0180 0.0215
ID = 6.1 A, TJ = 125 °C
ID = 6.1 A, TJ = 175 °C
ID = 5.5 A
-
-
-
0.0360
0.0460
Drain-Source On-State Resistance a
RDS(on)
Ω
-
V
GS = 4.5 V
-
0.0218 0.0261
Forward Transconductance b
Dynamic b
gfs
VDS = 15 V, ID = 6.1 A
-
33
-
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge c
Gate-Source Charge c
Gate-Drain Charge c
Gate Resistance
Turn-On Delay Time c
Rise Time c
Turn-Off Delay Time c
Fall Time c
Ciss
Coss
Crss
Qg
-
-
1617
132
53
2021
165
66
V
GS = 0 V
VDS = 30 V, f = 1 MHz
pF
-
-
27.4
4.9
4.6
1.25
9
41
Qgs
Qgd
Rg
V
GS = 10 V
VDS = 30 V, ID = 8.7 A
f = 1 MHz
-
-
nC
-
-
0.6
-
2.5
13.4
14.4
38
Ω
td(on)
tr
td(off)
tf
-
9.6
25
VDD = 30 V, RL = 30 Ω
ID ≅ 1 A, VGEN = 10 V, Rg = 1 Ω
ns
-
-
9.3
14
Source-Drain Diode Ratings and Characteristics b
Pulsed Current a
ISM
-
-
-
48
A
V
Forward Voltage
VSD
IF = 4 A, VGS = 0 V
0.78
1.2
Notes
a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
S14-2054-Rev. B, 20-Oct-14
Document Number: 62855
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQS850EN
Vishay Siliconix
www.vishay.com
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
30
24
18
12
6
30
24
18
12
6
VGS = 10 V thru 4 V
TC = 25 °C
VGS = 3 V
TC = 125 °C
TC = - 55 °C
0
0
0
1
2
3
4
5
0
1
2
3
4
5
VGS - Gate-to-Source Voltage (V)
VDS - Drain-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
5.0
4.0
3.0
2.0
1.0
0.0
60
48
36
24
12
0
TC = - 55 °C
TC = 25 °C
TC = 125 °C
TC = 25 °C
TC = 125 °C
TC = - 55 °C
0
1
2
3
4
5
0.0
3.0
6.0
9.0
12.0
15.0
ID - Drain Current (A)
VGS - Gate-to-Source Voltage (V)
Transfer Characteristics
Transconductance
2500
2000
1500
1000
500
0.05
0.04
0.03
0.02
0.01
0.00
Ciss
VGS = 4.5 V
VGS = 10 V
Coss
Crss
0
0
10
20
30
40
50
60
0
6
12
18
24
30
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
S14-2054-Rev. B, 20-Oct-14
Capacitance
Document Number: 62855
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQS850EN
Vishay Siliconix
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TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
2.5
2.0
1.5
1.0
0.5
10
I
V
D = 8.7 A
DS = 30 V
ID = 5.3 A
8
VGS = 10 V
6
4
VGS = 4.5 V
2
0
- 50 - 25
0
25
50
75 100 125 150 175
0
6
12
18
24
30
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
100
10
0.10
0.08
0.06
0.04
0.02
0.00
TJ = 150 °C
1
TJ = 150 °C
0.1
TJ = 25 °C
0.01
0.001
TJ = 25 °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0
2
4
6
8
10
VGS - Gate-to-Source Voltage (V)
VSD - Source-to-Drain Voltage (V)
Source Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
0.5
0.2
90
85
80
75
70
ID = 1 mA
- 0.1
- 0.4
- 0.7
- 1.0
ID = 5 mA
ID = 250 μA
- 50 - 25
0
25
50
75 100 125 150 175
- 50 - 25
0
25
50
75 100 125 150 175
TJ - Junction Temperature (°C)
TJ - Temperature (°C)
Threshold Voltage
Drain Source Breakdown vs. Junction Temperature
S14-2054-Rev. B, 20-Oct-14
Document Number: 62855
4
For technical questions, contact: automostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SQS850EN
Vishay Siliconix
www.vishay.com
THERMAL RATINGS (TA = 25 °C, unless otherwise noted)
100
IDM Limited
100 μs
1 ms
10
1
Limited by RDS(on)
*
ID Limited
10 ms
100 ms, 1 s, 10 s, DC
0.1
TC = 25 °C
Single Pulse
BVDSS Limited
0.01
0.01
0.1
1
10
100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
1
Duty Cycle = 0.5
0.2
0.1
Notes:
0.1
P
DM
0.05
t
1
t
2
t
t
1
2
0.02
1. Duty Cycle, D =
2. Per Unit Base = R
= 81 °C/W
thJA
(t)
3. T - T = P
Z
JM
A
DM thJA
Single Pulse
4. Surface Mounted
0.01
-4
-3
-2
-1
10
10
10
10
1
100
1000
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
S14-2054-Rev. B, 20-Oct-14
Document Number: 62855
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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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SQS850EN
Vishay Siliconix
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THERMAL RATINGS(TA = 25 °C, unless otherwise noted)
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
-4
-3
-2
-1
10
10
10
Square Wave Pulse Duration (s)
10
1
Normalized Thermal Transient Impedance, Junction-to-Case
Note
•
The characteristics shown in the two graphs
- Normalized Transient Thermal Impedance Junction-to-Ambient (25 °C)
- Normalized Transient Thermal Impedance Junction-to-Case (25 °C)
are given for general guidelines only to enable the user to get a “ball park” indication of part capabilities. The data are extracted from single
pulse transient thermal impedance characteristics which are developed from empirical measurements. The latter is valid for the part
mounted on printed circuit board - FR4, size 1" x 1" x 0.062", double sided with 2 oz. copper, 100 % on both sides. The part capabilities
can widely vary depending on actual application parameters and operating conditions.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62855.
S14-2054-Rev. B, 20-Oct-14
Document Number: 62855
6
For technical questions, contact: automostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Ordering Information
www.vishay.com
Vishay Siliconix
PowerPAK® 1212-8 and PowerPAK 1212-8W
Ordering codes for the SQ rugged series power MOSFETs in the PowerPAK 1212-8 and PowerPAK 1212-8W packages:
DATASHEET PART NUMBER
SQ7414AEN
SQ7414AENW
SQ7415AEN
SQ7415AENW
SQS401EN
OLD ORDERING CODE a
SQ7414AEN-T1-GE3
-
NEW ORDERING CODE
SQ7414AEN-T1_GE3
SQ7414AENW-T1_GE3
SQ7415AEN-T1_GE3
SQ7415AENW-T1_GE3
SQS401EN-T1_GE3
SQS401ENW-T1_GE3
SQS405EN-T1_GE3
SQS405ENW-T1_GE3
SQS420EN-T1_GE3
SQS423EN-T1_GE3
SQS460EN-T1_GE3
SQS462EN-T1_GE3
SQS482EN-T1_GE3
SQS484EN-T1_GE3
SQS490EN-T1_GE3
SQS840EN-T1_GE3
SQS850EN-T1_GE3
SQ7415AEN-T1-GE3
-
SQS401EN-T1-GE3
-
SQS401ENW
SQS405EN
SQS405EN-T1-GE3
-
SQS405ENW
SQS420EN
SQS420EN-T1-GE3
SQS423EN-T1-GE3
SQS460EN-T1-GE3
SQS462EN-T1-GE3
SQS482EN-T1-GE3
SQS484EN-T1-GE3
SQS490EN-T1-GE3
SQS840EN-T1-GE3
SQS850EN-T1-GE3
SQS423EN
SQS460EN
SQS462EN
SQS482EN
SQS484EN
SQS490EN
SQS840EN
SQS850EN
Note
a. Old ordering code is obsolete and no longer valid for new orders
Revision: 25-Aug-15
Document Number: 66697
1
For technical questions, contact: automostechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® 1212, (Single/Dual)
L
H
E2
E4
K
W
8
1
4
1
2
3
4
Z
2
5
L1
E3
Backside View of Single Pad
A1
L
H
K
E2
E4
H
2
E1
E
1
2
3
4
Detail Z
D1
D2
Notes:
1. Inch will govern
2
Dimensions exclusive of mold gate burrs
3. Dimensions exclusive of mold flash and cutting burrs
E3
Backside View of Dual Pad
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
1.12
0.05
0.41
0.33
3.61
3.21
2.70
MIN.
0.031
0
MAX.
0.044
0.002
0.016
0.013
0.142
0.126
0.106
A
A1
b
0.79
0
0.23
0.13
3.00
2.95
1.98
0.009
0.005
0.118
0.116
0.078
c
D
D1
D2
D4
E
0.31 TYP.
0.012 TYP.
3.00
2.95
1.47
1.75
3.61
3.21
2.21
1.98
0.118
0.116
0.058
0.069
0.142
0.126
0.087
0.078
E1
E2
E3
E4
e
0.535 TYP.
0.65 BSC
0.61
0.021 TYP.
0.026 BSC
0.024
K
K1
H
0.35
0.014
0.15
0.15
0.051
0°
0.51
0.56
0.204
12°
0.006
0.006
0.002
0°
0.020
0.022
0.008
12°
L
L1
θ
W
M
0.15
0.36
0.006
0.014
0.125 TYP.
0.005 TYP.
ECN: C15-0077-Rev. K, 26-Jan-15
DWG: 5882
Revison: 26-Jan-15
Document Number: 71656
1
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
AN822
Vishay Siliconix
®
PowerPAK 1212 Mounting and Thermal Considerations
Johnson Zhao
MOSFETs for switching applications are now available
The PowerPAK 1212-8 has a footprint area compara-
ble to TSOP-6. It is over 40 % smaller than standard
TSSOP-8. Its die capacity is more than twice the size
of the standard TSOP-6’s. It has thermal performance
an order of magnitude better than the SO-8, and 20
times better than TSSOP-8. Its thermal performance is
better than all current SMT packages in the market. It
will take the advantage of any PC board heat sink
capability. Bringing the junction temperature down also
increases the die efficiency by around 20 % compared
with TSSOP-8. For applications where bigger pack-
ages are typically required solely for thermal consider-
ation, the PowerPAK 1212-8 is a good option.
with die on resistances around 1 mΩ and with the
capability to handle 85 A. While these die capabilities
represent a major advance over what was available
just a few years ago, it is important for power MOSFET
packaging technology to keep pace. It should be obvi-
ous that degradation of a high performance die by the
package is undesirable. PowerPAK is a new package
technology that addresses these issues. The PowerPAK
1212-8 provides ultra-low thermal impedance in a
small package that is ideal for space-constrained
applications. In this application note, the PowerPAK
1212-8’s construction is described. Following this,
mounting information is presented. Finally, thermal
and electrical performance is discussed.
Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
space constraints.
THE PowerPAK PACKAGE
The PowerPAK 1212-8 package (Figure 1) is a deriva-
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is
mounted on. The PowerPAK 1212-8 thus translates
the benefits of the PowerPAK SO-8 into a smaller
package, with the same level of thermal performance.
PowerPAK 1212 SINGLE MOUNTING
To take the advantage of the single PowerPAK 1212-8’s
thermal performance see Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 single in the index of this
document.
(Please refer to application note “PowerPAK SO-8
Mounting and Thermal Considerations.”)
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
2
area of about 0.3 to 0.5 in of will yield little improve-
ment in thermal performance.
Figure 1. PowerPAK 1212 Devices
Document Number 71681
03-Mar-06
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AN822
Vishay Siliconix
PowerPAK 1212 DUAL
To take the advantage of the dual PowerPAK 1212-8’s
thermal performance, the minimum recommended
land pattern can be found in Application Note 826,
Recommended Minimum Pad Patterns With Outline
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
ture profile used, and the temperatures and time
duration, are shown in Figures 2 and 3. For the lead
(Pb)-free solder profile, see http://www.vishay.com/
doc?73257.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in of will yield little improve-
Ramp-Up Rate
+ 6 °C /Second Maximum
2
Temperature at 155 15 °C
Temperature Above 180 °C
Maximum Temperature
Time at Maximum Temperature
Ramp-Down Rate
120 Seconds Maximum
ment in thermal performance.
70 - 180 Seconds
240 + 5/- 0 °C
20 - 40 Seconds
REFLOW SOLDERING
+ 6 °C/Second Maximum
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-
Figure 2. Solder Reflow Temperature Profile
10 s (max)
210 - 220 °C
3 °C/s (max)
4 °C/s (max)
183 °C
140 - 170 °C
50 s (max)
3° C/s (max)
60 s (min)
Reflow Zone
Pre-Heating Zone
Maximum peak temperature at 240 °C is allowed.
Figure 3. Solder Reflow Temperatures and Time Durations
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Document Number 71681
03-Mar-06
AN822
Vishay Siliconix
TABLE 1: EQIVALENT STEADY STATE PERFORMANCE
Package
SO-8
Single
20
TSSOP-8
TSOP-8
PPAK 1212
PPAK SO-8
Single Dual
1.8 5.5
Configuration
Dual
Single
Dual
Single
40
Dual
Single
Dual
40
52
83
90
2.4
5.5
Thermal Resiatance RthJC(C/W)
PowerPAK 1212
49.8 °C
Standard SO-8
Standard TSSOP-8
TSOP-6
85 °C
149 °C
125 °C
2.4 °C/W
20 °C/W
52 °C/W
40 °C/W
PC Board at 45 °C
Figure 4. Temperature of Devices on a PC Board
THERMAL PERFORMANCE
Introduction
Spreading Copper
A basic measure of a device’s thermal performance is Designers add additional copper, spreading copper, to
the junction-to-case thermal resistance, Rθjc, or the the drain pad to aid in conducting heat from a device. It
junction to- foot thermal resistance, Rθjf. This parameter is helpful to have some information about the thermal
is measured for the device mounted to an infinite heat performance for a given area of spreading copper.
sink and is therefore a characterization of the device
only, in other words, independent of the properties of the
object to which the device is mounted. Table 1 shows a
comparison of the PowerPAK 1212-8, PowerPAK SO-8,
standard TSSOP-8 and SO-8 equivalent steady state
performance.
Figure 5 and Figure 6 show the thermal resistance of a
PowerPAK 1212-8 single and dual devices mounted on
a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
nal layers and the backside layer are solid copper. The
internal layers were chosen as solid copper to model the
large power and ground planes common in many appli-
By minimizing the junction-to-foot thermal resistance, the cations. The top layer was cut back to a smaller area and
MOSFET die temperature is very close to the tempera- at each step junction-to-ambient thermal resistance
ture of the PC board. Consider four devices mounted on measurements were taken. The results indicate that an
a PC board with a board temperature of 45 °C (Figure 4)
.
area above 0.2 to 0.3 square inches of spreading copper
gives no additional thermal performance improvement.
A subsequent experiment was run where the copper on
the back-side was reduced, first to 50 % in stripes to
mimic circuit traces, and then totally removed. No signif-
icant effect was observed.
Suppose each device is dissipating 2 W. Using the junc-
tion-to-foot thermal resistance characteristics of the
PowerPAK 1212-8 and the other SMT packages, die
temperatures are determined to be 49.8 °C for the Pow-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on r
whereas a rise
DS(ON)
of over 40 °C will cause an increase in r
as 20 %.
as high
DS(ON)
Document Number 71681
03-Mar-06
www.vishay.com
3
AN822
Vishay Siliconix
130
120
110
100
90
105
Spreading Copper (sq. in.)
Spreading Copper (sq. in.)
95
85
75
65
55
45
80
50 %
100 %
70
100 %
0 %
60
50 %
0 %
50
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 6. Spreading Copper - Junction-to-Ambient Performance
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Figure 5. Spreading Copper - Si7401DN
CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK The PowerPAK 1212-8 combines small size with attrac-
1212-8 uses the same packaging technology and has tive thermal characteristics. By minimizing the thermal
been shown to have the same level of thermal perfor- rise above the board temperature, PowerPAK simplifies
mance while having a footprint that is more than 40 % thermal design considerations, allows the device to run
smaller than the standard TSSOP-8.
cooler, keeps r
low, and permits the device to
DS(ON)
handle more current than a same- or larger-size MOS-
FET die in the standard TSSOP-8 or SO-8 packages.
Recommended PowerPAK 1212-8 land patterns are
provided to aid in PC board layout for designs using this
new package.
www.vishay.com
4
Document Number 71681
03-Mar-06
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single
0.152
(3.860)
0.039
0.068
0.010
(0.255)
(0.990)
(1.725)
0.016
(0.405)
0.026
(0.660)
0.025
0.030
(0.635)
(0.760)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Document Number: 72597
Revision: 21-Jan-08
www.vishay.com
7
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
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Revision: 02-Oct-12
Document Number: 91000
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