SUD25N15-52_06 [VISHAY]

N-Channel 150-V (D-S) 175Celsius MOSFET; N沟道150 -V （D -S ） 175Celsius MOSFET


型号：	SUD25N15-52_06
厂家：	VISHAY
描述：	N-Channel 150-V (D-S) 175Celsius MOSFET N沟道150 -V （D -S ） 175Celsius MOSFET
文件：	总4页 (文件大小：194K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SPICE Device Model SUD25N15-52

Vishay Siliconix

N-Channel 150-V (D-S) 175° MOSFET

CHARACTERISTICS

• N-Channel Vertical DMOS

• Macro Model (Subcircuit Model)

• Level 3 MOS

• Apply for both Linear and Switching Application

• Accurate over the −55 to 125°C Temperature Range

• Model the Gate Charge, Transient, and Diode Reverse Recovery

Characteristics

DESCRIPTION

The attached spice model describes the typical electrical

characteristics of the n-channel vertical DMOS. The subcircuit

model is extracted and optimized over the −55 to 125°C

temperature ranges under the pulsed 0-V to 10-V gate drive. The

saturated output impedance is best fit at the gate bias near the

threshold voltage.

A novel gate-to-drain feedback capacitance network is used to model

the gate charge characteristics while avoiding convergence difficulties

of the switched C_gdmodel. All model parameter values are optimized

to provide a best fit to the measured electrical data and are not

intended as an exact physical interpretation of the device.

SUBCIRCUIT MODEL SCHEMATIC

This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate

data sheet of the same number for guaranteed specification limits.

www.vishay.com

Document Number: 70553

S-60409Rev. B, 20-Mar-06

SPICE Device Model SUD25N15-52

Vishay Siliconix

SPECIFICATIONS (T_J= 25°C UNLESS OTHERWISE NOTED)

Simulated

Data

Measured

Data

Parameter

Symbol

Test Condition

Unit

Static

Gate Threshold Voltage

On-State Drain Current^a

V_GS(th)

I_D(on)

_DS= V_GS, I_D= 250 µA

V_DS= 5 V, V_GS= 10 V

124

V_GS= 10 V, I_D= 5 A

0.040

0.070

0.086

0.047

0.89

0.042

V_GS= 10 V, I_D= 5 A, T_J= 125°C

V_GS= 10 V, I_D= 5 A, T_J= 175°C

V_GS= 6 V, I_D= 5 A

Drain-Source On-State Resistance^a

r_DS(on)

Ω

0.047

0.90

Forward Voltage^a

V_SD

I_S= 15 A, V_GS= 0 V

Dynamic^b

Input Capacitance

C_iss

C_oss

C_rss

Q_g

1695

231

101

1725

216

100

V_GS= 0 V, V_DS= 25 V, f = 1 MHz

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge^c

Gate-Source Charge^c

Gate-Drain Charge^c

Turn-On Delay Time^c

Rise Time^c

V_DS= 75 V, V_GS= 10 V, I_D= 25 A

Q_gs

Q_gd

t_d(on)

t_r

_DD= 50 V, R_L= 3 Ω

Turn-Off Delay Time^c

Fall Time^c

t_d(off)

t_f

_D≅ 25 A, V_GEN= 10 V, R_G= 2.5 Ω

Source-Drain Reverse Recovery Time

t_rr

I_F= 25 A, di/dt = 100 A/µs

Notes

a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.

b. Guaranteed by design, not subject to production testing.

c. Independent of operating temperature.

www.vishay.com

Document Number: 70553

S-60409Rev. B, 20-Mar-06

SPICE Device Model SUD25N15-52

Vishay Siliconix

COMPARISON OF MODEL WITH MEASURED DATA (T_J=25°C UNLESS OTHERWISE NOTED)

www.vishay.com

Document Number: 70553

S-60409Rev. B, 20-Mar-06

Legal Disclaimer Notice

Vishay

Disclaimer

All product specifications and data are subject to change without notice.

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Document Number: 91000

Revision: 18-Jul-08

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