SiC403ACD-T1-GE3 [VISHAY]
6 A microBUCK® SiC403A/B Integrated Buck Regulator with Programmable LDO; 6的microBUCK® SiC403A / B集成降压稳压器，具有可编程LDO
| 型号： | SiC403ACD-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | 6 A microBUCK® SiC403A/B Integrated Buck Regulator with Programmable LDO |
| 文件： | 总24页 (文件大小：1061K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiC403A, SiC403BCD
Vishay Siliconix
6 A microBUCK® SiC403A/B
Integrated Buck Regulator with Programmable LDO
DESCRIPTION
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High efficiency > 93 %
6 A continuous output current capability
Integrated bootstrap switch
The Vishay Siliconix SiC403A/B an advanced stand-alone
synchronous buck regulator featuring integrated power
MOSFETs, bootstrap switch, and a programmable LDO in a
space-saving PowerPAK MLP55-32L pin packages.
Programmable 200 mA LDO with bypass logic
Temperature compensated current limit
All ceramic solution enabled
Pseudo fixed-frequency adaptive on-time control
Programmable input UVLO threshold
Independent enable pin for switcher and LDO
Selectable ultra-sonic power-save mode (SiC403A)
Selectable power-save mode (SiC403B)
Programmable soft-start
1 % internal reference voltage
Power good output
Over-voltage and under-voltage protections
Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
The SiC403A/B is capable of operating with all ceramic
solutions and switching frequencies up to 1 MHz. The
programmable frequency, synchronous operation and
selectable power-save allow operation at high efficiency
across the full range of load current. The internal LDO may
be used to supply 5 V for the gate drive circuits or it may be
bypassed with an external 5 V for optimum efficiency.
Additional features include cycle-by-cycle current limit,
voltage soft-start, under-voltage protection, programmable
over-current protection, soft shutdown and selectable
power-save. The Vishay Siliconix SiC403A/B also provides
an enable input and a power good output.
PRODUCT SUMMARY
Input Voltage Range
Output Voltage Range
Operating Frequency
Continuous Output Current
Peak Efficiency
3 V to 28 V
0.6 V to 5.5 V
200 kHz to 1 MHz
6 A
APPLICATIONS
•
•
•
•
•
•
Notebook, desktop and server computers
Digital HDTV and digital consumer applications
Networking and telecommunication equipment
Printers, DSL, and STB applications
Embedded applications
93 %
Package
PowerPAK MLP55-32L
Point of load power supplies
TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS
EN/PSV (Tri-State)
P
GOOD
LDO_EN
V
OUT
31 30 29 28 27 26 25
32
V
OUT
LX
LX
FB
24
23
22
21
20
19
18
17
1
V
OUT
PAD 1
2
3
4
5
6
7
8
V
P
DD
GND
GND
A
GND
A
P
GND
PAD 3
LX
P
P
P
FBL
GND
GND
V
IN
PAD 2
V
IN
SS
V
IN
GND
GND
BST
P
Typical Application Circuit for SiC403A/B (PowerPAK MLP5x5-32L)
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: powerictechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
1
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM
VIN
A
EN/PSV
29
PGOOD
26
VIN
VDD
VDD
Bootstrap
Switch
8
BST
AGND
SS
D
7
Control & Status
Reference
Soft Start
VDD
12 NC
DL
Hi-side
MOSFET
B
LX
Gate Drive
Control
On- time
Generator
1
FB
13 LXBST
28 LXS
VDD
FB Comparator
DL
Lo-side
MOSFET
31
2
TON
Zero Cross Detector
C
PGND
ILIM
VOUT
Bypass Comparator
Valley Current Limit
VIN
27
VDD
A
B
3
5
VDD
FBL
Y
LDO
14
NC
VLDO Switchover MUX
32
A = connected to pins 6, 9-11, PAD 2
B = connected to pins 23-25, PAD 3
C = connected to pins 15-22
ENL
D = connect to pins 4, 30, PAD 1
SiC403A/B Functional Block Diagram
PIN CONFIGURATION
31 30 29 28 27 26 25
32
LX
1
2
3
4
5
6
7
8
24
23
FB
PAD 1
V
OUT
LX
P
A
V
GND
DD
22
21
GND
PAD 3
A
P
P
GND
GND
GND
FBL
LX
20
19
18
17
PAD 2
V
P
P
P
IN
GND
GND
GND
V
IN
SS
BST
SiC403A/B Pin Configuration (Top View)
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For technical questions, contact: powerictechsupport@vishay.com
This document is subject to change without notice.
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
PIN DESCRIPTION
Pin Number
Symbol
Description
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from VOUT to AGND
Switcher output voltage sense pin - also the input to the internal switch-over between VOUT and
LDO. The voltage at this pin must be less than or equal to the voltage at the VDD pin.
1
FB
.
2
VOUT
V
Bias supply for the IC - when using the internal LDO as a bias power supply, VDD is the LDO output.
When using an external power supply as the bias for the IC, the LDO output should be disabled.
3
VDD
AGND
FBL
4, 30, PAD 1
5
Analog ground
Feedback input for the internal LDO - used to program the LDO output. Connect to an external
resistor divider from VDD to AGND
.
6, 9 to 11, PAD 2
7
VIN
SS
Input supply voltage
The soft start ramp will be programmed by an internal current source charging a capacitor on this pin.
Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply
for the high-side gate drive.
8
BST
12, 14
13
NC
LXBST
LX
No connection
LX Boost - connect to the BST capacitor.
Switching (phase) node
Power ground
23 to 25, PAD3
15 to 22
PGND
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
resistor is required.
26
PGOOD
27
28
ILIM
Current limit sense pin - used to program the current limit by connecting a resistor from ILIM to LXS.
LX sense - connects to RILIM
LXS
Enable/power save input for the switching regulator - connect to AGND to disable the switching
regulator, connect to VDD to operate with power-save mode and float to operate in forced continuous
mode.
29
EN/PSV
31
32
tON
On-time programming input - set the on-time by connecting through a resistor to AGND
Enable input for the LDO - connect ENL to AGND to disable the LDO. Drive with logic signal for logic
ENL
control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND
.
ORDERING INFORMATION
Part Number
Package
Marking (Line 1: P/N)
SiC403ACD-T1-GE3
PowerPAK MLP55-32L
SiC403A
SiC403B
SiC403BCD-T1-GE3
SiC403DB
PowerPAK MLP55-32L
Reference board
Format:
LINE 1: P/N
LINE 2: Siliconix logo + Lot code + ESD symbol
LINE 3: Factory code + Year code + Work week code
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: powerictechsupport@vishay.com
www.vishay.com
3
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS (T = 25 °C, unless otherwise noted)
A
Electrical Parameter
Conditions
Limits
- 0.3 to + 30
- 0.4 max.
Unit
VIN
to PGND
VIN
to VDD
LX
to PGND
- 0.3 to + 30
- 2 to + 30
LX (Transient < 100 ns)
to PGND
VDD
to PGND
- 0.3 to + 6
EN/PSV, PGOOD, ILIM
tON
Reference to PGND
to PGND
- 0.3 to + (VDD + 0.3)
- 0.3 to + (VDD - 1.5)
- 0.3 to + 6
V
to LX
BST
to PGND
- 0.3 to + 35
- 0.3 to VIN
ENL
AGND to PGND
- 0.3 to + 0.3
Temperature
Maximum Junction Temperature
Storage Temperature
Power Dissipation
150
°C
- 65 to 150
(b)
Junction to Ambient Thermal Impedance (RthJA
)
IC Section
50
3.4
1.3
°C/W
W
Ambient Temperature = 25 °C
Ambient Temperature = 100 °C
Maximum Power Dissipation
ESD Protection
HBM
2
kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Input Voltage
VIN
3
28
V
DD to PGND
3
5.5
5.5
V
Output Voltage
VOUT
0.6
Temperature
°C
Ambient Temperature
- 40 to 85
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For technical questions, contact: powerictechsupport@vishay.com
This document is subject to change without notice.
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Test Conditions Unless Specified
V
IN = 12 V, VDD = 5 V, TA = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
TJ = < 125 °C, typical application circuit
Parameter
Symbol
Min. Typ. Max. Unit
Input Power Supplies
Input Supply Voltage
VDD
VIN
3
3
28
VDD
5.5
Sensed at ENL pin, rising
Sensed at ENL pin, falling
2.4
2.23
2.6
2.4
2.95
2.57
VIN UVLO Threshold (a)
VIN UVLO Hysteresis
VUVLO
VUVLO, HYS
VUVLO
V
0.25
Measured at VDD pin, rising
Measured at VDD pin, falling
2.5
2.4
3
VDD UVLO Threshold
2.9
V
V
DD UVLO Hysteresis
IN Supply Current
VUVLO, HYS
0.2
12
ENL, EN/PSV = 0 V , VIN = 28 V
20
IIN
Standby mode; ENL = VDD, EN/PSV = 0 V
ENL, EN/PSV = 0 V
160
190
µA
IDD
300
SiC403A, EN/PSV = VDD, no load
(fSW = 25 kHz), VFB > 0.6 V (b)
0.3
0.7
8
SiC403B, EN/PSV = VDD, no load,
VFB > 0.6 V (b)
VDD Supply Current
mA
V
DD = 5 V, fSW = 250 kHz,
EN/PSV = floating, no load (b)
V
DD = 3 V, fSW = 250 kHz,
5
EN/PSV = floating, no load (b)
Static VIN and load
FB On-Time Threshold
Frequency Range
0.594 0.600 0.606
V
kHz
fSW
Continuous mode operation
Minimum fSW, (SiC403A only)
1000
25
10
Bootstrap Switch Resistance
Timing
Continuous mode operation VIN = 12 V,
On-Time
tON
999
1110 1220
VOUT = 5 V, fSW = 300 kHz, Rton = 133 k
Minimum On-Time (b)
Minimum Off-Time (b)
80
tON, min.
ns
VDD = 5 V
VDD = 3 V
250
370
tOFF, min.
Soft Start
Soft Start Current (b)
Soft Start Voltage (b)
Analog Inputs/Outputs
VOUT Input Resistance
Current Sense
ISS
3
µA
V
VSS
When VOUT reaches regulation
1.5
RO-IN
500
k
Zero-Crossing Detector Threshold Voltage
Power Good
VSense-th
LX-PGND
- 3
+ 3
mV
PG_VTH_UPPER
PG_VTH_LOWER
Upper limit, VFB > internal 600 mV reference
+ 20
Power Good Threshold
%
Lower limit, VFB < internal 600 mV reference
VDD = 5 V, CSS = 10 nF
- 10
12
7
Start-Up Delay Time
(between PWM enable and PGOOD high)
PG_Td
ms
VDD = 3 V, CSS = 10 nF
Fault (noise-immunity) Delay Time (b)
PG_ICC
PG_ILK
5
µs
µA
Leakage Current
1
Power Good On-Resistance
Fault Protection
PG_RDS_ON
10
VDD = 5 V, RILIM = 4750, TJ = 0 °C to +125 °C
VDD = 3.3 V, RILIM = 4750
4.8
6
7.2
Valley Current Limit
ILIM Source Current
ILIM
A
5.1
10
µA
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: powerictechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
5
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
Test Conditions Unless Specified
IN = 12 V, VDD = 5 V, TA = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
TJ = < 125 °C, typical application circuit
V
Parameter
Symbol
Min. Typ. Max. Unit
I
LIM Comparator Offset Voltage
VILM-LK
With respect to AGND
- 10
0
+ 10
mV
%
VFB with respect to Internal 600 mV
reference, 8 consecutive clocks
Output Under-Voltage Fault
VOUV_Fault
- 25
Smart Power-Save Protection
Threshold Voltage (b)
PSave_VTH
VFB with respect to internal 600 mV
+ 10
Over-Voltage Protection Threshold
Over-Voltage Fault Delay (b)
Over Temperature Shutdown (b)
Logic Inputs/Outputs
V
FB with respect to internal 600 mV
10 °C hysteresis
+ 20
5
tOV-Delay
TShut
µs
°C
150
Logic Input High Voltage
VIH
VIL
1
Logic Input Low Volatge
0.4
5
EN/PSV Input for P-Save Operation (b)
VDD = 5 V
2.2
1
V
EN/PSV Input for Forced Continuous
Operation (b)
2
EN/PSV Input for Disabling Switcher
EN/PSV Input Bias Current
ENL Input Bias Current
FBL, FB Input Bias Current
Linear Dropout Regulator
FBL (b)
0
0.4
+ 10
18
IEN
IENL
EN/PSV = VDD or GND
ENL = VIN = 28 V
- 10
11
µA
V
FBL_ILK
FBL, FB = VDD or GND
- 1
+ 1
VLDO ACC
0.75
65
Short-circuit protection,
V
IN = 12 V, VDD < 0.75 V
Start-up and foldback, VIN = 12 V,
0.75 < VDD < 90 % of final VDD value
115
200
LDO Current Limit
LDO_ILIM
mA
Operating current limit, VIN = 12 V,
DD > 90 % of final VDD value
135
V
VLDO to VOUT Switch-over Threshold (d)
VLDO to VOUT Non-switch-over Threshold (d)
VLDO to VOUT Switch-over Resistance
VLDO-BPS
VLDO-NBPS
RLDO
- 130
- 500
+ 130
+ 500
mV
VOUT = 5 V
From VIN to VDD
DD = + 5 V, IVLDO = 100 mA
2
,
LDO Drop Out Voltage (e)
1.2
V
V
Notes:
a. VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
b. Typical value measured on standard evaluation board.
c. SiC403A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout
d. The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage diff erential between the VLDO and VOUT pins which ensures that
V
LDO will not switch-over to VOUT
.
e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.
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For technical questions, contact: powerictechsupport@vishay.com
This document is subject to change without notice.
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
100
2.5
2
1.26
1.24
1.22
1.2
0.14
80
REGULATION
V
IN=20V
0.12
V
IN=6V
Vin=12V
Vin=20V
0.1
V
IN=12V
60
40
20
0
1.5
1
Vin=6V
0.08
0.06
0.04
0.02
0
1.18
1.16
1.14
V
IN=12V
0.5
0
V
IN=20V
Vin=20V
0.01
Vin=12V
VIN=6V
Vin=6V
Vpeak
0.001
0.01
0.1
1
10
0.001
0.1
OUT(A)
1
10
I
I
OUT(A)
Effiency vs. Load-Forced Continuous Mode
= 1.2 V, V = 5 V, EN/PSV is Floating, External Bias, SiC403B
DD
VOUT vs. Load-Forced Continuous Mode
V
OUT
V
= 1.2 V, V = 5 V, EN/PSV is Floating, External Bias, SiC403B
OUT
DD
100
80
60
40
20
0
2.5
1.26
1.24
1.22
1.2
0.12
Vin=12V
Efficiency
Vin=6V
0.1
Vin=20V
2
Vin=12V
Vin=20
0.08
Regula
o
1.5
Vin=6
0.06
0.04
0.02
0
1
1.18
1.16
1.14
Vin=12
Vin=20V
0.5
Vin=20
Vin=6
Vpeak
0.01
Vin=12V
P
LOSS
Vin=6V
0
0.001
0.1
1
10
0.001
0.01
0.1
OUT(A)
1
10
I
IOUT(A)
Effiency vs. Load-PSAVE Mode
VOUT vs. Load-PSAVE Mode
V
= 1.2 V, V = EN/PSV = 5 V, External Bias, SiC403B
V
= 1.2 V, V = EN/PSV = 5 V, External Bias, SiC403B
OUT
DD
OUT DD
100
80
60
40
20
0
2.5
2
1.26
1.24
1.22
1.2
0.12
0.1
V
DD=3.3V
V
DD=5V
V
DD=5V
0.08
0.06
0.04
0.02
0
1.5
1
Regula on
V
DD=3.3V
1.18
1.16
1.14
V
DD=5V
0.5
0
DD
V
PEAK
VDD
=3.3V
DD
0.001
0.01
0.1
1
10
0.001
0.01
0.1
1
10
I
OUT(A)
OUT
Effiency vs. Load-PSAVE Mode
VOUT vs. Load-PSAVE Mode
V
= 1.2 V, V = 12 V, V = EN/PSV = 5 V, External Bias, SiC403B
V
= 1.2 V, V = 12 V, V = EN/PSV = 5 V, External Bias, SiC403B
OUT
IN
DD
OUT IN DD
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: powerictechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
7
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
400
400
350
300
250
200
150
100
50
350
V
IN=12V
300
250
200
150
100
50
V
IN=6V
V
IN=6V
V
IN=20V
V
IN=20V
VIN=12V
0
0
0.01
0.1
1
10
0.001
0.01
0.1
1
10
IOUT(ADC)
IOUT(ADC)
Frequency vs. Load-Forced Continuous Mode
Frequency vs. Load-PSAVE Mode
V
= 1.2 V, V = 5 V, EN/PSV is Floating, External Bias, SiC403B
V
= 1.2 V, V = EN/PSV = 5 V, External Bias, SiC403B
OUT
DD
OUT DD
400
1.575
1.55
0.150
0.125
0.100
350
300
250
200
150
100
50
1.525
1.5
V
OUT
0.075
0.050
0.025
0.000
1.475
1.45
V
peak
1.425
0
6
8.8
11.6
14.4
17.2
20
22.8
25.6
6
8
10
12
14
16
18
20
22
24
26
28
VIN(VDC)
VIN(VDC)
VOUT vs. Line-Forced Continuous Mode
Frequency vs. Line-FCM Mode
V
= 1.5 V, V
= V = ENL = 5 V, EN/PSV is Floating, SiC403B
V
= 1.5 V, V = V = ENL = 5 V, EN/PSV is Floating, SiC403B
OUT
LDO
DD
OUT
LDO DD
1200
1000
800
600
400
200
0
100
80
60
40
20
0
2.5
2
V
IN=20V
V
IN=6V
1.5
1
V
IN=12V
3.3V
5V
V
IN=20V
0.5
0
V
IN=12V
V
IN=6V
0.001
0.01
0.1
1
10
6
8
10
12
14
16
18
20
22
24
26
28
IOUT(ADC)
Input Voltage(V)
On Time vs. Line
Efficiency vs. Load-Forced Continuous Mode
V
= 1.5 V, V
= V = ENL = 5 V, I
= 0 A, SiC403B
V
= 1.2 V, V = 5 V, EN/PSV is Floating, External Bias, SiC403A
OUT
LDO
DD
OUT
OUT DD
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For technical questions, contact: powerictechsupport@vishay.com
This document is subject to change without notice.
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
100
2.5
2
100
80
60
40
20
0
2.5
2
90
V
IN=6V
80
70
60
50
40
30
20
10
0
V
DD3.3V
V
IN=12V
Efficiency
V
IN=20V
1.5
1
1.5
1
V
DD=5V
Efficiency
V
IN=20V
0.5
0
0.5
0
V
IN=12V
V
V
DD=5V
Ploss
0.01
V
DD=3.3V
P
LOSS
IN=6V
0.001
0.1
1
10
0.001
0.01
0.1
1
10
IOUT(ADC)
IOUT(ADC)
Efficiency vs. Load-PSAVE Mode
Efficiency vs. Load-PSAVE Mode
V
= 1.2 V, V = 5 V = EN/PSV, External Bias, SiC403A
V
= 1.2 V, V = 12 V, V = EN/PSV = 5 V, External Bias, SiC403A
OUT
DD
OUT
IN
DD
Vout
Vout
(50mV/div)
(20mV/div)
LX
LX
(5V/div)
(5V/div)
Time(20µs/div)
Time(2µs/div)
Forced Continuous Mode - No Load
Powersave Mode - No Load
V
= 12 V, V
= 1.2 V, I
= 0 A, V = EN/PSV = ENL = 5 V, SiC403A
V
= 12 V, V
= 1.2 V, I
= 0 A, V = EN/PSV = ENL = 5 V
IN
OUT
OUT
DD
IN
OUT
OUT DD
LX
LX
(10V/div)
(10V/div)
Vout
VDD
Vout
(500mV/div)
(500mV/div)
VDD
(5V/div)
(5V/div)
(5V/div)
(5V/div)
Pgood
Pgood
Time(1ms/div)
Time(1ms/div)
Self-Biased Start-Up - Power Good True
Enable Start-Up - Power Good True
V
= 12 V step, V
= 1.2 V, I
= 0 A, V = EN/PSV = ENL = 5 V
V
= 12 V, V
= 1.2 V, I
= 1 A, V = EN/PSV= 5 V
IN
OUT
OUT
DD
IN
OUT
OUT DD
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: powerictechsupport@vishay.com
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SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Vout
(20mV/div)
LX
(5V/div)
Time(10ms/div)
Powersave Mode - No Load
V
= 12 V, V
= 1.2 V, I = 0 A, V = EN/PSV = ENL = 5 V, SiC403B
IN
OUT
OUT DD
Vout
IOUT
Vout
(500mV/div)
(5A/div)
(200mV/div)
LX
LX
(10V/div)
(5V/div)
(10V/div)
(5V/div)
Pgood
Pgood
Time(200µs/div)
Output Over-Current Response
Time(500µs/div)
Output Under-Voltage Response
V
= 12 V, V
= 1.2 V, I
= 0 A, V = ENL = 3.3 V, EN/PSV is floating
V
= 12 V, V
= 1.2 V, V = ENL = 3.3 V, EN/PSV is floating
IN
OUT
OUT
DD
IN
OUT DD
V
OUT
(500mV/div)
Vout
(200mV/div)
(5A/div)
IOUT
I
OUT
(5A/div)
LX
LX
(10V/div)
(5V/div)
(10V/div)
(5V/div)
Pgood
Pgood
Time(50µs/div)
Time(500µs/div)
Short Output Response
Shorted Output Response at Soft-Start Operation
V
= 12 V, V
= 1.2 V, V = ENL = 3.3 V, EN/PSV is floating
V
= 12 V, V
= 1.2 V, V = ENL = 3.3 V, EN/PSV is floating
IN
OUT
DD
IN
OUT DD
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SiC403A, SiC403BCD
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Vout
LX
Vout
(100mV/div)
(10V/div)
(100mV/div)
LX
(10V/div)
Iout
IOUT
(2A/div)
(2A/div)
Time(10µs/div)
Time(10µs/div)
Transient Response in Power Saving Mode
Transient Response in Forced Continuous Mode
V
= 12 V, V
= 1.2 V, I
= 0 A to 6 A, V = EN/PSV = 5 V
V
= 12 V, V
= 1.2 V, I
= 0 A to 6 A, V = EN/PSV = 5 V
IN
OUT
OUT
DD
IN
OUT
OUT DD
OPERATIONAL DESCRIPTION
Device Overview
logic low, the output voltage discharges into the VOUT pin
through an internal FET.
The SiC403A/B is a step down synchronous DC/DC
buck converter with integrated power MOSFETs and a
200 mA capable programmable LDO. The device is capable
of 6 A operation at very high efficiency. A space saving
5 x 5 (mm) 32-pin package is used. The programmable
operating frequency of up to 1 MHz enables optimizing the
configuration for PCB area and efficiency.
The buck controller uses a pseudo-fixed frequency adaptive
on-time control. This control method allows fast transient
igponse which permits the use of smaller output capacitors.
Pseudo-Fixed Frequency Adaptive On-Time Control
The PWM control method used by the SiC403A/B is
pseudo- fixed frequency, adaptive on-time, as shown in
figure 1. The ripple voltage generated at the output capacitor
ESR is used as a PWM ramp signal. This ripple is used to
trigger the on-time of the controller.
t
ON
V
IN
V
LX
Input Voltage Requirements
C
IN
The SiC403A/B requires two input supplies for normal
operation: VIN and VDD. VIN operates over a wide range from
3 V to 28 V. VDD requires a 3 V to 5.5 V supply input that can
be an external source or the internal LDO configured to
supply 3 V to 5.5 V from VIN.
V
Q1
Q2
FB
FB threshold
V
LX
V
OUT
L
ESR
Power Up Sequence
FB
+
When the SiC403A/B uses an external power source at the
VDD pin, the switching regulator initiates the start up when
VIN, VDD, and EN/PSV are above their respective thresholds.
When EN/PSV is at logic high, VDD needs to be applied after
VIN rises. It is also recommended to use a 10 resistor
between an external power source and the VDD pin. To start
up by using the EN/PSV pin when both VDD and VIN are
above their respective thresholds, apply EN/PSV to enable
the start-up process. For SiC403A/B in self-biased mode,
refer to the LDO section for a full description.
C
OUT
Figure 1 - Output Ripple and PWM Control Method
The adaptive on-time is determined by an internal one- shot
timer. When the one-shot is triggered by the output ripple, the
device sends a single on-time pulse to the high- side
MOSFET. The pulse period is determined by VOUT and VIN;
the period is proportional to output voltage and inversely
proportional to input voltage. With this adaptive on-time
arrangement, the device automatically anticipates the
on-time needed to regulate VOUT for the present VIN
condition and at the selected frequency.
Shutdown
The SiC403A/B can be shut-down by pulling either VDD or
EN/PSV below its threshold. When using an external power
source, it is recommended that the VDD voltage ramps down
before the VIN voltage. When VDD is active and EN/PSV at
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
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SiC403A, SiC403BCD
Vishay Siliconix
The advantages of adaptive on-time control are:
• Predictable operating frequency compared to other
variable frequency methods.
(VDD - 1.75) x 10
k =
VIN
• Reduced component count by eliminating the error
amplifier and compensation components.
• Reduced component count by removing the need to sense
and control inductor current.
• Fast transient response - the response time is controlled
by a fast comparator instead of a typically slow error
amplifier.
The maximum RtON value allowed is shown by the following
equation.
(ton - 10 ns) x VIN
Rton
=
25 pF x VOUT
Immediately after the on-time, the DL (drive signal for the low
side FET) output drives high to turn on the low-side
MOSFET. DL has a minimum high time of ~ 320 ns, after
which DL continues to stay high until one of the following
occurs:
• Reduced output capacitance due to fast transient
response.
One-Shot Timer and Operating Frequency
• VFB falls below the reference
The one-shot timer operates as shown in figure 2. The FB
Comparator output goes high when VFB is less than the
internal 600 mV reference. This feeds into the gate drive and
turns on the high-side MOSFET, and also starts the one-shot
timer. The one-shot timer uses an internal comparator and a
capacitor. One comparator input is connected to VOUT, the
other input is connected to the capacitor. When the on-time
begins, the internal capacitor charges from zero volts
through a current which is proportional to VIN. When the
capacitor voltage reaches VOUT, the on-time is completed
and the high-side MOSFET turns off.
• The zero cross detector senses that the voltage on the LX
node is below ground. Power save is activated eight
switching cycles after a zero crossing is detected.
t
ON Limitations and VDD Supply Voltage
For VDD below 4.5 V, the tON accuracy may be limited by the
input voltage.
The original RtON equation is accurate if VIN satisfies the
relationship over the entire VIN range, as follows.
V
IN < (VDD - 1.6 V) x 10
If VIN exceeds (VDD - 1.6 V) x 10, for all or part of the VIN
range, the RtON equation is not accurate. In all cases where
VIN > (VDD - 1.6 V) x 10, the RtON equation must be modified,
as follows.
Gate
drives
FB comparator
FB
VREF
-
+
Q1
LX
DH
V
L
OUT
V
(ton - 10 ns) x (VDD - 1.6 V) x 10
Rton
=
V
OUT
ESR
OUT
FB
25 pF x VOUT
One-shot
timer
Q2
V
IN
+
DL
C
Note that when VIN > (VDD - 1.6 V) x 10 , the actual on-time
is fixed and does not vary with VIN. When operating in this
condition, the switching frequency will vary inversely with VIN
rather than approximating a fixed frequency.
R
ton
On-time = K x R x (V
V )
OUT/ IN
ton
Figure 2 - On-Time Generation
VOUT Voltage Selection
The switcher output voltage is regulated by comparing VOUT
as seen through a resistor divider at the FB pin to the internal
600 mV reference voltage, see figure 3.
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN. Under
steady-state conditions, the switching frequency can be
determined from the on-time by the following equation.
To FB pin
V
OUT
R
1
V
OUT
f
=
SW
t
x V
IN
ON
R
2
The SiC403A/B uses an external resistor to set the on-time
which indirectly sets the frequency. The on-time can be
programmed to provide an operating frequency from
200 kHz to 1 MHz using a resistor between the TON pin and
ground. The resistor value is selected by the following
equation.
Figure 3 - Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
k
R
ton
=
25 pF x f
SW
The constant, k, equals 1, when V is greater than 3.6 V. If
DD
V
is less than 3.6 V and V is greater than (V -1.75) x 10,
DD
IN DD
VRIPPLE
R1
R2
k is shown by the following equation.
VOUT = 0.6 x 1 +
+
2
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S12-1972-Rev. A, 27-Aug-12
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SiC403A, SiC403BCD
Vishay Siliconix
When a large capacitor is placed in parallel with R1 (CTOP
)
Ultrasonic Power-Save Operation (SiC403A)
VOUT is shown by the following equation.
The SiC403A provides ultrasonic power-save operation at
light loads, with the minimum operating frequency fixed at
slightly under 25 kHz. This is accomplished by using an
internal timer that monitors the time between consecutive
high-side gate pulses. If the time exceeds 40 µs, DL drives
high to turn the low-side MOSFET on. This draws current
from VOUT through the inductor, forcing both VOUT and VFB
to fall. When VFB drops to the 600 mV threshold, the next DH
(the drive signal for the high side FET) on-time is triggered.
After the on-time is completed the high-side MOSFET is
turned off and the low-side MOSFET turns on. The low-side
MOSFET remains on until the inductor current ramps down
to zero, at which point the low-side MOSFET is turned off.
Because the on-times are forced to occur at intervals no
greater than 40 µs, the frequency will not fall far below
25 kHz. Figure 5 shows ultrasonic power-save operation.
2
VRIPPLE
R1
R2
1 + (R1ωCTOP
)
VOUT = 0.6 x 1 +
+
x
2
2
R2 x R
R2 + R1
1 ωCTOP
1 +
Enable and Power-Save Inputs
The EN/PSV input is used to enable or disable the switching
regulator. When EN/PSV is low (grounded), the switching
regulator is off and in its lowest power state. When off, the
output of the switching regulator soft-discharges the output
into a 15 internal resistor via the VOUT pin. When EN/PSV
is allowed to float, the pin voltage will float to 33 % of the
voltage at VDD. The switching regulator turns on with
power-save disabled and all switching is in forced continuous
mode.
When EN/PSV is high (above 44 % of the voltage at VDD),
the switching regulator turns on with power-save enabled.
The SiC403A/B P-Save operation reduces the switching
frequency according to the load for increased efficiency at
light load conditions.
minimum f
25 kHz
SW
~
FB ripple
voltage (VFB)
FB threshold
(600 mV)
(0A)
Inductor
current
Forced Continuous Mode Operation
The SiC403A/B operates the switcher in FCM (Forced
Continuous Mode) by floating the EN/PSV pin (see figure 4).
In this mode one of the power MOSFETs is always on, with
no intentional dead time other than to avoid cross-
conduction. This feature results in uniform frequency across
the full load range with the trade-off being poor efficiency at
light loads due to the high-frequency switching of the
MOSFETs. DH is gate signal to drive upper MOSFET. DL is
lower gate signal to drive lower MOSFET
DH on-time is triggered when
reaches the FB threshold
On-time
(t
V
FB
)
ON
DH
DL
40 µs time-out
After the 40 µs time-out, DL drives high if V
FB
has not reached the FB threshold.
FB ripple
voltage (VFB)
Figure 5 - Ultrasonic Power-Save Operation
FB threshold
(600 mV)
Power-Save Operation (SiC403B)
The SiC403B provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors the
inductor current via the voltage across the low-side MOSFET
during the off-time. If the inductor current falls to zero
for 8 consecutive switching cycles, the controller enters
MOSFET on each subsequent cycle provided that the
power-save operation. It will turn off the low-side MOSFET
on each subsequent cycle provided that the current crosses
zero. At this time both MOSFETs remain off until VFB drops
to the 600 mV threshold. Because the MOSFETs are off, the
load is supplied by the output capacitor.
DC load current
Inductor
current
DH on-time is triggered when
On-time
(t
V
reaches the FB threshold
FB
)
ON
DH
DL
If the inductor current does not reach zero on any switching
cycle, the controller immediately exits power-save and
returns to forced continuous mode.
DL drives high when on-time is completed.
DL remains high until V falls to the FB threshold.
FB
Figure 6 shows power-save operation at light loads.
Figure 4 - Forced Continuous Mode Operation
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
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SiC403A, SiC403BCD
Vishay Siliconix
rapid rate. This technique reduces switching losses while
maintaining high efficiency and also avoids the need for
snubbers for the power MOSFETs.
Current Limit Protection
The device features programmable current limiting, which is
accomplished by using the RDS-ON of the lower MOSFET for
current sensing. The current limit is set by RILIM resistor. The
RILIM resistor connects from the ILIM pin to the LXS pin which
is also the drain of the low-side MOSFET. When the low-side
MOSFET is on, an internal ~ 10 µA current flows from the
ILIM pin and through the RILIM resistor, creating a voltage
drop across the resistor. While the low-side MOSFET is on,
the inductor current flows through it and creates a voltage
across the RDS-ON. The voltage across the MOSFET is
negative with respect to ground. If this MOSFET voltage drop
exceeds the voltage across RILIM, the voltage at the ILIM pin
will be negative and current limit will activate. The current
limit then keeps the low-side MOSFET on and will not allow
another high-side on-time, until the current in the low-side
MOSFET reduces enough to bring the ILIM voltage back up
to zero. This method regulates the inductor valley current at
the level shown by ILIM in figure 8.
Figure 6 - Power-Save Mode
Smart Power-Save Protection
Active loads may leak current from a higher voltage into the
switcher output. Under light load conditions with power-save
enabled, this can force VOUT to slowly rise and reach the
over-voltage threshold, resulting in a hard shut-down. Smart
power-save prevents this condition. When the FB voltage
exceeds 10 % above nominal, the device immediately
disables power-save, and DL drives high to turn on the
low-side MOSFET. This draws current from VOUT through
the inductor and causes VOUT to fall. When VFB drops back
to the 600 mV trip point, a normal tON switching cycle begins.
This method prevents a hard OVP shut-down and also
cycles energy from VOUT back to VIN. It also minimizes
operating power by avoiding forced conduction mode
operation. Figure 7 shows typical waveforms for the Smart
Power Save feature.
I
PEAK
I
LOAD
I
LIM
Time
Figure 8 - Valley Current Limit
Setting the valley current limit to 6 A results in a peak
inductor current of 6 A plus peak ripple current. In this
situation, the average (load) current through the inductor is
6 A plus one-half the peak-to-peak ripple current.
The internal 10 µA current source is temperature
compensated at 4100 ppm in order to provide tracking with
V
drifts up to due to leakage
OUT
current flowing into C
OUT
V
discharges via inductor
OUT
Smart power save
and low-side MOSFET
threshold (825 mV)
Normal V ripple
OUT
FB
threshold
the RDS-ON
.
DH and DL off
The RILIM value is calculated by the following equation.
High-side
drive (DH)
RILIM = 792 x ILIM x [0.101 x (5 V - VDD) + 1]
Single DH on-time pulse
after DL turn-off
Low-side
drive (DL)
When selecting a value for RILIM be sure not to exceed the
absolute maximum voltage value for the ILIM pin. Note that
because the low-side MOSFET with low RDS-ON is used for
current sensing, the PCB layout, solder connections, and
PCB connection to the LX node must be done carefully to
obtain good results. RILIM should be connected directly to
LXS (pin 28).
DL turns on when smart
PSAVE threshold is reached
Normal DL pulse after DH
on-time pulse
DL turns off FB
threshold is reached
Figure 7 - Smart Power-Save
SmartDriveTM
Soft-Start of PWM Regulator
For each DH pulse, the DH driver initially turns on the high
side MOSFET at a lower speed, allowing a softer, smooth
turn-off of the low-side diode. Once the diode is off and the
LX voltage has risen 0.5 V above PGND, the SmartDrive
circuit automatically drives the high-side MOSFET on at a
SiC403A/B has a programmable soft-start time that is
controlled by an external capacitor at the SS pin. After the
controller meets both UVLO and EN/PSV thresholds, the
controller has an internal current source of 3 µA flowing
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SiC403A, SiC403BCD
Vishay Siliconix
through the SS pin to charge the capacitor. During the start
up process (figure 9), 50 % of the voltage at the SS pin is
used as the reference for the FB comparator. The PWM
comparator issues an on-time pulse when the voltage at the
FB pin is less than 40 % of the SS pin. As a result, the output
voltage follows the SS voltage. The output voltage reaches
and maintains regulation when the soft start voltage
is 1.5 V. The time between the first LX pulse and VOUT
reaching regulation is the soft-start time (tSS). The
calculation for the soft-start time is shown by the following
equation.
PGOOD will transition low if the VFB pin exceeds + 20 % of
nominal, which is also the over-voltage shutdown threshold.
PGOOD also pulls low if the EN/PSV pin is low when VDD is
present.
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 600 mV + 20 %
(720 mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input is
toggled or VDD is cycled. There is a 5 µs delay built into the
OVP detector to prevent false transitions. PGOOD is also low
after an OVP event.
1.5 V
tSS = CSS
x
3 µA
The voltage at the SS pin continues to ramp up and
eventually equals 64 % of VDD. After the soft start completes,
the FB pin voltage is compared to an internal reference of
0.6 V. The delay time between the VOUT regulation point and
PGOOD going high is shown by the following equation.
Output Under-Voltage Protection
When VFB falls 25 % below its nominal voltage (falls to
450 mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tristate
the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
C
SS x (0.64 x VDD - 1.5 V)
3 µA
tPGOOD-DELAY
=
VDD UVLO, and POR
UVLO (Under-Voltage Lock-Out) circuitry inhibits switching
and tri-states the DH/DL drivers until VDD rises above 3 V. An
internal POR (Power-On Reset) occurs when VDD exceeds
3 V, which resets the fault latch and a soft-start counter cycle
begins which prepares for soft-start. The SiC403A/B then
begins a soft-start cycle. The PWM will shut off if VDD falls
below 2.4 V.
LDO Regulator
SiC403A/B has an option to bias the switcher by using an
internal LDO from VIN. The LDO output is connected to VDD
internally. The output of the LDO is programmable by using
external resistors from the VDD pin to AGND (see figure 10).
The feedback pin (FBL) for the LDO is regulated to 750 mV.
Figure 9 - Soft-start Timing Diagram
Pre-Bias Start-Up
The SiC403A/B can start up normally even when there is an
existing output voltage present. The soft start time is still the
same as normal start up (when the output voltage starts from
zero). The output voltage starts to ramp up when 40 % of the
voltage at SS pin meets the existing FB voltage level.
Pre-bias startup is achieved by turning off the lower gate
when the inductor current falls below zero. This method
prevents the output voltage from discharging.
Figure 10 - LDO Output Voltage Selection
The LDO output voltage is set by the following equation.
RLDO1
VLDO = 750 mV x 1 +
RLDO2
Power Good Output
A minimum capacitance of 1 µF referenced to AGND is
normally required at the output of the LDO for stability.
Note that if the LDO voltage is set lower than 4.5 V, the
minimum output capacitance for the LDO is 10 µF.
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the FB
pin is 10 % below the nominal voltage, PGOOD is pulled low.
It is held low until the output voltage returns above - 8 % of
nominal.
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
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SiC403A, SiC403BCD
Vishay Siliconix
LDO ENL Functions
Due to the initial current limitations on the LDO during power
up (figure 11), any external load attached to the VDD pin must
be limited to less than the start up current before the LDO
has reached 90 % of its final regulation value.
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is off. When ENL is above
the VIN UVLO threshold, the LDO is enabled and the
switcher is also enabled if the EN/PSV and VDD are above
their threshold. The table below summarizes the function of
ENL and EN/PSV pins.
EN/PSV
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
ENL
LDO
Off
Off
On
On
On
On
Switcher
Off
Low, < 0.4 V
Low, < 0.4 V
On
1 V < High < 2.6 V
1 V < High < 2.6 V
High, > 2.6 V
High, > 2.6 V
Off
Figure 11 - LDO Start-Up
Off
LDO Switch-Over Poeration
Off
The SiC403A/B includes a switch-over function for the LDO.
The switch-over function is designed to increase efficiency
by using the more efficient DC/DC converter to power the
LDO output, avoiding the less efficient LDO regulator when
possible. The switch-over function connects the VDD pin
directly to the VOUT pin using an internal switch. When the
switch-over is complete the LDO is turned off, which results
in a power savings and maximizes efficiency. If the LDO
output is used to bias the SiC403A/B, then after switch-over
the device is self-powered from the switching regulator with
the LDO turned off.
On
The ENL pin also acts as the switcher under-voltage lockout
for the VIN supply. When SiC403A/B is self-biased from the
LDO and runs from the VIN power source only, the VIN UVLO
feature can be used to prevent false UV faults for the PWM
output by programming with a resistor divider at the VIN, ENL
and AGND pins. When SiC403A/B has an external bias
voltage at VDD and the ENL pin is used to program the VIN
UVLO feature, the voltage at FBL needs to be higher than
750 mV to force the LDO off.
The switch-over starts 32 switching cycles after PGOOD
output goes high. The voltages at the VDD and VOUT pins are
then compared; if the two voltages are within 300 mV of
each other, the VDD pin connects to the VOUT pin using an
internal switch, and the LDO is turned off. To avoid unwanted
switch-over, the minimum difference between the voltages
for VOUT and VDD should be 500 mV.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM output
turning off. If ENL goes below the VIN UVLO threshold and
stays above 1 V, then the switcher will turn off but the LDO
will remain on.
It is not recommended to use the switch-over feature for an
output voltage less than VDD UVLO threshold since the
SiC403A/B is not operational below that threshold.
LDO Start-up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
1. ENL pin
Switch-Over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that are
inherent to its construction, as shown in figure 12. If the
voltage at the VOUT pin is higher than VDD, then the
respective diode will turn on and the current will flow through
this diode. This has the potential of damaging the device.
Therefore, VOUT must be less than VDD to prevent damaging
the device.
2. VLDO output
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when the
VDD voltage (which is the LDO output voltage) is less than
0.75 V, the LDO initiates a current-limited start-up (typically
65 mA) to charge the output capacitors while protecting from
a short circuit event. When VDD is greater than 0.75 V but still
less than 90 % of its final value (as sensed at the FBL pin),
the LDO current limit is increased to ~115 mA. When VDD
has reached 90 % of the final value (as sensed at the FBL
pin), the LDO current limit is increased to ~ 200 mA and the
LDO output is quickly driven to the nominal value by the
internal LDO regulator. It is recommended that during LDO
start-up to hold the PWM switching off until the LDO has
reached 90 % of the final value. This prevents overloading
the current-limited LDO output during the LDO start-up.
Switchover
control
Switchover
MOSFET
V
OUT
LDO
Parastic diode
VDD
Figure 12 - Switch-over MOSFET Parasitic Diodes
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Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC403A, SiC403BCD
Vishay Siliconix
Design Procedure
larger inductance translates directly into larger packages and
higher cost. Cost, size, output ripple, and efficiency are all
used in the selection process.
The ripple current will also set the boundary for PSave
operation. The switching will typically enter PSave mode
when the load current decreases to 1/2 of the ripple current.
For example, if ripple current is 4 A then PSave operation will
typically start for loads less than 2 A. If ripple current is set at
40 % of maximum load current, then PSave will start for loads
less than 20 % of maximum current.
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor ripple
current must be specified.
The maximum input voltage (VIN max.) is the highest specified
input voltage. The minimum input voltage (VIN min.) is
determined by the lowest input voltage after evaluating the
voltage drops due to connectors, fuses, switches, and PCB
traces.
The following parameters define the design:
• Nominal output voltage (VOUT
• Static or DC output tolerance
• Transient response
)
The inductor value is typically selected to provide a ripple
current that is between 25 % to 50 % of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
• Maximum load current (IOUT
)
During the on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
There are two values of load current to evaluate - continuous
load current and peak load current. Continuous load current
relates to thermal stresses which drive the selection of
the inductor and input capacitors. Peak load current
determines instantaneous component stresses and filtering
requirements such as inductor saturation, output capacitors,
and design of the current limit circuit.
The following values are used in this design:
• VIN = 12 V 10 %
• VOUT = 1.5 V 4 %
(V - V
) x t
ON
IN
OUT
L =
I
RIPPLE
Example
In this example, the inductor ripple current is set equal to
50 % of the maximum load current. Thus ripple current will be
50 % x 6 A or 3 A. To find the minimum inductance needed,
use the VIN and tON values that correspond to VINmax.
• fSW = 300 kHz
• Load = 6 A max.
(13.2 - 1.5) x 379 ns
L =
= 1.48 µH
3 A
A slightly larger value of 1.5 µH is selected. This will
decrease the maximum IRIPPLE to 2.7 A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency.
The desired switching frequency is 300 kHz which results
from using component selected for optimum size and cost.
A resistor (RtON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
25 pF x R
x V
OUT
tON
tON_VINmin.
=
+ 10 ns = 461 ns
V
INmin.
(V - V
) x t
ON
IN
OUT
(ton - 10 ns) x VIN
IRIPPLE
=
Rton
=
L
25 pF x VOUT
(10.8 V - 1.5 V) x 461 ns
1.5 µH x (1 + 0.2)
IRIPPLE_min
=
= 2.38 A
.
To select RtON, use the maximum value for VIN, and for tON
use the value associated with maximum VIN.
(10.8 V - 1.5 V) x 379 ns
1.5 µH x (1 - 0.2)
IRIPPLE_max
=
= 3.7 A
.
V
OUT
t
=
ON
V
x f
SW
INmax.
Capacitor Selection
The output capacitors are chosen based upon required
ESR and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple.
A change in the output ripple voltage will lead to a change in
DC voltage at the output.
The design goal for output voltage ripple is 4 % of 1.5 V or
60 mV. The maximum ESR value allowed is shown by the
following equations.
Substituting for RtON results in the following solution.
tON = 129.9 k, use RtON = 130 k.
R
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values result in smaller size but
create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current/voltage
and for a given DC resistance are more efficient. However,
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
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SiC403A, SiC403BCD
Vishay Siliconix
7.9
1.5
2 (1.6 - 1.5)
6
2
V
60 mV
RIPPLE
1.5 µH x
-
x 1 µs
ESR
=
=
max.
C
C
= 7.9 x
I
3.7 A
OUT
RIPPLEmax.
ESR
= 16.2 mΩ
max.
= 194 µF
OUT
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current is
at the peak, determines the required capacitance. If the load
release is instantaneous (load changes from maximum to
zero in < 1 µs), the output capacitor must absorb all the
inductor's stored energy. This will cause a peak voltage on
the capacitor according to the following equation.
Note that COUT is much smaller in this example, 194 µF
compared to 298 µF based on a worst case load release. To
meet the two design criteria of minimum 298 µF and
maximum 16 m ESR, select one capacitor of 330 µF and
9 m ESR.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
1
2
2
)
L (I
+
x I
OUT
RIPPLEmax.
C
=
Double-pulsing occurs due to switching noise seen at the FB
input or because the FB ripple voltage is too low. This causes
the FB comparator to trigger prematurely after the 250 ns
minimum off-time has expired. In extreme cases the noise
can cause three or more successive on-times. Double-
pulsing will result in higher ripple voltage at the output, but in
most applications it will not affect operation. This form of
instability can usually be avoided by providing the FB pin with
a smooth, clean ripple signal that is at least 10 mVp-p, which
may dictate the need to increase the ESR of the output
capacitors. It is also imperative to provide a proper PCB
layout as discussed in the Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
shown in figure 13. This capacitor should be left unpopulated
until it can be confirmed that double-pulsing exists. Adding
the CTOP capacitor will couple more ripple into FB to help
eliminate the problem. An optional connection on the PCB
should be available for this capacitor.
OUT_min.
2
2
(V
) - (V
)
OUT
PEAK
Assuming a peak voltage VPEAK of 1.6 V (150 mV rise upon
load release), and a 6 A load release, the required
capacitance is shown by the next equation.
1
1.5 µH x (6 + x 3.7)2
2
C
C
=
OUT_min.
(1.6)2 - (1.5)2
= 298 µF
OUT_min.
During the load release time, the voltage cross the inductor
is approximately - VOUT. This causes a down-slope or falling
di/dt in the inductor. If the load dI/dt is not much faster than
the dI/dt of the inductor, then the inductor current will tend to
track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor; therefore a smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dILOAD/dt.
C
TOP
Peak inductor current is shown by the next equation.
ILPK = Imax. + 1/2 x IRIPPLEmax.
ILPK = 6 + 1/2 x 3.7 = 7.9 A
R
1
To FB pin
V
OUT
dILOAD
dt
R
2
Rate of change of load current =
= maximum load release = 6 A
I
max.
Figure 13 - Capacitor Coupling to FB Pin
I
V
I
max.
LPK
L x
-
x dt
dl
LOAD
OUT
C
= I
x
OUT
LPK
2 (V - V
)
OUT
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking
stability is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and ringing.
Ringing for more than one cycle after the initial step is an
indication that the ESR should be increased.
PK
Example
dl
LOAD
2 A
=
dt
1 µs
This would cause the output current to move from 6 A to
0 A in 3 µs, giving the minimum output capacitance
requirement shown in the following equation.
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SiC403A, SiC403BCD
Vishay Siliconix
ESR Requirements
Figure 15 shows the magnitude of the ripple contribution due
to CL at the FB pin.
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10 mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other
is the ripple due to capacitive charging and discharging
during the switching cycle. For most applications the
minimum ESR ripple voltage is dominated by the output
capacitors, typically SP or POSCAP devices. For stability the
ESR zero of the output capacitor should be lower than
approximately one-third the switching frequency. The
formula for minimum ESR is shown by the following
equation.
Figure 15 - FB Voltage by CL Voltage
It is shown by the following equation.
(R1//R2) x S x CC
3
ESR
=
min.
VFBCL = VCL
x
2 x π x C
x f
SW
OUT
(R1//R2) x S x CC + 1
Using Ceramic Output Capacitors
Figure 16 shows the magnitude of the ripple contribution due
to the output voltage ripple at the FB pin.
When the system is using high ESR value capacitors, the
feedback voltage ripple lags the phase node voltage by 90°.
Therefore, the converter is easily stabilized. When the
system is using ceramic output capacitors, the ESR value is
normally too small to meet the above ESR criteria. As a
result, the feedback voltage ripple is 180° from the phase
node and behaves in an unstable manner. In this application
it is necessary to add a small virtual ESR network that is
composed of two capacitors and one resistor, as shown in
figure 14.
Figure 16 - FB Voltage by Output Voltage
It is shown by the following equation.
R2
VFBΔVOUT = ΔVOUT
x
1
R1//
+ R2
S x CC
The purpose of this network is to couple the inductor current
ripple information into the feedback voltage such that the
feedback voltage has 90° phase lag to the switching node
similar to the case of using standard high ESR capacitors.
This is illustrated in figure 17.
Figure 14 - Virtual ESR Ramp Current
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across CL and output ripple voltage.
They are defined in the following equations.
IL x DCR (s x L/DCR + 1)
VCL
=
S x RL x CL + 1
ΔIL
8C x fSW
ΔVOUT
=
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
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SiC403A, SiC403BCD
Vishay Siliconix
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line and
load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static conditions
it trips when the feedback pin is 600 mV, 1 %.
The on-time pulse from the SiC403A/B in the design
example is calculated to give a pseudo-fixed frequency of
300 kHz. Some frequency variation with line and load is
expected. This variation changes the output ripple voltage.
Because adaptive on-time converters regulate to the valley
of the output ripple, ½ of the output ripple appears as a DC
regulation error. For example, if the output ripple is 50 mV
with VIN = 6 V, then the measured DC output will be 25 mV
above the comparator trip point.
If the ripple increases to 80 mV with VIN = 28 V, then the
measured DC output will be 40 mV above the comparator
trip. The best way to minimize this effect is to minimize the
output ripple.
The use of 1 % feedback resistors may result in up to 1 %
error. If tighter DC accuracy is required, 0.1 % resistors
should be used.
The output inductor value may change with current. This will
change the output ripple and therefore will have a minor
effect on the DC output voltage. The output ESR also affects
the output ripple and thus has a minor effect on the DC
output voltage.
Figure 17 - FB Voltage in Phasor Diagram
The magnitude of the feedback ripple voltage, which is
dominated by the contribution from CL, is controlled by the
value of R1, R2 and CC. If the corner frequency of (R1//R2) x
CC is too high, the ripple magnitude at the FB pin will be
smaller, which can lead to double-pulsing. Conversely, if the
corner frequency of (R1//R2) x CC is too low, the ripple
magnitude at FB pin will be higher. Since the SiC403A/B
regulates to the valley of the ripple voltage at the FB pin, a
high ripple magnitude is undesirable as it significantly
impacts the output voltage regulation. As a result, it is
desirable to select a corner frequency for (R1//R2) x CC to
achieve enough, but not excessive, ripple magnitude and
phase margin. The component values for R1, R2, and CC
should be calculated using the following procedure.
Select CL (typical 10 nF) and RL to match with L and DCR
time constant using the following equation.
Switching Frequency Variation
L
RL =
The switching frequency varies with load current as a result
of the power losses in the MOSFETs and DCR of the
inductor. For a conventional PWM constant-frequency
converter, as load increases the duty cycle also increases
slightly to compensate for IR and switching losses in the
MOSFETs and inductor. An adaptive on-time converter must
also compensate for the same losses by increasing the
effective duty cycle (more time is spent drawing energy from
VIN as losses increase). The on-time is essentially constant
for a given VOUT/VIN combination, to offset the losses the off-
time will tend to reduce slightly as load increases. The net
effect is that switching frequency increases slightly with
increasing load.
DCR x CL
Select CC by using the following equation.
1
3
CC
≈
x
R1//R2 2 x π x fSW
The resistor values (R1 and R2) in the voltage divider circuit
set the VOUT for the switcher. The typical value for CC is from
10 pF to 1 nF.
Dropout Performance
The output voltage adjustment range for continuous
conduction operation is limited by the fixed 250 ns (typical)
minimum off-time of the one-shot. When working with low
input voltages, the duty-factor limit must be calculated using
worst-case values for on and off times.
The duty-factor limitation is shown by the next equation.
t
ON(min.)
DUTY =
t
x t
OFF(max.)
ON(min.)
The inductor resistance and MOSFET on-state voltage drops
must be included when performing worst-case dropout
duty-factor calculations.
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Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
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SiC403A, SiC403BCD
Vishay Siliconix
SIC403 EVALUATION REF BOARD (External 5 V bias)
1
1
1
t
b s l x
T O N
B S T
V O U T
N C
N C
A G N D
3 5
B S T 8
V o
A G N D
3 0
A G N D
2
4
P G N D
2 2
P G N D
1 2
1 4
2 1
P G N D
2 0
P G N D
1 9
P G N D
1 8
P G N D
E N / P S V
E N L
_ P S E V N 2 9
3 2
1 7
P G N D
1 6
P G N D
1
1 5
1
1
Evaluation Board Schematic
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: powerictechsupport@vishay.com
This document is subject to change without notice.
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SiC403A, SiC403BCD
Vishay Siliconix
BILL OF MATERIALS
Qty. Ref. Designator PCB Footprint Value Voltage
Description
CAP, 0.1 µF, 50 V, 0603
68 µF TAN, 20 V, 593D, 20 %
CAP, Radial, 150 µF, 35 V
CAP, 0.01 µF, 50 V, 0402
1 µF, 50 V.X7R.B, 0603
330 µF, 6.3 V, D
Part Number
Generic Component
593D686X0020D2TE3
EU-FM1V151
Manufacturer
2
3
1
1
1
2
2
2
1
1
1
1
4
C11, C14
C10, C20, C22
C12
SM0603
593D
0.1 µF
68 µF
150 µF
0.01 µF
1 µF
50 V
20 V
35 V
50 V
50 V
6.3 V
50 V
10 V
10 V
35 V
25 V
0
Radial
C13
SM0402
SM0603
SM593D
SM0402
SM0805
SM0402
SM1210
SM0603
IHLP4040
0
Generic Component
Generic Component
593D337X06R3E2
Generic Component
Generic Component
Generic Component
Generic Component
Generic Component
IHLP4040DZER1R5M01
8834
C6
C16, C18
C25, C30
C26, C27
C28
330 µF
68 pF
1 µF
CAP, 68 pF, 50 V, 0402
1 µF, 10 V, 0805
0.1 µF
10 µF
3.3 nF
1.5 µH
0
CAP, 0.1 µF, 10 V, 0402
CAP, 10 µF, 35 V, 1210
CAP, CER, 22 nF, 25 V
1.5 µH
C15
C29
L1
M1, M2, M3, M4
0
Nylonon Standoff
P1, P2, P6, P7, P8,
P9, P10, P11
8
Terminal
0
0
Test Points
1573-3
1
1
1
1
1
1
1
1
1
R7
SM0603
SM0603
SM0603
SM0402
SM0603
SM0603
SM0603
SM0402
SM0603
0
4.64K
5.11K
100
10K
50 V
50 V
50 V
50 V
50 V
50 V
50 V
50 V
50 V
Res, 0
Generic Component
Generic Component
Generic Component
Generic Component
Generic Component
Generic Component
Generic Component
Generic Component
Generic Component
R8
Res, 4.64K, 0603
Res, 5.11K, 0603
100 R, 50 V, 0402
Res, 10K, 50 V, 0603
Res, 5.11K, 0603
Res, 130K, 0603
0 R, 50 V, 0402
R10
R13
R15
R23
R30
R39
R52
5.11K
130K
0
0
RES, 31.6K, 50 V, 0603
6 A micro BUCK integrated Buck
Regulator with Programmable
LDO
PowerPAK
MLP55-32L
SiC403ACD-T1-GE3/
SiC403BCD-T1GE3
1
4
U1
0
0
0
0
B1, B2, B3, B4
0
BANANA JACK
575-4
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Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
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SiC403A, SiC403BCD
Vishay Siliconix
PACKAGE DIMENSIONS
Top View
Side View
Bottom View
Millimeters
Dim.
Inches
Millimeters
Inches
Nom.
0.137
0.041
0.041
0.077
0.014
0.137
0.065
0.058
0.018
Note
Dim.
Min. Nom. Max.
Min. Nom. Max.
Min.
3.43
1.00
1.00
1.92
Nom.
3.48
1.05
1.05
1.97
0.36
3.48
1.66
1.48
0.45
Max.
3.53
1.10
1.10
2.02
Min.
0.135
0.039
0.039
0.075
Max.
0.139
0.043
0.043
0.079
A
A1
A2
b
0.70
0.00
0.75
-
0.80
0.05
0.027 0.029 0.031
D2-1
D2-2
D2-3
D2-4
D2-5
E2-1
E2-2
E2-3
E2-4
0.00
-
0.002
8
4
0.20 ref.
0.25
0.008 ref.
0.20
0.35
0.30
0.45
0.078 0.098 0.110
D
5.00 BSC
0.50 BSC
5.00 BSC
0.40
0.196 BSC
e
0.019 BSC
3.43
1.61
1.43
3.53
1.71
1.53
0.135
0.063
0.056
0.139
0.067
0.060
E
0.196 BSC
L
0.013 0.015 0.017
N
32
32
8
3
3
3
Nd
Ne
8
8
8
Note:
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y1 4.5M - 1994.
3. N is the number of terminals
Nd is the number of terminals in X-direction and
Ne is the number of terminals in Y-direction.
4. Dimensions applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62768.
Document Number: 62768
S12-1972-Rev. A, 27-Aug-12
For technical questions, contact: powerictechsupport@vishay.com
This document is subject to change without notice.
www.vishay.com
23
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
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Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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Material Category Policy
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
conform to JEDEC JS709A standards.
Revision: 02-Oct-12
Document Number: 91000
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