SiC789CD-T1-GE3 [VISHAY]
Thermal monitor flag;
| 型号： | SiC789CD-T1-GE3 |
| 厂家： | 
VISHAY |
| 描述： | Thermal monitor flag |
| 文件： | 总19页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiC789, SiC789A
www.vishay.com
Vishay Siliconix
60 A VRPower® Integrated Power Stage
DESCRIPTION
FEATURES
• Thermally enhanced PowerPAK® MLP66-40L
package
The SiC789 and SiC789A are integrated power stage
solutions optimized for synchronous buck applications to
offer high current, high efficiency, and high power
density performance. Packaged in Vishay’s proprietary
6 mm x 6 mm MLP package, SiC789 and SiC789A enable
voltage regulator designs to deliver up to 60 A continuous
current per phase.
• Vishay’s Gen IV MOSFET technology and a
low-side MOSFET with integrated Schottky
diode
• Delivers up to 60 A continuous current
• 95 % peak efficiency
The
internal
power
MOSFETs
utilize
Vishay’s
• High frequency operation up to 1.5 MHz
• Power MOSFETs optimized for 12 V input stage
state-of-the-art Gen IV TrenchFET technology that delivers
industry benchmark performance to significantly reduce
switching and conduction losses.
• 3.3 V (SiC789A) / 5 V (SiC789) PWM logic with tri-state and
hold-off
The SiC789 and SiC789A incorporate an advanced
MOSFET gate driver IC that features high current driving
capability, adaptive dead-time control, an integrated
bootstrap Schottky diode, a thermal warning (THWn) that
alerts the system of excessive junction temperature, and
skip mode (SMOD#) to improve light load efficiency. The
drivers are also compatible with a wide range of PWM
controllers and supports tri-state PWM, 3.3 V (SiC789A) /
5 V (SiC789) PWM logic.
• SMOD# logic for light load efficiency improvement
• Low PWM propagation delay (< 20 ns)
• Thermal monitor flag
• Faster enable / disable
• Under voltage lockout for VCIN
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Multi-phase VRDs for CPU, GPU, and memory
TYPICAL APPLICATION DIAGRAM
5 V
V
IN
BOOT
PHASE
VCIN
SMOD#
VSWH
DSBL#
VOUT
Gate
driver
PWM
controller
PWM
THWn
Fig. 1 - SiC789 and SiC789A Typical Application Diagram
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
1
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC789, SiC789A
www.vishay.com
Vishay Siliconix
PINOUT CONFIGURATION
VSWH30
30 VSWH
1 SMOD#
SMOD# 1
2 VCIN
VCIN 2
VSWH29
PGND28
PGND27
PGND26
PGND25
PGND24
PGND23
29 VSWH
28 PGND
27 PGND
26 PGND
25 PGND
24 PGND
23 PGND
41
CGND
41
CGND
3 VDRV
VDRV 3
4 BOOT
BOOT4
5 CGND
6 GH
CGND5
GH 6
43
VSWH
43
VSWH
7 PHASE
PHASE 7
42
VIN
42
VIN
8 VIN
9 VIN
10 VIN
VIN 8
VIN 9
PGND22
PGND21
22 PGND
21 PGND
VIN 10
Top view
Bottom view
Fig. 2 - SiC789 and SiC789A Pin Configuration
PIN DESCRIPTION
PIN NUMBER
NAME
FUNCTION
1
SMOD#
VCIN
Low-side gate turn-off logic. Active low
Supply voltage for internal logic circuitry
Supply voltage for internal gate driver
High-side driver bootstrap voltage
Analog ground for the driver IC
2
3
VDRV
4
BOOT
CGND
GH
5, 37, 41
6
High-side gate signal
7
PHASE
VIN
Return path of high-side gate driver
8 to 14, 42
Power stage input voltage. Drain of high-side MOSFET
Switch node of the power stage
Power ground
15, 29 to 35, 43
VSWH
PGND
GL
16 to 28
36
Low-side gate signal
38
THWn
DSBL#
PWM
Thermal warning open drain output
Disable pin. Active low
39
40
PWM control input
ORDERING INFORMATION
PART NUMBER
PACKAGE
MARKING CODE
SiC789A
OPTION
SiC789ACD-T1-GE3
SiC789CD-T1-GE3
SiC789ADB and SiC789DB
3.3 V PWM optimized
5 V PWM optimized
PowerPAK® MLP66-40L
SiC789
Reference board
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
2
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC789, SiC789A
www.vishay.com
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
Input Voltage
CONDITIONS
LIMIT
UNIT
VIN
-0.3 to +25
-0.3 to +7
-0.3 to +7
-0.3 to +25
-8 to +30
32
Control Logic Supply Voltage
Drive Supply Voltage
VCIN
VDRV
Switch Node (DC voltage)
Switch Node (AC voltage) (1)
BOOT Voltage (DC voltage)
BOOT Voltage (AC voltage) (2)
BOOT to PHASE (DC voltage)
BOOT to PHASE (AC voltage) (3)
VSWH
V
VBOOT
38
-0.3 to +7
-0.3 to +8
VBOOT- PHASE
All Logic Inputs and Outputs
(PWM, DSBL#, and THWn)
-0.3 to VCIN + 0.3
fS = 300 kHz, VIN = 12 V, VOUT = 1.8 V
60
50
(4)
Output Current, IOUT(AV)
A
°C
V
fS = 1 MHz, VIN = 12 V, VOUT = 1.8 V
Max. Operating Junction Temperature
Ambient Temperature
TJ
150
TA
-40 to +125
-65 to +150
5000
Storage Temperature
Tstg
Human body model, JESD22-A114
Charged device model, JESD22-C101
Electrostatic Discharge Protection
1000
Note
(1)
(2)
(3)
(4)
The specification values indicated “AC” is VSWH to PGND, -8 V (< 20 ns, 10 μJ), min. and 30 V (< 50 ns), max.
The specification value indicates “AC voltage” is VBOOT to PGND, 36 V (< 50 ns) max.
The specification value indicates “AC voltage” is VBOOT to VPHASE, 8 V (< 20 ns) max.
Output current rated with testing evaluation board at TA = 25 °C with natural convection cooling. The rating is limited by the peak evaluation
board temperature, TJ = 150 °C, and varies depending on the operating conditions and PCB layout. This rating may be changed with different
application settings.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
MINIMUM
TYPICAL
MAXIMUM
UNIT
Input Voltage (VIN)
4.5
4.5
4.5
4
-
5
18
5.5
5.5
5.5
-
Drive Supply Voltage (VDRV
)
V
Control Logic Supply Voltage (VCIN
)
5
BOOT to PHASE (VBOOT-PHASE, DC voltage)
Thermal Resistance from Junction to PAD
Thermal Resistance from Junction to Case
4.5
1
-
°C/W
-
2.5
-
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
3
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC789, SiC789A
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
(DSBL# = SMOD# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
LIMITS
UNIT
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
POWER SUPPLY
VDSBL# = 0 V, no switching, VPWM = FLOAT
-
-
-
-
-
-
-
85
290
295
16
-
-
Control Logic Supply Current
Drive Supply Current
IVCIN
VDSBL# = 5 V, no switching, VPWM = FLOAT
μA
V
DSBL# = 5 V, fS = 300 kHz, D = 0.1
fS = 300 kHz, D = 0.1
-
25
-
mA
μA
fS = 1 MHz, D = 0.1
50
IVDRV
VDSBL# = 0 V, no switching
35
-
VDSBL# = 5 V, no switching
60
-
BOOTSTRAP SUPPLY
Bootstrap Diode Forward Voltage
PWM CONTROL INPUT (SiC789)
Rising Threshold
VF
IF = 2 mA
0.4
V
V
VTH_PWM_R
VTH_PWM_F
VTRI
3.4
0.72
-
3.7
0.9
4.0
1.1
-
Falling Threshold
Tri-state Voltage
VPWM = FLOAT
2.3
Tri-state Rising Threshold
Tri-state Falling Threshold
VTRI_TH_R
VTRI_TH_F
0.9
3.1
1.15
3.35
1.38
3.6
Tri-state Rising Threshold
Hysteresis
VHYS_TRI_R
VHYS_TRI_F
-
-
225
325
-
-
mV
μA
Tri-state Falling Threshold
Hysteresis
VPWM = 5 V
VPWM = 0 V
-
-
-
-
350
PWM Input Current
IPWM
-350
PWM CONTROL INPUT (SiC789A)
Rising Threshold
VTH_PWM_R
VTH_PWM_F
VTRI
2.2
0.72
-
2.45
0.9
2.7
1.1
-
Falling Threshold
Tri-state Voltage
VPWM = FLOAT
1.8
V
Tri-state Rising Threshold
Tri-state Falling Threshold
VTRI_TH_R
VTRI_TH_F
0.9
1.95
1.15
2.2
1.38
2.45
Tri-state Rising Threshold
Hysteresis
VHYS_TRI_R
VHYS_TRI_F
-
-
225
275
-
-
mV
μA
Tri-state Falling Threshold
Hysteresis
VPWM = 3.3 V
VPWM = 0 V
-
-
-
-
225
PWM Input Current
IPWM
-225
TIMING SPECIFICATIONS
Tri-State to GH/GL Rising
Propagation Delay
tPD_TRI_R
-
30
-
Tri-state Hold-Off Time
tTSHO
-
-
130
18
-
-
GH - Turn Off Propagation Delay
tPD_OFF_GH
No load, see fig. 4
GH - Turn On Propagation Delay
(Dead time rising)
tPD_ON_GH
tPD_OFF_GL
tPD_ON_GL
-
-
-
10
12
10
-
-
-
GL - Turn Off Propagation Delay
ns
GL - Turn On Propagation Delay
(Dead time falling)
DSBL# Low to GH/GL Falling
Propagation Delay
tPD_DSBL#_F
Fig. 5
Fig. 5
-
15
-
DSBL# High to GH/GL Rising
Propagation Delay
tPD_DSBL#_R
tPWM_ON_MIN
-
20
-
-
-
PWM Minimum On-Time
30
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
4
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC789, SiC789A
www.vishay.com
Vishay Siliconix
ELECTRICAL SPECIFICATIONS
(DSBL# = SMOD# = 5 V, VIN = 12 V, VDRV and VCIN = 5 V, TA = 25 °C)
LIMITS
UNIT
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
DSBL# SMOD# INPUT
DSBL# Logic Input Voltage
VIH_DSBL#
VIL_DSBL#
VIH_SMOD#
VIL_SMOD#
Input logic high
Input logic low
Input logic high
Input logic low
2
-
-
-
-
-
-
0.8
-
V
2
-
SMOD# Logic Input Voltage
PROTECTION
0.8
VCIN rising, on threshold
-
2.7
-
3.7
3.1
4.1
Under Voltage Lockout
VUVLO
V
VCIN falling, off threshold
-
-
-
-
-
-
Under Voltage Lockout Hysteresis
THWn Flag Set (2)
THWn Flag Clear (2)
VUVLO_HYST
TTHWn_SET
TTHWn_CLEAR
TTHWn_HYST
VOL_THWn
575
160
135
25
mV
-
-
°C
V
THWn Flag Hysteresis (2)
-
THWn Output Low
ITHWn = 2 mA
-
0.02
Notes
(1)
Typical limits are established by characterization and are not production tested.
Guaranteed by design.
(2)
DETAILED OPERATIONAL DESCRIPTION
PWM Input with Tri-state Function
Pre-Charger Function
The PWM input receives the PWM control signal from the VR
controller IC. The PWM input is designed to be compatible
with standard controllers using two state logic (H and L) and
advanced controllers that incorporate tri-state logic (H, L
and tri-state) on the PWM output. For two state logic, the
PWM input operates as follows. When PWM is driven above
VPWM_TH_R the low-side is turned OFF and the high-side is
turned ON. When PWM input is driven below VPWM_TH_F the
high-side is turned OFF and the low-side is turned ON. For
tri-state logic, the PWM input operates as previously stated
for driving the MOSFETs when PWM is logic high and logic
low. However, there is a third state that is entered as the
PWM output of tri-state compatible controller enters its high
impedance state during shut-down. The high impedance
state of the controller’s PWM output allows the SiC789 and
SiC789A to pull the PWM input into the tri-state region (see
definition of PWM logic and Tri-State, fig. 4). If the PWM
input stays in this region for the Tri-state Hold-Off Period,
tTSHO, both high-side and low-side MOSFETs are turned
OFF. The function allows the VR phase to be disabled
without negative output voltage swing caused by inductor
ringing and saves a Schottky diode clamp. The PWM and
tri-state regions are separated by hysteresis to prevent
false triggering. The SiC789A incorporates PWM voltage
thresholds that are compatible with 3.3 V logic and the
SiC789 thresholds are compatible with 5 V logic.
When DSBL# is driven from below VIL_DSBL# to above
VIH_DSBL# the low-side is turned ON for a short duration
(60 ns typical) to refresh the BOOT capacitor in case it has
been discharged due to the driver being in standby for a
long period of time.
Diode Emulation Mode (SMOD#)
When SMOD# is logic low diode emulation mode is enabled
and the low-side is turned OFF. This is a non-synchronous
conversion mode that improves light load efficiency by
reducing switching losses. Conducted losses that occur in
synchronous buck regulators when inductor current is
negative can also be reduced. Circuitry in the external
controller IC detects when inductor current crosses zero
and drives SMOD# below VIL_SMOD# turning the low-side
MOSFET OFF. The function can be also be used for a
pre-biased output voltage. If SMOD# is left unconnected, an
internal pull up resistor will pull the pin to VCIN (logic high) to
disable the SMOD# function.
Thermal Shutdown Warning (THWn)
The THWn pin is an open drain signal that flags the presence
of excessive junction temperature. Connect, with
a
maximum of 20 kΩ, to VCIN. An internal temperature sensor
detects the junction temperature. The temperature
threshold is 160 °C. When this junction temperature is
exceeded the THWn flag is set. When the junction
temperature drops below 135 °C the device will clear the
THWn signal. The SiC789 and SiC789A do not stop
operation when the flag is set. The decision to shutdown
must be made by an external thermal control function.
Disable (DSBL#)
In the low state, the DSBL# pin shuts down the driver IC and
disables both high-side and low-side MOSFETs. In this
state, standby current is minimized. If DSBL# is left
unconnected, an internal pull-down resistor will pull the pin
to CGND and shut down the IC.
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
5
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC789, SiC789A
www.vishay.com
Voltage Input (VIN)
Vishay Siliconix
Bootstrap Circuit (BOOT)
This is the power input to the drain of the high-side power
MOSFET. This pin is connected to the high power
intermediate BUS rail.
The internal bootstrap diode and an external bootstrap
capacitor form a charge pump that supplies voltage to the
BOOT pin. An integrated bootstrap diode is incorporated so
that only an external capacitor is necessary to complete the
bootstrap circuit. Connect a boot strap capacitor with one
leg tied to BOOT pin and the other tied to PHASE pin.
Switch Node (VSWH and PHASE)
The switch node, VSWH, is the circuit power stage output.
This is the output applied to the power inductor and output
filter to deliver the output for the buck converter. The PHASE
pin is internally connected to the switch node, VSWH. This pin
is to be used exclusively as the return pin for the BOOT
capacitor. A 20 kΩ resistor is connected between GH and
PHASE to provide a discharge path for the HS MOSFET in
the event that VCIN goes to zero while VIN is still applied.
Shoot-Through Protection and Adaptive Dead Time
The SiC789 and SiC789A have an internal adaptive logic to
avoid shoot through and optimize dead time. The shoot
through protection ensures that both high-side and low-side
MOSFETs are not turned ON at the same time. The adaptive
dead time control operates as follows. The high-side and
low-side gate voltages are monitored to prevent the
MOSFET turning ON from tuning ON until the other
MOSFET's gate voltage is sufficiently low (< 1 V). Built in
delays also ensure that one power MOSFET is completely
OFF, before the other can be turned ON. This feature helps
to adjust dead time as gate transitions change with respect
to output current and temperature.
Ground Connections (CGND and PGND
)
PGND (power ground) should be externally connected to
CGND (control signal ground). The layout of the printed circuit
board should be such that the inductance separating CGND
and PGND is minimized. Transient differences due to
inductance effects between these two pins should not
exceed 0.5 V
Under Voltage Lockout (UVLO)
Control and Drive Supply Voltage Input (VDRV, VCIN
)
During the start up cycle, the UVLO disables the gate
drive, holding high-side and low-side MOSFET gates low,
until the supply voltage rail has reached a point at which
the logic circuitry can be safely activated. The SiC789 and
SiC789A also incorporate logic to clamp the gate drive
signals to zero when the UVLO falling edge triggers the
shutdown of the device. As an added precaution, a 20 kΩ
resistor is connected between GH and PHASE to provide a
discharge path for the HS MOSFET.
V
CIN is the bias supply for the gate drive control IC. VDRV is
the bias supply for the gate drivers. It is recommended to
separate these pins through a resistor. This creates a low
pass filtering effect to avoid coupling of high frequency gate
drive noise into the IC.
FUNCTIONAL BLOCK DIAGRAM
THWn
BOOT
GH
VIN
VDRV
Thermal monitor
& warning
VCIN
UVLO
DSBL#
VCIN
-
+
20K
PHASE
PWM logic
control &
state
Anti-cross
conduction
control
Vref = 1 V
GL
VSWH
PWM
CGND
-
+
machine
logic
Vref = 1 V
VDRV
GL
PGND
SMOD#
Fig. 3 - SiC789 and SiC789A Functional Block Diagram
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
6
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC789, SiC789A
www.vishay.com
Vishay Siliconix
DEVICE TRUTH TABLE
DSBL#
SMOD#
PWM
GH
L
GL
L
Open
L
X
X
L
X
X
L
L
H
L
L
L
H
L
H
Tri-state
L
H
L
L
H
L
L
H
H
H
H
L
H
L
H
H
H
L
H
Tri-state
L
PWM TIMING DIAGRAM
VTH_PWM_R
VTH_PWM_F
VTH_TRI_F
VTH_TRI_R
PWM
tPD_OFF_GL
tTSHO
GL
tPD_ON_GL
tPD_TRI_R
tTSHO
tPD_ON_GH
tPD_OFF_GH
tPD_TRI_R
GH
Fig. 4 - Definition of PWM Logic and Tri-State
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
7
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC789, SiC789A
www.vishay.com
OPERATION TIMING DIAGRAM: DSBL#
PWM
Vishay Siliconix
PWM
Enable
DSBL #
DSBL #
GH
GL
GH
GL
t
t
DSBL# High to GH Rising Propagation Delay
DSBL# High to GL Rising Propagation Delay
PWM
PWM
Disable
DSBL #
DSBL #
GH
GL
GH
GL
t
t
DSBL# Low to GL Falling Propagation Delay
DSBL# Low to GH Falling Propagation Delay
Fig. 5 - DSBL# Propagation Delay
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
8
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiC789, SiC789A
www.vishay.com
Vishay Siliconix
ELECTRICAL CHARACTERISTICS
Test condition: VIN = 12 V, VDRV = VCIN = 5 V, DSBL# = SMOD# = 5 V, VOUT = 1 V, LOUT = 270 nH (DCR = 0.32 mΩ), TA = 25 °C
(All power loss and normalized power loss curves show SiC789 and SiC789A losses only unless otherwise stated)
12.0
10.5
9.0
7.5
6.0
4.5
3.0
1.5
0.0
94
90
86
82
78
74
70
66
62
300 kHz
500 kHz
1 MHz
1 MHz
800 kHz
800 kHz
300 kHz
Complete converter efficiency
IN = [(VIN x IIN) + 5 V x (IVDRV + IVCIN)]
OUT = VOUT x IOUT, measured at output capacitor
P
P
500 kHz
0
0
0
5
10 15 20 25 30 35 40 45 50 55
Output Current, IOUT (A)
0
5
10 15 20 25 30 35 40 45 50 55
Output Current, IOUT (A)
Fig. 6 - Efficiency vs. Output Current
Fig. 9 - Power Loss vs. Output Current
12.0
10.5
9.0
7.5
6.0
4.5
3.0
1.5
0.0
94
90
86
82
78
74
70
66
62
VOUT = 1.0V
VOUT = 0.9V
fS = 500 kHz
VOUT = 0.7 V
VOUT = 0.7V
VOUT = 0.8 V
VOUT = 0.9 V
VOUT = 1.0 V
VOUT = 0.8V
fS = 500kHz
5
10 15 20 25 30 35 40 45 50 55
Output Current, IOUT (A)
0
5
10 15 20 25 30 35 40 45 50 55
Output Current, IOUT (A)
Fig. 7 - Efficiency vs. Output Current
Fig. 10 - Power Loss vs. Output Current
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
64
56
48
40
32
24
16
8
fS = 300 kHz
300 kHz
1 MHz
VOUT = 0.7 V
VOUT = 0.8 V
VOUT = 0.9 V
VOUT = 1.0 V
0
0
5
10 15 20 25 30 35 40 45 50 55
Output Current, IOUT (A)
15 30 45 60 75 90 105 120 135 150
PCB Temperature, TPCB (°C)
Fig. 8 - Power Loss vs. Output Current
Fig. 11 - Safe Operating Area
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
9
For technical questions, contact: powerictechsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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SiC789, SiC789A
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1.80
1.65
1.50
1.35
1.20
1.05
0.90
0.75
0.60
1.20
1.16
1.12
1.08
1.04
1.00
0.96
0.92
0.88
300 kHz
1 MHz
200 300 400 500 600 700 800 900 1000 1100 1200
0
5
10 15 20 25 30 35 40 45 50 55
Output Current, IOUT (A)
Switching Frequency, fS (kHz)
Fig. 12 - Power Loss vs. Switching Frequency
Fig. 15 - Driver Supply Current vs. Output Current
0.40
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
IF = 2 mA
VUVLO_RISING
VUVLO_FALLING
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Fig. 13 - UVLO Threshold vs. Temperature
Fig. 16 - BOOT Diode Forward Voltage vs. Temperature
3.2
3.4
3.0
2.6
2.2
1.8
1.4
1.0
0.6
0.2
2.8
VTH_PWM_R
VTH_PWM_R
2.4
VTRI_TH_F
VTRI
2.0
1.6
1.2
VTRI_TH_F
VTRI
VTRI_TH_R
VTRI_TH_R
0.8
VTH_PWM_F
VTH_PWM_F
0.4
0.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
-60 -40 -20
0
20 40 60 80 100 120 140
Driver Supply Voltage, VCIN (V)
Temperature (°C)
Fig. 14 - PWM Threshold vs. Temperature (SiC789A)
Fig. 17 - PWM Threshold vs. Driver Supply Voltage (SiC789A)
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
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SiC789, SiC789A
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4.8
4.2
3.6
3.0
2.4
1.8
1.2
0.6
0.0
4.8
4.2
3.6
3.0
2.4
1.8
1.2
0.6
0.0
VTH_PWM_R
VTRI_TH_F
VTRI
VTH_PWM_R
VTRI_TH_F
VTRI
VTRI_TH_R
VTRI_TH_R
VTH_PWM_F
VTH_PWM_F
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
-60 -40 -20
0
20 40 60 80 100 120 140
Driver Supply Voltage, VCIN (V)
Temperature (°C)
Fig. 18 - PWM Threshold vs. Temperature (SiC789)
Fig. 21 - PWM Threshold vs. Driver Supply Voltage (SiC789)
2.2
2.2
2.0
1.8
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VIH_DSBL#
VIH_DSBL#
1.6
1.4
VIL_DSBL#
1.2
1.0
0.8
VIL_DSBL#
0.6
-60 -40 -20
0
20 40 60 80 100 120 140
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
Driver Supply Voltage, VCIN (V)
Temperature (°C)
Fig. 19 - DSBL# Threshold vs. Temperature
Fig. 22 - DSBL# Threshold vs. Driver Supply Voltage
2.2
2.0
1.8
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
VIH_SMOD#
VIH_SMOD#
1.6
1.4
VIL_SMOD#
1.2
1.0
0.8
VIL_SMOD#
0.6
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
-60 -40 -20
0
20 40 60 80 100 120 140
Driver Supply Voltage, VCIN (V)
Temperature (°C)
Fig. 20 - SMOD# Threshold vs. Temperature
Fig. 23 - SMOD# Threshold vs. Driver Supply Voltage
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
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SiC789, SiC789A
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-8.0
-8.5
12.0
11.5
11.0
10.5
10.0
9.5
VSMOD# = 0 V
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
-12.0
9.0
8.5
8.0
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Fig. 24 - DSBL# Pull-down Current vs. Temperature
Fig. 26 - SMOD# Pull-up Current vs. Temperature
200
430
410
390
370
350
330
310
290
270
180
160
140
120
100
80
VPWM = FLOAT
VDSBL# = 0 V
60
40
-60 -40 -20
0
20 40 60 80 100 120 140
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
Temperature (°C)
Fig. 25 - Driver Shutdown Current vs. Temperature
Fig. 27 - Driver Quiescent Current vs. Temperature
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
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SiC789, SiC789A
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PCB LAYOUT RECOMMENDATIONS
Step 1: VIN / PGND Planes and Decoupling
Step 3: VCIN / VDRV Input Filter
VIN Plane
Vias for ground connection
CGND
PGND
Cvdrv
VIN CGND
Cvcin
VSWH
PGND Plane
1. Layout VIN and PGND planes as shown above
1. VCIN / VDRV input filter ceramic capacitors should be
placed as close as possible to IC. It is recommended to
connect two capacitors separately
2. Ceramic capacitors should be placed directly between
VIN and PGND, and as close as possible to IC for best
decoupling effect
2. VCIN capacitor should be placed between pin 2 and
pin 37 (CGND of driver IC) to achieve best noise filtering
3. Different ceramic capacitor values and packages should
be used to cover entire decoupling spectrum, e.g. 1210,
0805, 0603, and 0402
3. VDRV capacitor should be placed between pin 3 and
PGND to provide maximum instantaneous driver current
for low-side MOSFET during switching cycle. PGND can
be connected to inner ground plane through vias, as
shown above
4. Smaller capacitance values, placed closer to the IC’s VIN
pin(s), result in better high frequency noise absorbing
4. Pin 5 and pin 37 should be connected with CGND pad, as
shown above
Step 2: VSWH Plane
5. For connecting VCIN to CGND, it is recommended to use
a large plane to reduce parasitic inductance
Step 4: BOOT Resistor and Capacitor Placement
CGND
Snubber
VSWH
PGND Plane
1. Connect output inductor to IC with large plane to lower
resistance
2. VSWH plane also serves as a heat-sink for low-side
MOSFET. Please make the plane wide and short to
achieve best thermal path
1. The components need to be placed as close as possible
to IC, directly between PHASE (pin 7) and BOOT (pin 4)
3. If a snubber network is required, place components as
shown above
2. To reduce parasitic inductance, 0402 package size can
be used
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
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SiC789, SiC789A
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Step 5: Signal Routing
Vishay Siliconix
Step 7: Ground Connection
CGND
CGND
CGND
GND Plane
PGND
1. Route the PWM, SMOD#, DSBL#, and THWn signal
traces out of the top right corner, next to pin 1
1. It is recommended to make the entire first inner layer
(below top layer) the ground plane
2. The PWM signal is a very important signal, both signal
and return traces should not cross any power nodes on
any layer
2. The ground plane provides analog ground and power
ground connections
3. The ground plane provides shielding between noise
source on top layer and signal traces on bottom layer
3. It is best to “shield” these traces from power switching
nodes, e.g. VSWH, with a GND island to improve signal
integrity
Step 6: Adding Thermal Relief Vias
VIN Plane
VIN
CGND
VSWH
P
GND Plane
1. Thermal relief vias can be added to the VIN and CGND
pads to utilize inner layers for high-current and thermal
dissipation
2. To achieve better thermal performance, additional vias
can be added to VIN and PGND planes
3. The VSWH pad is a noise source and it is not
recommended to place vias on this pad
4. 8 mil drill for pads and 10 mils drill for planes are the
optional via sizes. Vias on pad may drain solder during
assembly and cause assembly issues. Please consult
with the assembly house for guidelines
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
14
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SiC789, SiC789A
www.vishay.com
Vishay Siliconix
RECOMMENDED LAND PATTERN PowerPAK® MLP66-40L in millimeters
2.200
0.276
2.200
0.276
0.100
0.100
0.100
0.100
0.200
0.025
0.025
40
40
0.100
0.100
4.600
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
15
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SiC789, SiC789A
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Vishay Siliconix
PACKAGE OUTLINE DRAWING MLP66-40L
2 x
0.08 C
A1
A2
K1
A
5
6
0.10 C A
D
Pin #1 dent
K2
A
0.41
30
D2-1
40
Pin 1 dot
by marking
31
2 x
1
0.10 C B
MLP66-40L
(6 mm x 6 mm)
10
21
B
20
11
D2-2
D2-3
C
(Nd-1)X
ref.
e
Top view
Side view
Bottom view
MILLIMETERS
INCHES
NOM.
0.029
DIM.
MIN.
0.70
0.00
NOM.
0.75
MAX.
0.80
MIN.
0.027
0.000
MAX.
0.031
0.002
A
A1
-
0.05
-
A2
0.20 ref.
0.25
0.008 ref.
0.098
b
0.20
0.30
0.45
0.078
0.011
D
6.00 BSC
0.50 BSC
6.00 BSC
0.40
0.236 BSC
0.019 BSC
0.236 BSC
0.015
e
E
L
0.35
0.013
0.017
N
40
40
Nd
Ne
D2-1
D2-2
D2-3
E2-1
E2-2
E2-3
K1
K2
10
10
10
10
1.45
1.45
2.35
4.35
1.95
1.95
1.50
1.55
1.55
2.45
4.45
2.05
2.05
0.057
0.057
0.095
0.171
0.076
0.076
0.059
0.061
0.061
0.096
0.175
0.080
0.080
1.50
0.059
2.40
0.094
4.40
0.173
2.00
0.078
2.00
0.078
0.73 BSC
0.21 BSC
0.028 BSC
0.008 BSC
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?62972.
S14-2287-Rev. B, 08-Dec-14
Document Number: 62972
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Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® MLP66-40 Case Outline
K1
2 x
0.08 C
A1
A2
A
5
6
0.10 C A
K2
D
A
Pin 1 dot
by marking
0.41
30
D2-1
31
40
2 x
1
0.10 C B
MLP66-40
(6 mm x 6 mm)
10
21
B
20
11
D2-2
D2-3
C
(Nd-1)X
ref.
e
Top View
Bottom View
Side View
MILLIMETERS
INCHES
DIM.
MIN.
0.70
0.00
NOM.
0.75
MAX.
0.80
MIN.
0.027
0.000
NOM.
0.029
MAX.
0.031
0.002
A (8)
A1
-
0.05
-
A2
b (4)
0.20 ref.
0.25
0.008 ref.
0.098
0.20
0.30
0.45
0.078
0.011
D
6.00 BSC
0.50 BSC
6.00 BSC
0.40
0.236 BSC
0.019 BSC
0.236 BSC
0.015
e
E
L
0.35
0.013
0.017
N (3)
Nd (3)
Ne (3)
D2-1
D2-2
D2-3
E2-1
E2-2
E2-3
K1
40
40
10
10
10
10
1.45
1.45
2.35
4.35
1.95
1.95
1.50
1.55
1.55
2.45
4.45
2.05
2.05
0.057
0.057
0.095
0.171
0.076
0.076
0.059
0.061
0.061
0.096
0.175
0.080
0.080
1.50
0.059
2.40
0.094
4.40
0.173
2.00
0.078
2.00
0.078
0.73 BSC
0.21 BSC
0.028 BSC
0.008 BSC
K2
ECN: T14-0826-Rev. B, 12-Jan-15
DWG: 5986
Notes
1. Use millimeters as the primary measurement
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994
3. N is the number of terminals. Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body
6. Exact shape and size of this feature is optional
7. Package warpage max. 0.08 mm
8. Applied only for terminals
Revision: 12-Jan-15
Document Number: 64846
1
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PAD Pattern
Vishay Siliconix
www.vishay.com
Recommended Land Pattern PowerPAK® MLP66-40L
2.200
0.276
2.200
0.276
0.100
0.100
0.100
0.100
0.200
0.025
0.025
1
1
40
40
0.100
0.100
4.600
All Dimensions are in milimeters
Revision: 28-Feb-14
Document Number: 67964
1
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Legal Disclaimer Notice
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Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of
typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding
statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a
particular product with the properties described in the product specification is suitable for use in a particular application.
Parameters provided in datasheets and / or specifications may vary in different applications and performance may vary over
time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk.
Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for
such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document
or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Revision: 13-Jun-16
Document Number: 91000
1
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