TFDU8108-TT3_技术文档

TFDU8108

Vishay Semiconductors

Very Fast Infrared Transceiver Module (VFIR, 16 Mbit/s)

IrDA^®Serial Interface Compatible

2.7 V to 5.5 V Supply Voltage Range

Description

The TFDU8108 transceiver is part of a family of low

power consumption infrared transceiver modules. It is

compliant to the IrDA physical layer standard for VFIR

infrared data communication, supporting IrDA speeds

up to 16 Mbit/s (VFIR) and carrier based remote con-

trol modes up to 2 MHz. Integrated within the trans-

ceiver module are a PIN photodiode, an infrared emit-

ter (IRED), and a low-power control IC.

20110

At a minimum, a Vcc bypass capacitor is the only

external component required implementing a com-

plete solution. For limiting the transceiver’s internal

power dissipation one additional resistor might be

necessary. The transceiver can be operated with

logic I/O voltages as low as 1.8 V.

• Tri-State-receiver output, weak pull-up when in

Features

• Compliant to the latest IrDA physical

layer standard (up to 16 Mbit/s), HP-SIR^®,

Sharp ASK^®and TV Remote Control

• Compliant to the IrDA "Serial Interface

Specification for Transceivers"

• Surface mount Soldering to side and top view ori-

entation

output is disabled

• Built - In EMI Protection - No external shielding

necessary

• Pin to Pin compatible to legacy Vishay SIR and

FIR infrared transceivers

• Eye safety class 1 (IEC60825-1, ed. 2001), limited

LED on-time, LED current is controlled, no single

fault to be considered

• Lead (Pb)-free device

• Qualified for lead (Pb)-free and Sn/Pb processing

(MSL4)

• Device in accordance with RoHS 2002/95/EC and

WEEE 2002/96/EC

• Split power supply, can be driven by a separate

power supply not loading the regulated supply.

U.S. Pat. No. 6,157,476

e3

3

• Surface Mount package 9.7 x 4.7 x 4.0 mm

for side view and top view applications

• Operating supply voltage from 2.7 V to 5.5 V

• Compliant to all logic levels between 1.8 V and 5 V

• TV Remote Control support

• Low Power consumption (2 mA idle supply cur-

rent)

• Power Shutdown mode (1 µA shutdown current)

Applications

• Notebook Computers, Desktop PCs, Palmtop

computers (Win CE, Palm PC), PDAs

• Telecommunication products (Cellular Phones,

Pagers)

• Digital still and video cameras

• Printers, fax machines, photocopiers,

screen projectors

• Internet TV boxes, Video Conferencing Systems

• External infrared adapters (dongles)

• Medical and industrial data collection devices

• MP3 players

Package

TFDU8108

Baby Face

(Universal)

weight 200 mg

19497

www.vishay.com

360

Document Number 82558

Rev. 1.8, 16-Mar-07

TFDU8108

Vishay Semiconductors

Ordering Information

Part Number

TFDU8108-TR3

TFDU8108-TT3

TFDU8108

Description

Oriented in carrier tape for side view surface mounting

Oriented in carrier tape for top view surface mounting

In tube

Qty / Reel

1000 pcs

50 pcs

Functional Block Diagram

V

: Analog supply voltage

CC1

logic

CC2

V

cc1

V

logic

ASIC

: Digital supply voltage, I/O reference voltage

: Independent supply voltage for the LED driver

Voltage

Regulator

RXD

Serial Interface according the IrDA standard "Serial

Interface for Transceiver Control"

SCLK: Clock line as timing reference*)

TXD: TX/SWDAT - line*)

+

-

+

V

cc2

Driver

V

IRKAT

AGC

RXD: RX/SRDAT - line*)

SCLK

Serial Interface

GND

TXD

*) see Appendix A for definitions

GND

19493

Figure 1. Functional Block Diagram

Definitions:

In the Vishay transceiver data sheets the following nomenclature is

• VFIR: 16 Mbit/s

used for defining the IrDA operating modes:

MIR and FIR were implement with IrPhy 1.1, followed by IrPhy 1.2,

adding the SIR Low Power Standard. IrPhy 1.3 extended the Low

Power Option to MIR and FIR and VFIR was added with IrPhy 1.4.

A new version of the standard in any case obsoletes the former ver-

sion.

•

SIR: 2.4 kbit/s to 115.2 kbit/s, equivalent to the ba-

sic serial infrared standard with the physical layer

version IrPhy 1.0

•

MIR: 576 kbit/s to 1152 kbit/s

FIR: 4 Mbit/s

Pin Description

Pin Number

Function

Description

I/O

Active

1

IRED Anode IRED anode to be externally connected to V_CC2This pin is allowed

to be supplied from an uncontrolled power supply seperated from

the controlled V_CC1- supply.

2

3

4

IRED Cathode

TXD

IRED Cathode, internally connected to driver transistor

Transmit Data Input, dynamically loaded

I

HIGH

LOW

RXD

Received Data Output, Tri-State CMOS driver output capable of

driving a standard CMOS or TTL load. No external pull-up or pull-

down resistor is required. Pin is current limited for protection against

programming errors. The output is loaded with a weak 500 kΩ pull-

up, when in SD mode. The RXD echoes the optical TXD signal

duration transmission.

O

5

6

SCLK

V_CC

Serial Clock, dynamically loaded

Supply Voltage

I

HIGH

7

V_logic

Supply voltage for digital part, 1.8 V to 5.5 V, defines logic swing for

TXD, SCLK, and RXD

8

GND

Ground

Document Number 82558

Rev. 1.8, 16-Mar-07

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361

TFDU8108

Vishay Semiconductors

BabyFace (Universal)

"U" Option BabyFace

(Universal)

IRED

Detector

1

2

3 4

5

6

7 8

17087

Figure 2. Pinning

Absolute Maximum Ratings

Reference point Ground (pin 8) unless otherwise noted.

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter

Test Conditions

Symbol

Min

Typ.

Max

Unit

V

Supply voltage range,

transceiver

0 V < V_CC2< 6 V

V_CC1

- 0.5

6

Supply voltage range,

transmitter

0 V < V_CC1< 6 V

V_CC2

V_logic

- 0.5

6

V

Supply voltage range,

transceiver logic

IRED anode voltage

V_IREDA

V_TXD

- 0.5

6

V

Transmitter data input voltage

Receiver data output voltage

Input currents

V_logic+ 0.5

10

V_RXD

V

For all pins, except IRED anode

mA

Output sinking current

Power dissipation

25

mA

See derating curve, figure 7

P_D

T_J

350

mW

Junction temperature

125

°C

Ambient temperature range

(operating)

T_amb

0

+ 85

Storage temperature range

Soldering temperature

T_stg

- 40

+ 100

260

°C

See recommended solder

profile (see figures 4 to 6)

Average output current

I

_IRED(DC)

130

600

mA

mm

Repetitive pulse output current < 90 µs, t_on< 20 %

Virtual source size Method: (1 - 1/e) encircled

energy

I_IRED(RP)

d

2.5

2.8

Maximum Intensity for Class 1 Operation of IEC825-1 or

EN60825-1, edition Jan. 2001

Internal

limitation to

class 1

IrDA^®specified maximum limit

500

mW/sr

Due to the internal limitation measures the device is a "class1" device. It will not exceed the IrDA^®intensity limit of 500 mW/sr.

www.vishay.com

362

Document Number 82558

Rev. 1.8, 16-Mar-07

TFDU8108

Vishay Semiconductors

Electrical Characteristics

Transceiver

T

= 25 °C, V = 2.7 V to 5.5 V unless otherwise noted.

amb

CC

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter

Test Conditions

Symbol

Min

Typ

Max

Unit

V

Supply voltage V_CC1

V_CC1

2.7

5.5

Supply voltage V_logic

Dynamic supply current

V_logic

1.8

5.5

V

Receive mode only. In transmit mode, add the averaged programmed current of IRED current as I_CC2

Active, SIR, E_e= 0 klx (idle)

T = - 25 °C to 85 °C

I_CC1

I_logic

0.8

2.5

10

5

mA

µA

Dynamic supply current

Active, VFIR, E_e= 0 klx, (idle)

T = - 25 °C to 85 °C

active, no load E_e= 0 klx, (idle)

T = - 25 °C to 85 °C

E_e= 1 klx*) receive mode,

1

mA

E

_Eo= 100 mW/m²

(9.6 kbit/s to 4.0 Mbit/s),

R_L= 10 kΩ to V_logic= 5 V,

C_L= 15 pF

T = - 25 °C to 85 °C

Standby supply current

Inactive, set to shutdown mode

T = 25 °C, E_e= 0 klx

I_SD

2

µA

T = 25 °C, E_e= 1 klx*) **)

Shutdown mode, **)

T = 85 °C

I_SD

5

µA

Operating temperature range

Output voltage low

T_A

0

+ 85

0.4

°C

V

C

_load= 15 pF,

V_logic= 3 V, I_OLO< + 500 µA

_load= 15 pF,

_logic= 5 V, I_OHI< - 250 µA

V_OLO

Output voltage high

C

V_OHI

0.8 x V_logic

V

Input voltage high (TXD, SCLK)

V_IL

V_IH

V_IL

- 0.5

0.5

6

V_logic- 0.3

V

logic decision level

(TXD, SCLK) ***)

0.5 x V_logic

Input leakage current

(TXD, SCLK)

I_L

- 10

+ 10

5

µA

pF

Input capacitance

C_I

*) Standard illuminant A.

**) In shutdown condition the device is not ambient light sensitive.

***) The device will work with less tight levels than specified min/max values of the logic input voltage. It is recommended to use the speci-

fied min/max values to minimize operating/standby supply currents.

Document Number 82558

Rev. 1.8, 16-Mar-07

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363

TFDU8108

Vishay Semiconductors

Optoelectronic Characteristics

Receiver

T

= 25 °C, V = 2.7 V to 5.5 V unless otherwise noted.

CC

amb

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter

Test Conditions

Symbol

Min

Typ.

Max

Unit

mW/m²

Minimum detection threshold

irradiance

9.6 kbit/s to 115.2 kbit/s, SIR

λ = 850 nm to 900 nm

E_e

25

40

mW/m²

kW/m²

Minimum detection threshold

irradiance

1.152 Mbit/s, MIR

λ = 850 nm to 900 nm

E_e

65

85

90

Minimum detection threshold

irradiance

4 Mbit/s, FIR

λ = 850 nm to 900 nm

Minimum detection threshold

irradiance

16 Mbit/s, VFIR

λ = 850 nm to 900 nm

E_e

160

10

200

Maximum detection threshold

irradiance

λ = 850 nm to 900 nm

E_e

5

mW/m²

µs

Logic LOW receiver input

irradiance

E_e

4

RXD pulse width of output

signal, 50 % SIR mode

Input pulse length 20 μs,

9.6 kbit/s

t_PW

1.3

200

105

225

32

2.6

260

145

285

52

RXD pulse width of output

signal, 50 % SIR mode

Input pulse length 1.41 μs,

115.2 kbit/s

µs

ns

RXD pulse width of output

signal, 50 % MIR mode

Input pulse length 217 ns,

1.152 Mbit/s

RXD pulse width of output

signal, 50 % FIR mode

Input pulse length 125 ns,

4 Mbit/s

125

42

RXD pulse width of output

signal, 50 % FIR mode

Input pulse length 250 ns,

4 Mbit/s

RXD pulse width of output

signal, 50 %

Input pulse length 16 Mbit/s,

VFIR

39.5 ns < P_wopt< 43 ns

RXD rise time of output signal

RXD fall time of output signal

20 % to 80%, C_L= 15 pF

90 % to 10%, C_L= 15 pF

t_{r (RXD)}

2

5

15

ns

30

Input irradiance = 40 mW/m²,

115.2 kbit/s

RXD Jitter, leading edge, SIR

mode

350

Input irradiance = 100 mW/m²,

1.152 Mbit/s

Input irradiance = 100 mW/m²,

4 Mbit/s

Input irradiance = 200 mW/m²,

16 Mbit/s, VFIR mode

RXD Jitter, leading edge, MIR

mode

40

20

7

ns

RXD Jitter, leading edge, FIR

mode

RXD Jitter, leading edge

5

RXD output pulse delay

Latency

t_RXDdel

t_LAT

1

µs

55

100

500

Receiver Startup Time

t_POR

100

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364

Document Number 82558

Rev. 1.8, 16-Mar-07

TFDU8108

Vishay Semiconductors

Transmitter

T

= 25 °C, V = 2.7 V to 5.5 V unless otherwise noted.

amb

CC

Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.

Parameter

Test Conditions

Symbol

Min

Typ.

Max

Unit

mA

IRED operating current

internally controlled*)

V_CC1= 3.3 V, the maximum

I_D

8

16

32

64

128

256

512

current is limited internally. An

external resistor can be used to

reduce the power dissipation at

higher operating voltages, see

derating curve.

600

Max. output radiant intensity

Output radiant intensity

V

_CC= 3.3 V, α = 0°,15°

I_e

0.3

mW/sr/mA

TXD = High, R1 = 0 Ω

programmed to max. power

level

V

_CC= 5.0 V, α = 0°, 15°

I_e

0.04

2.20

mW/sr

µs

TXD = Low, programmed to

shutdown mode

TXD pulse width of output

signal, 50 %

Input pulse length 1.63 µs,

115.2 kbit/s

t_PW

1.45

TXD pulse width of output

signal, 50 %

Input pulse width 0.1 µs < t_TXD

< 60 μs

t_TXD

Input pulse width t_TXD≥ 60 µs

20

60

µs

ns

TXD pulse width of output

signal, 50 %

Input pulse length 250 ns,

(FIR, double pulse)

t_PW

240

260

TXD pulse width of output

signal, 50 %

Input pulse length 217.0 (MIR)

115

260

135

ns

TXD pulse width of output

signal, 50 %

FIR mode

Input pulse length 125 ns (FIR)

125

TXD pulse width of output

signal, 50 %

Input pulse length 41.7 ns

t_PW

α

38.3

870

45.0

ns

°

Output radiant intensity, angle of

half intensity

24

40

Peak - emission wavelength

λ_p

900

nm

Spectral bandwidth

nm

ns

Optical rise time, fall time

t_ropt, t_fopt

19

15

Optical overshoot

%

*) Programmable using the"serial interface“ programming sequence, see Appendix A for implementation guidance and Appendix B for in-

tensity values and range.

Document Number 82558

Rev. 1.8, 16-Mar-07

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365

TFDU8108

Vishay Semiconductors

Recommended Circuit Diagram

Recommended Application Circuit

Components

Operated with a low impedance power supply the

TFDU8108 series devices need no external compo-

nents. However, depending on the entire system

design and board layout, additional components may

be required (see figure 3).

Component

Recommended Value

C1

C2

R1

4.7 µF, 16 V

0.1 µF, Ceramic

Recommended for V_CC2≥ 4 V

Depending on current limit

< 10 Ω, 0.125 W

R2

V

CC2

R1

CC1

IRED

Cathode

IRED

Anode

I/O and Software

R2

For operating the device from a Controller I/O a driver

software must be implemented.

Rxd

Txd

Vcc

SCLK

C1

C2

Mode Switching and Programming

V

logic

GND

The generic IrDA "Serial Interface programming"

needs no special settings for the device. Only the cur-

rent control table must be taken into account. For the

description see the Appendix A, B and C and the IrDA

document "Serial Interface specification for transceiv-

ers"

V

logic

SCLK

Txd

17089

Figure 3. Recommended Application Circuit

All external components (R, C) are optional

Vishay transceivers integrate a sensitive receiver and

a built-in power driver. The combination of both needs

a careful circuit board layout. The use of thin, long,

resistive and inductive wiring must be avoided. The

inputs (TXD, SCLK) and the output RXD should be

directly DC-coupled to the I/O circuit.

R1 is used for reducing the power dissipation when

operating the device at a supply voltage of V_CC2

> 4 V.

For increasing the max. output power of the IRED, the

value of the resistor should be reduced. It should be

dimensioned to keep the IRED anode voltage below

4 V for using the full temperature range. For device

and eye protection the pulse duration and current are

internally limited.

R2, C1 and C2 are optional and dependent on the

quality of the supply voltage V

and injected noise.

CC1

An unstable power supply with dropping voltage dur-

ing transmission may reduce sensitivity (and trans-

mission range) of the transceiver.

The placement of these parts is critical. It is strongly

recommended to position C2 as near as possible to

the transceiver power supply pins. An electrolytic

capacitor should be used for C1 while a ceramic

capacitor is used for C2.

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366

Document Number 82558

Rev. 1.8, 16-Mar-07

TFDU8108

Vishay Semiconductors

Recommended Solder Profiles

Solder Profile for Sn/Pb Soldering

The data for the drying procedure is given on labels

on the packing and also in the application note

"Taping, Labeling, Storage and Packing"

260

10 s max. at 230 °C

240

220

200

180

160

140

120

100

80

240 °C max.

(http://www.vishay.com/docs/82601/82601.pdf).

2...4 °C/s

160 °C max.

275

≥

T

peak

= 260 °C

T

255 °C for 10 s....30 s

250

225

200

175

150

125

100

75

120 s...180 s

90 s max.

≥

T

217 °C for 70 s max

2...4 °C/s

60

40

30 s max.

70 s max.

20

0

50

100

150

200

250

300

350

90 s...120 s

19535

Time/s

2 °C...4 °C/s

2 °C...3 °C/s

50

Figure 4. Recommended Solder Profile for Sn/Pb soldering

25

0

Lead (Pb)-Free, Recommended Solder Profile

0

100

150

Time/s

200

250

300

350

The TFDU8108 is a lead (Pb)-free transceiver and

qualified for lead (Pb)-free processing. For lead (Pb)-

free solder paste like Sn (3.0 - 4.0) Ag (0.5 - 0.9) Cu,

there are two standard reflow profiles: Ramp-Soak-

Spike (RSS) and Ramp-To-Spike (RTS). The Ramp-

Soak-Spike profile was developed primarily for reflow

ovens heated by infrared radiation. With widespread

use of forced convection reflow ovens the Ramp-To-

Spike profile is used increasingly. Shown below in fig-

ure 5 and 6 are VISHAY's recommended profiles for

use with the TFDU8108 transceivers. For more

details please refer to the application note

19532

Figure 5. Solder Profile, RSS Recommendation

280

260

240

220

200

180

160

140

120

100

80

T

peak

= 260 °C max

< 4 °C/s

1.3 °C/s

≤

Time above 217 °C t 70 s

Time above 250 °C t 40 s

Peak temperature T = 260 °C

< 2 °C/s

peak

60

“SMD Assembly Instructions”

(http://www.vishay.com/docs/82602/82602.pdf).

40

20

0

50

100

150

200

250

300

A ramp-up rate less than 0.9 °C/s is not recom-

mended. Ramp-up rates faster than 1.3 °C/s could

damage an optical part because the thermal conduc-

tivity is less than compared to a standard IC.

Time/s

Figure 6. RTS Recommendation

Current Derating Diagram

Wave Soldering

For TFDUxxxx and TFBSxxxx transceiver devices

wave soldering is not recommended.

600

500

400

300

Manual Soldering

Manual soldering is the standard method for lab use.

However, for a production process it cannot be rec-

ommended because the risk of damage is highly

dependent on the experience of the operator. Never-

theless, we added a chapter to the above mentioned

application note, describing manual soldering and

desoldering.

Current derating as a function of

the maximum forward current of

IRED. Maximum duty cycle: 25 %.

200

100

0

- 40 - 20

0

20 40 60 80 100 120 140

Temperature (°C)

Storage

14875

The storage and drying processes for all VISHAY

transceivers (TFDUxxxx and TFBSxxx) are equiva-

lent to MSL4.

Figure 7. Current Derating Diagram

Document Number 82558

Rev. 1.8, 16-Mar-07

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367

TFDU8108

Vishay Semiconductors

TFDU8108 - BabyFace (Universal) Package

(Mechanical Dimensions)

18473-1

Figure 8. Mechanical drawing, dimensions in mm, tolerance 0.2 mm if not otherwise shown

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368

Document Number 82558

Rev. 1.8, 16-Mar-07

TFDU8108

Vishay Semiconductors

Recommended SMD Pad Layout

7 x 1 = 7

0.6 ( 0.7)

2.5 ( 2.0)

1

8

1

16524-1

Figure 9. Mechanical drawing, dimensions in mm, tolerance 0.2 mm if not otherwise shown

Reel Dimensions

Drawing-No.: 9.800-5090.01-4

Issue: 1; 29.11.05

14017

Figure 10. Reel dimensions, dimensions in mm, tolerance 0.2 mm

Tape Width

A max.

N

W₁min.

W₂max.

W₃min.

W₃max.

mm

24

mm

330

mm

60

mm

24.4

30.4

23.9

27.4

Document Number 82558

Rev. 1.8, 16-Mar-07

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369

TFDU8108

Vishay Semiconductors

Tape Dimensions

19822

Drawing-No.: 9.700-5251.01-4

Issue: 3; 02.09.05

Figure 11. Tape drawing,TFDU8108 for top view mounting, tolerance 0.1 mm

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370

Document Number 82558

Rev. 1.8, 16-Mar-07

TFDU8108

Vishay Semiconductors

19875

Drawing-No.: 9.700-5297.01-4

Issue: 1; 04.08.05

Figure 12. Tape drawing, TFDU8108 for side view mounting

after mounting, tolerance 0.1 mm

Document Number 82558

Rev. 1.8, 16-Mar-07

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371

TFDU8108

Vishay Semiconductors

Tube drawing

19496

Figure 13. Tube drawing

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372

Document Number 82558

Rev. 1.8, 16-Mar-07

TFDU8108

Vishay Semiconductors

Appendix A

Serial Interface Implementation

Basics of the IrDA Definitions

The data lines are multiplexed with the transmitter The SCLK line is always driven by the master and is

and receiver signals and separate clocks are used used to clock the data being written to or read from

since the transceivers respond to the same address. the slave.

When no infrared communication is in progress and

the serial bus is idle, the IRTX line is kept low and

IRRX is kept high.

This line is driven by a totem-pole output buffer. The

SCLK line is always stopped when the serial interface

is idle to minimize power consumption and to avoid

any interference with the analog circuitry inside the

slave. There are no gaps between the bytes in either

the Command or Response Phase. Data is always

transferred in Little Endian order (least significant bit

first). Input data is sampled on the rising edge of

SCLK. IRTX/SWDAT output data from the controller

is clocked by SCLK falling edge. IRRX/SRDAT output

data from the slave is clocked by SCLK rising edge.

Each byte of data in both Command and Response

Phases is preceded by one start bit. The data to be

written to the slave is carried on the IRTX/SWDAT

line. When the control interface is idle, this line carries

the infrared data signal used to drive the transmitter

LED. When the first low-to-high transition on SCLK is

detected at the beginning of the command sequence,

the slave will disable the transmitter LED. When the

first low-to-high transition on SCLK is detected at the

beginning of the command sequence, the slave will

disable the transmitter LED. The infrared controller

then outputs the command string on the IRTX/

SWDAT line. On the last SCLK cycle of the command

sequence the slave re-enables the transmitter LED

and normal infrared transmission can resume. No

transition on SCLK must occur until the next com-

mand sequence otherwise the slave will disable the

transmitter LED again. Read data is carried on the

IRRX/SRDAT line. The slave disables the internal sig-

nal from the receiver photo diode during the response

phase of a read transaction. The addressed slave will

output the read data on the IRRX/SRDAT line regard-

less of the setting of the Receiver Output Enable bit in

the main control register (main-ctrl-0). Non addressed

slaves will tri-state the IRRX/SRDAT line. When the

transceiver is powered up, the IRTX/SWDAT line

should be kept low and SCLK should be cycled at

least 30 times by the infrared controller before the first

command is issued on the IRTX/SWDAT line, see fig-

ure 18. This guarantees that the transceiver interface

circuitry will properly initialize and be ready to receive

commands from the controller. In case of a multiple

transceiver configuration, only one transceiver should

have the receiver output enabled.

OFE A

IRTX/SWDAT

IRRX/SRDAT

TX/SWDAT

Optical

Transceiver

RX/SRDAT

Infrared

Controller

SCLK1

SCLK2

SCLK

VCC

OFE B

TX/SWDAT

RX/SRDAT

SCLK

Optical

Transceiver

17092

Figure 14. Interface to Two Infrared Transceivers

Shielded Cable

Connector

LVDS

Transceiver

VCC

GND

VCC

GND

IRTX+/SWDAT+

IRTX-/SWDAT-

IRRX+/SRDAT+

IRRX-/SRDAT-

SCLK+

TX/SWDAT

RX/SRDAT

SCLK

Infrared

Controller

Optical

Transceiver

SCLK-

A_SL

GND

17093

Figure 15. Infrared Dongle with Differential Signaling

Functional description

The serial interface is designed to interconnect two or

more devices. One of the devices is always in control

of the serial interface and is responsible for starting

every transaction. This device functions as the bus

master and is always the infrared controller. The infra-

red transceivers act as bus slaves and only respond

to transactions initiated by the master. A bus transac-

tion is made up of one or two phases. The first phase

is the Command Phase and is present in every trans-

action. The second phase is the Response Phase

and is present only in those transactions in which data

must be returned from the slave. If the operation

involves a data transfer from the slave, there will be a

Response Phase following the Command Phase in

which the slave will output the data.

The Response Phase, if present, must begin 4 clock

cycles after the last bit of the Command Phase, as

shown in figures 16 and 17, otherwise it is assumed

that there will be no response phase and the master

can terminate the transaction.

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A series resistor (approx. 200 Ω) should be placed on

the receiver output from each transceiver to prevent

large currents in case a conflict occurs due to a pro-

gramming error.

Note: Generally the abbreviations IRTX/IRRX and TXD/RXD are

used for the data transmission lines for the optical communication.

IRTX/IRRX is mostly used at the controller, TXD/RXD at the trans-

ceiver

19505

Figure 19. Write Data Waveform with Extended Index

START ADDRESS & CONTROL

SCLK

IRTX/

SWDAT

IRRX/

19506

SRDAT

Figure 20. Read Data Waveform

19502

Figure 16. Special Command Waveform

START ADDRESS,INDEX, DIR. START

DATA

SCLK

IRTX/

SWDAT

19507

Figure 21. Read Data Waveform with Extended Index

IRRX/

SRDAT

Note: During a read transaction the infrared controller sets the

IRTX/SWDAT line high after sending the address and index byte

(or bytes). It will then set it low two clock cycles before the end of

the transaction. It is strongly recommended that optical transceiv-

ers monitor this line instead of counting clock cycles in order to

detect the end of the read transaction. This will always guarantee

correct operation in case two or more transceivers from different

manufacturers are sharing the serial interface.

19503

Figure 17. Write Data Waveform

Note: If the APEN bit in control register 0 is set to 1, the internal sig-

nal from the receiver photo diode is disconnected and the IRRX/

SRDAT line is pulsed low for one clock cycle at the end of a write

or special command.

> 30 CLOCK CYCLES

ꢀ

ꢁ

SCLK

IRTX/

SWDAT

IRRX/

SRDAT

19504

Figure 18. Initial Reset Timing

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Switching Characteristics

Maximum capacitive load = 20 pF

*)

Symbol

Parameters

Test Conditions

Min.

250

Max.

Unit

ns

t_CKp

SCLK Clock Period

Rising edge of SCLK to next rising edge

of SCLK

infinity

t_CKh

t_CKI

SCLK Clock High Time

SCLK Clock Low Time

At 2.0 V for single-ended signals

At 0.8 V for single-ended signals

After falling edge of SCLK

60

80

ns

t_DOtv

Output Data Valid

40

(from infrared controller)

t_DOth

t_DOrv

t_DOrh

Output Data Hold

(from infrared controller)

After falling edge of SCLK

After rising edge of SCLK

0

ns

Output Data Valid

(from optical transceiver)

40

60

Output Data Hold

(from optical transceiver)

t_DOrf

t_DIs

Line Float Delay

Input Data Setup

Input Data Hold

After rising edge of SCLK

Before rising edge of SCLK

After rising edge of SCLK

ns

10

5

t_DIh

^*)Maximum capacitive load = 20 pF. That is is different from "Serial interface - specification". For the bus protocol see "RECOMMENDED

SERIAL INTERFACE FOR TRANSCEIVER CONTROL, Draft Version 1.0a, March 29, 2000, IrDA". In Appendix B the transceiver related

data are given.

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Appendix B

Application Guideline

In the following some guideline is given for handling A data word consists of one byte preceded by one

the TFDU8108 in an application ambient, especially start bit.

for testing. It is also a guideline for interfacing with a

controller. We recommend to use for first evaluation

the Vishay IRM1802 controller. For more information

see the special data sheet. Driver software is avail-

able on request. Contact irdc@vishay.com.

The specified serial interface allows the communica-

tion between infrared controller and transceiver

through write and read transactions. In two register

blocks with different functions all data is stored for

operating the interface. The Main Control Registers

allow write and read transactions and here the exe-

cutable configuration of the device is stored. The

Extended Indexed Registers contain the description

of the supported functionality of the device and can be

read only.

Serial Interface Capability of the Vishay

IrDA Transceivers

Abstract

A serial interface allows an infrared controller to com-

municate with one or more infrared transceivers. The

basic specification of the IrDA specified interface is

described in "Serial Interface for Transceiver Control,

v 1.0a", IrDA.

Power-on

After power on the transceiver is in the default mode

shown in table B1.

Addressing

This part of the document describes the capabilities of

the serial interface implemented in the Vishay IrDA The transceiver is addressable by three address bits.

transceivers TFDU8108. The VFIR (16 Mbit/s) device There are individual and common addresses with the

TFDU8108 and the FIR device TFDU6108 (4 Mbit/s) values shown in table B2.

are using the same interface specification (with spe-

cific identification and programming).

Registers Data Depth

In general data registers use a data depth of eight

bits. Sometimes it is not necessary to implement the

IrDA Serial Interface Basics

The "Serial Interface for Transceiver Control" is a full depth. In such cases the invisible bits are consid-

master/slave synchronous serial bus, which uses the ered as a zero.

TXD and RXD as data lines and the SCLK as clock

line with a minimum period of 250 ns. The transceiver

works always as slave and jumps into a control mode

The register content is listed in the tables B4 to B7.

on the first rising edge of the clock line remaining

Registers

there until the command phase is finished. After

power-on, it is required to initialize the transceiver by

at least 30 clock cycles of SCLK with TXD continu- Data acknowledgement generated by the slave is

Data Acknowledgment

ously low before starting programming.

available if the APEN bit is set to 1 in the common

control register, see the "main_ctrl_0" register values

table B4. In IrDA default state this functionality is dis-

abled. It is recommended to enable this function.

If TXD gets active (high) during the initialization period

the initialization must be repeated.

Table B1: Power-on default mode

Function

TFDU8108

sleep

Power Mode (active or sleep)

RXD (Receive)

disable (floating tri-state)

disable

TXD_LED (Emitter driver):

APEN (Acknowledgment)

Infrared Operating Mode (Speed)

Transmitter Power (Intensity setting)

disable

SIR

max. SIR power level

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Table B2: Addressing

Description

Address value ADDR [2:0]

Individual address

010

111

Common (broadcast) address

Table B3: Index Commands

Commands INDEX

[3:0]

Mode

write/read

Actions

Register Name

Data Bits

Data

TFDU8108

default

0h

1h

W/R

X

Common control

Infrared mode

TXD power level

Not used

main-ctrl-0 register

main-ctrl-1 register

main-ctrl-2 register

[4:0]

[7:0]

[7:4]

00h

70h

2h

3h - Bh

Ch

X

Not used

Dh

W

Reset transceiver,

Only one byte!

R

X

Not used

Eh

Fh

W

R

Not used

Extended indexing

Note: The main_ctrl_1 register is written software dependent on the offset value stored in ext_ctrl_7 and ext_ctrl_8 registers.

The main_ctrl_1 register can be set to the following values, shown in the table.

Tables B4 to B7: Control Register Values

The status of the entire transceiver is stored in the

control registers.

Table B4: Register main-ctrl-0

Command structure:

C

0

bit 0

bit 1

bit 2

1

bit 0

bit 1

bit 2

0

bit 4

0

INDEX [3:0], 0h

ADDR [0:2]

DATA [7:0]

C is the transfer direction:

• C = 1: WRITE or RESET transaction

• C = 0: READ transaction

Main-ctrl-0, register values

Value

Function

Default

bit 0

PM SL - Power Mode Select

low power-mode (shutdown

(sleep) mode)

normal operation power mode

IRRX/SRDAT line enabled

enabled

shutdown

bit 1

RX OEN - Receiver Output Enable

IRRX/SRDAT line disable

(tristated)

disabled

bit 2

bit 3

bit 4

TLED EN - Transmitter LED Enable

not used

disabled

not used

disabled

APEN^*)

don’t acknowledge

acknowledge

*)

APEN - Acknowledge Pulse Enable, (optional)

This bit is used to enable the acknowledge pulse. When it is set to 1 and RX OEN is 1 (receiver output enabled) the IRRX/SRDAT line will

be set low for one clock cycle upon successful completion of every write command or special command with individual (non broadcast)

transceiver address. The internal signal from the receiver photo diode is disconnected when this bit is set to 1.

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Table B5: Register main-ctrl-1

Command structure:

C

1

0

bit 0

bit 1

bit 2

1

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

INDEX [3:0], 1h

ADDR [0:2]

DATA [7:0]

Main-ctrl-1, register values

DATA [7:0]

Function

00h

SIR (default)

MIR

01h

02h

FIR

Apple Talk^®(FIR functionality)

03h

05h

08h

VFIR - 16

Sharp IR^®(SIR functionality)

IrDA CIR

20h

Depending on the values of "ext_ctrl_7" and "ext_ctrl_8" check for correct main_ctrl_1. In case of an error, the transceiver will load 00h

into the main_ctrl_1 register and will not give an acknowledgement.

Table B6: Register main-ctrl-2

Command structure:

C

1

0

bit 0

bit 1

bit 2

1

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

INDEX [3:0], 1h

ADDR [0:2]

DATA [7:0]

Main-ctrl-2, DATA [7:0], bit 4 to bit 7

DATA bit bit bit bit bit bit bit bit

TXD -

IRED [mA]

le [mW/sr]

15°

(typ. on axis)

Link distance on axis

VFIR > 0.7 m,

FIR > 1 m (link distance

limited by receiver

sensitivity)

Recommended for

VFIR/FIR standard

[7:0]

7

6

5

4

3

2

1

0

8xh-

Fxh

1

x

512

140 (240)

7xh^*)

0

1

0

x

256

> 70 (120) *)

35 (60)

SIR >1 m

FIR > 0.7 m, VFIR > 0.5 m

SIR, More Ext.

FIR LP

6xh

128

SIR > 0.70 m

FIR > 0.50 m

VFIR > 0.30 m

Extended FIR

Low Power

5xh

0

1

0

1

64

16 (30)

SIR > 0.5 m

FIR > 0.30 m

VFIR > 0.30 m

VFIR Low Power/

FIR Low Power

4xh

3xh

0

1

0

1

0

1

(48)

32

8 (19)

40 (10)

(5)

SIR > 0.35 m

FIR > 0.20 m

VFIR > 0.20 m

SIR Low Power

2xh

1xh

0xh

0

1

0

1

0

16

8

SIR Low Power, min

without optical

windows

SIR > 0.15 m

FIR > 0.10 m

VFIR > 0.10 m

Close distance, e.g.

Docking station

x

0

*) Device is tested under this condition. Default setting is 7xh.

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TFDU8108

Vishay Semiconductors

IRED current I_f

[mA]

Intensity I_e

[mW/sr]

d[m] at E_e=

100 mW/m²

d[m] at E_e=

40 mW/m²

d[m] at E_e=

90 mW/m²

d[m] at E_e=

225 mW/m²

512

256

128

64

240

120

60

1.55

2.45

1.63

1.03

1.10

1.73

1.15

0.73

0.77

1.22

0.82

0.52

30

0.55

0.87

0.58

0.37

48

22.5

15

0.47

0.75

0.50

0.32

32

0.39

0.61

0.41

0.26

16

7.5

3.75

0.27

0.43

0.29

0.18

8

0.19

0.31

0.20

0.13

Note: Calculated expected range in dependence of IRED drive current for the case that the receiver sensitivity is not limiting the range, on

axis, for information only.

IRED current I_f

[mA]

Intensity I_e

[mW/sr]

d[m] at E_e=

100 mW/m²

d[m] at E_e=

40 mW/m²

d[m] at E_e=

90 mW/m²

d[m] at E_e=

225 mW/m²

512

256

128

64

140.0

70.0

35.0

17.5

13.1

8.8

1.18

1.87

1.25

0.79

0.15

0.23

1.16

0.10

0.59

0.94

0.62

0.39

0.42

0.66

0.44

0.28

48

0.36

0.57

0.38

0.24

32

0.30

0.47

0.31

0.20

16

4.4

0.21

0.33

0.22

0.14

8

2.2

0.15

0.23

0.16

0.10

Note: Calculated expected range in dependence of IRED drive current for the case that the receiver sensitivity is not limiting the range;

15° off-axis, for information only.

Table B7: Reading Extended Indexed Registers

Note: Read Data with Extended Index E_INDX is one of the Extended Indexed Registers. It must be addressed via a precursor of writing

all 1s into the normal index location, thus INDEX[3:0] = Fh. It is an 8 bit address value, which must be followed by 3 SCLK cycles plus a

start clock before reading the DATA value. As in the normal Read Transaction, the input signal, TXD, must be set one clock cycle on LOW

(master ready to receive) and then on HIGH for the next 3 SCLKs and continuing through the entire Response Phase. The corresponding

reaction of the RXD line and the 8 bit DATA value is then read out as depicted below, noting that the Read Data value comes after the 3

SCLK cycles.

Read Command structure:

0

1

bit 0

bit 5

bit 1

bit 2

bit 7

1

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

C

INDEX [3:0], Fh

ADDR [0:2]

E_INDEX [0:7]

Response:

bit 0

bit 1

bit 2

bit 3

bit 4

bit 6

DATA [0:7]

Extended Indexed Registers

Action

E_INDEX [7:0]

Register name

ext_ctrl_0

DATA [7:0]

in TFDU8108

Definition default

in the TFDU8108

Manufacture ID

00h

0Bh

Chip information

(Factory reserved)

Read Support, Device ID

01h

04h

ext_ctrl_1

ext_ctrl_4

C6h

23h

Device ID

Receiver Recovery Time

Power On Stabilization

100 µs to 500 µs

Receiver Stabilization

05h

ext_ctrl_5

30h

0

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Action

E_INDEX [7:0]

06h

Register name

ext_ctrl_6

DATA [7:0]

in TFDU8108

Definition default

in the TFDU8108

SCLK Max. Frequency

(4MHz)

4 MHz

Common Capabilities

03h

Low Power Mode and

Programmable Transmitter

Power supported

Supported Infrared Modes

07h

08h

F0h

ext_ctrl_7

ext_ctrl_8

2Fh

01h

0Ah

All listed in Receive Mode

Sharp IR

Mask ID: Released Ver. Set,

followed by Revision Letter

ext_ctrl_240

Chip information

(Factory reserved)

Invalid Commands Handling

Reset

Commands and register addresses, which cannot be Two ways to set the serial interface into a defined

encoded by the Serial Interface, are ignored by the state are available: The brute force method is to

internal logic as invalid data. Below the different types switch the power off and on and let the device recover

invalid command handling and the slave reaction is in the default state. The software method is to set the

shown.

IRTX/SWDAT line low for ≥ 30 clock cycles of the

clock line. If this line is detected as low for ≥ 30 clock

cycles the transceiver is set into the command start

state and all registers are set to the as default imple-

mented values.

Table B8: Invalid Commands Handling

Description

Invalid command in read mode

Invalid command in write mode

Master Command

Slave Reaction on RXD/SRDAT

Index [3:0] & C = 0

no reaction

Index [3:0] & C = 1

No acknowledgement generating

independent of the value of APEN

Valid command in invalid read mode

Valid command in invalid write mode

Index [3:0] & C = 0

Index [3:0] & C = 1

no reaction

No acknowledgement generating

independent of the value of APEN

Valid command in valid write mode and

invalid data

Index [3:0] & C = 1

No acknowledgement generating

independent of the value of APEN

Broadcast address in read mode

ADDR [2:0] = 111 & C = 0

no reaction

No reaction means that the slave does not start the respond phase.

C is the transfer direction:

• C = 1: WRITE or RESET transaction

• C = 0: READ transaction

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Appendix C

SCLK

Serial Interface Programming Guide

The serial interface port of TFDU8108 enables an

interface controller to communicate using a standard-

ized protocol, recall module ID and capability informa-

tion, and implement receiver bandwidth mode swit-

ching, LED power control, shutdown and some other

functions.

This interface requires three signal lines: a clock line

(SCLK) that is used for timing, and two unidirectional

lines multiplexed with the transmitter (TXD, write) and

receiver (RXD, read) signal lines.

TX

Tsetup > 10 ns

125 ns < Tclk

s

Thold > 10 ns

18496

Figure 22. Programming Sequence

Protocol Specifications

The serial interface protocol is a command-based

communication standard and allows for the communi-

cation between controller and transceiver by way of

serial programming sequences on the clock (SCLK),

transmit (TXD), and receive (RXD) lines. The SCLK

line is used as a clocking signal and the transmit/

receive lines are used to write/read data information.

The protocol requires all transceivers to implement

the write commands, but does not require the read-

portion of the protocol to be implemented (though all

transceivers must at least follow the various com-

mands, even if they perform no internal action as a

result). This serial interface follows but does not sup-

port all read/ write commands or extended com-

mands, supporting only the special commands and

basic write/read commands. Write commands to the

transceiver take place on the SCLK and TXD lines

and may use the RXD line for acknowledgment. A

command may be directed to a single transceiver on

the SCLK, TXD and RXD bus by specifying a unique

three-bit transceiver address, or a command may be

directed to all transceivers on the bus by way of a spe-

cial three-bit broadcast address code. The Vishay

VFIR transceiver TFDU8108 will respond to trans-

ceiver address 010 and the broadcast address 111

only; it ignores all other transceiver addresses.

Programming sequence formats supported are

• one-byte special commands

• two-byte write commands

• two-byte read commands

• three-byte read commands

One-byte special command sequences are reserved

for time-critical actions, while the two-byte write com-

mand is predominantly used to set basic transceiver

characteristics. More information can be found in the

IrDA document "Serial Interface for Transceiver Con-

trol, v 1.0a" on http://www.IrDA.org.

Serial Interface Timing Specifications

In general, serial interface programming sequences

are similar to any clocked-data protocol:

• there is a range of acceptable clock rates, mea-

sured from rising edge to rising edge

• there is a minimum data setup time before clock

rising edges

• there is a minimum data hold time after clock rising

edges

All commands have a common "header" or series of

leading bits, which take the form shown below.

Recommended programming timing:

• f

< 8 MHz (according to the Serial Interface

SCLK

first bit sent to transceiver

0/1 I0 I1

Sync. R/W Commands Index

Bits 0/1

last bit sent to transceiver.

A0 A1 A2 ... ...

Standard, quasi-static programming is possible)

0

1

I2

I3

• T

> 125 ns,

> 10 ns,

> 10 ns

SCLK

Transceiver

Address

setup

hold

The bits shown are placed on the TXD (DATA) line

and clocked into the transceiver using the rising edge

of the SCLK signal. Only the data bits are shown as it

is assumed that a clock is always present, and that

the transceiver samples the data on the rising edge of

each clock pulse.

The timing diagrams, see figure 22, show the setup

and hold time for the serial interface programming

sequences.

Note: as illustrated in the diagram above, the protocol uses "Little

Endian" ordering of bits, so that the LSB is sent first, and the MSB

is sent last for register addresses, transceiver addresses, and read/

write data bytes. The notation that follows presents all addresses

and data in LSB-to-MSB order (bits 0, 1, 2, 3, ... 7) unless otherwise

stated.

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One-byte Special Commands

Two-byte Write Commands

One-byte special commands are used for time-critical

transceiver commands, such as full transceiver reset.

A total of six special commands are possible, al-

though only one command is available on the

TFDU8108.

Two-byte write commands are used for setting the

contents of transceiver registers which control trans-

ceiver such as shutdown/enable, receiver mode, LED

power level, etc. The register space requires four reg-

ister address bits (INDEX), although three codes are

used for controlling the transceiver (see above). The

1111 escape code is for extended commands. The 3-

bit transceiver address (ADDR) is for selecting the

destination, e.g. 010 to TFDU8108 and 001 to

TFDU6108. The second byte is data field (DATA) for

setting the characteristics of the transceiver module,

e.g. SIR mode (00) or VFIR (05) when the register

address is 0001.

0

1

I0

I1

I2

I3

A0 A1 A2

0

Sync.

Bits

W

Special Command

Code

Transceiver

Address

Stop

Bits

Command

Programming Sequence

(Binary)

RESET

(Set all registers to default value)

011 1011 010 00

The basic two-byte write command is illustrated

below:

0

1

I0 I1 I2 I3 A0 A1 A2 A3 D0..07

0

Sync.

Bits

W

Commands

Index

Transceiver

Address

8 Data Stop

Bits Bits

Some important serial interface programming

sequences are shown in table C1.

Table C1: Serial interface programming sequences

Command

TFDU8108 Programming Sequence (Transceiver address: 010)

Common Ctrl

DATA

SYNC/C/INDEX/ADDR/1/DATA/STOP

main_ctrl_0

Normal (Enable all)

Shutdown

0Fh

00h

01 1 0000 010 1 11110000 00

01 1 0000 010 1 00000000 00

Receiver Mode

main_ctrl_1

DATA

SIR

MIR

00h

01h

01 1 1000 010 1 00000000 00

01 1 1000 010 1 10000000 00

01 1 1000 010 1 01000000 00

01 1 1000 010 1 11000000 00

01 1 1000 010 1 10100000 00

01 1 1000 010 1 00010000 00

FIR

02h

Apple Talk

VFIR

03h

05h

Sharp-IR

08h

LED Intensity

main_ctrl_2

DATA

8 mA

16 mA

32 mA

64 mA

128 mA

256 mA

512 mA

1xh

2xh

3xh

5xh

6xh

7xh

Fxh

01 1 0100 010 1 00001000 00

01 1 0100 010 1 00000100 00

01 1 0100 010 1 00001100 00

01 1 0100 010 1 00001010 00

01 1 0100 010 1 00000110 00

01 1 0100 010 1 00001110 00

01 1 0100 010 1 00001111 00

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Ozone Depleting Substances Policy Statement

It is the policy of Vishay Semiconductor GmbH to

1. Meet all present and future national and international statutory requirements.

2. Regularly and continuously improve the performance of our products, processes, distribution and operating

systems with respect to their impact on the health and safety of our employees and the public, as well as

their impact on the environment.

It is particular concern to control or eliminate releases of those substances into the atmosphere which are

known as ozone depleting substances (ODSs).

The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs

and forbid their use within the next ten years. Various national and international initiatives are pressing for an

earlier ban on these substances.

Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use

of ODSs listed in the following documents.

1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments

respectively

2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental

Protection Agency (EPA) in the USA

3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.

Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting

substances and do not contain such substances.

We reserve the right to make changes to improve technical design

and may do so without further notice.

Parameters can vary in different applications. All operating parameters must be validated for each customer

application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or

unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages,

and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated

with such unintended or unauthorized use.

Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany

Document Number 82558

Rev. 1.8, 16-Mar-07

www.vishay.com

383


型号：	TFDU8108-TT3
厂家：	VISHAY
描述：	Transceiver, Surface Mount 光纤
文件：	总25页 (文件大小：324K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TFDU8108-TT3 [VISHAY]

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