2225N1R0M402CT

更新时间:2024-10-29 23:13:20
品牌:WALSIN
描述:Halogen Free & RoHS Compliance

2225N1R0M402CT 概述

Halogen Free & RoHS Compliance

2225N1R0M402CT 数据手册

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Multilayer Ceramic Capacitors  
Approval Sheet  
MULTILAYER CERAMIC CAPACITORS  
1825, 2220 & 2225 Sizes  
NP0, X7R Dielectrics  
Halogen Free & RoHS Compliance  
*Contents in this sheet are subject to change without prior notice.  
Page 1 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  
Multilayer Ceramic Capacitors  
Approval Sheet  
1. HOW TO ORDER  
2220  
B
104  
K
500  
C
T
Size  
Dielectric  
Capacitance  
Tolerance  
Rated voltage  
Termination  
Packaging style  
Inch (mm) N=NP0  
Two significant  
F=±1%  
Two significant digits  
followed by no. of zeros.  
And R is in place of  
decimal point.  
C=Cu/Ni/Sn  
T=7” reeled  
B=X7R  
digits followed by G=±2%  
no. of zeros. And R J=±5%  
1825 (4563)  
2220 (5750)  
2225 (5763)  
is in place of  
K=±10%  
M=±20%  
decimal point.  
250= 25 VDC  
500= 50 VDC  
101= 100 VDC  
eg.:  
0R5=0.5pF  
1R0=1.0pF  
104=10x104  
=100nF  
251= 250 VDC  
501= 500 VDC  
631= 630 VDC  
102= 1000 VDC  
152= 1500 VDC  
202= 2000 VDC  
252= 2500 VDC  
302= 3000 VDC  
402= 4000 VDC  
2. EXTERNAL DIMENSIONS  
Size  
Inch (mm)  
L (mm)  
W (mm)  
6.30±0.40  
5.00±0.40  
6.30±0.40  
T(mm) (Symbol)  
MB min (mm)  
0.75±0.35  
0.85±0.35  
0.85±0.35  
L
1825 (4563)  
4.50±0.40  
5.70±0.40  
5.70±0.40  
T
2.00±0.20 (K)  
2.50±0.30 (M)  
2.80±0.30 (U)  
2220 (5750)  
2225 (5763)  
W
MB  
MB  
Fig. 1 The outline of MLCC  
# Reflow soldering only is recommended.  
3. GENERAL ELECTRICAL DATA  
Dielectric  
Size  
NP0  
X7R  
1825, 2220, 2225  
Capacitance*  
10pF to 0.1µF  
1000pF to 10uF  
Capacitance tolerance  
Rated voltage (WVDC)  
F (±1%), G (±2%), J (±5%), K (±10%)  
J (±5%), K (±10%), M (±20%)  
25V, 50V, 100V, 200V, 250V, 500V, 630V, 1000V, 1500V, 2000V, 2500V, 3000V, 4000V  
Cap<30pF: Q400+20C  
2.5%  
Tan δ*  
Cap30pF: Q1000  
Operating temperature  
Capacitance characteristic  
Termination  
-55 to +125°C  
±30ppm  
±15%  
Ni/Sn (lead-free termination)  
*Measured at 1.0±0.2Vrms, 1.0MHz±10% for Cap1000pF and 1.0±0.2Vrms, 1.0kHz±10% for Cap>1000pF, 25°C at ambient  
temperature for NP0.  
*Measured at 1.0±0.2Vrms, 1.0kHz±10% for C10µF; 0.5±0.2Vrms, 120Hz±20% for C>10µF, 30~70% related humidity, 25°C ambient  
temperature for X7R.  
** Preconditioning for Class II MLCC: Perform a heat treatment at 150±10°C for 1 hour, then leave in a mbient condition for 24±2 hours  
before measurement.  
Page 2 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  
Multilayer Ceramic Capacitors  
Approval Sheet  
4. CAPACITANCE RANGE  
4-1 NP0 Dielectric  
DIELECTRIC  
NP0  
1825  
2220  
SIZE  
2225  
RATED VOLTAGE  
(VDC)  
200  
250  
200  
250  
200  
250  
50 100  
500 630 1000 2000 3000 4000 50 100  
500 630 1000 2000 3000 4000 50 100  
500 630 1000 2000 3000 4000  
10pF (100)  
12pF (120)  
15pF (150)  
18pF (180)  
22pF (220)  
27pF (270)  
33pF (330)  
39pF (390)  
47pF (470)  
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
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K
K
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K
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K
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K
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M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
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K
K
K
K
K
K
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K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
M
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
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K
K
K
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K
K
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K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
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K
K
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M
M
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M
M
M
K
K
K
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M
M
K
K
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K
K
K
K
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K
K
K
K
K
K
K
K
K
M
M
M
M
M
M
M
M
M
M
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
M
M
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
M
M
M
M
M
K
K
K
K
K
K
K
K
K
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K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
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K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
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K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
M
M
M
M
M
M
M
M
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
56pF (560)  
68pF (680)  
82pF (820)  
100pF (101)  
120pF (121)  
150pF (151)  
180pF (181)  
220pF (221)  
270pF (271)  
330pF (331)  
390pF (391)  
470pF (471)  
560pF (561)  
680pF (681)  
820pF (821)  
1,000pF (102)  
1,200pF (122)  
1,500pF (152)  
1,800pF (182)  
2,200pF (222)  
2,700pF (272)  
3,300pF (332)  
3,900pF (392)  
4,700pF (472)  
5,600pF (562)  
6,800pF (682)  
8,200pF (822)  
0.010uF (103)  
0.012µF (123)  
0.015µF (153)  
0.018µF (183)  
0.022µF (223)  
0.027µF (273)  
0.033µF (333)  
0.039µF (393)  
0.047µF (473)  
0.056µF (563)  
0.068µF (683)  
0.082µF (823)  
0.1µF (104) M  
0.12µF (124)  
0.15µF (154)  
0.18µF (184)  
0.22µF (224)  
0.27µF (274)  
1. The letter in cell is expressed the symbol of product thickness.  
2. For more information about products with special capacitance or other data, please contact WTC local representative.  
Page 3 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  
Multilayer Ceramic Capacitors  
Approval Sheet  
4-2 X7R Dielectric  
DIELECTRIC  
SIZE  
X7R  
1825  
2220  
500 630 1000 1500 2000 2500 3000 4000  
RATED VOLTAGE  
200  
250  
50 100 200 250 500 630 1000 1500 2000 3000 4000 25 50 100  
(VDC)  
1,000pF (102) K  
1,200pF (122) K  
1,500pF (152) K  
1,800pF (182) K  
2,200pF (222) K  
2,700pF (272) K  
3,300pF (332) K  
3,900pF (392) K  
4,700pF (472) K  
5,600pF (562) K  
6,800pF (682) K  
8,200pF (822) K  
0.010µF (103) K  
0.012µF (123) K  
0.015µF (153) K  
0.018µF (183) K  
0.022µF (223) K  
0.027µF (273) K  
0.033µF (333) K  
0.039µF (393) K  
0.047µF (473) K  
0.056µF (563) K  
0.068µF (683) K  
0.082µF (823) K  
0.10µF (104) K  
0.12µF (124) K  
0.15µF (154) K  
0.18µF (184) K  
0.22µF (224) K  
0.27µF (274) K  
0.33µF (334) K  
0.39µF (394) K  
0.47µF (474) K  
0.56µF (564) K  
0.68µF (684) K  
0.82µF (824) K  
1.0µF (105) K  
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
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K
K
K
K
K
K
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
U
U
U
U
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
U
U
U
U
K
K
K
K
K
K
K
K
K
M
M
M
M
U
U
U
K
M
M
M
K
K
K
K
K
K
K
K
K
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K
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M
U
K
K
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K
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K
K
K
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K
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K
K
K
K
K
K
K
K
K
K
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K
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K
K
K
K
K
K
K
K
K
K
K
M
U
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
U
U
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
U
U
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
U
U
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
U
U
U
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
U
U
U
U
U
U
U
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
U
U
U
U
U
U
U
K
K
K
K
K
K
K
K
K
K
M
M
M
U
U
U
K
K
K
K
K
K
K
K
K
K
M
M
M
U
U
U
K
M
M
M
1.5µF (155) K  
2.2µF (225) K  
3.3µF (335) K  
4.7µF (475) K  
6.8µF (685)  
10µF (106)  
1. The letter in cell is expressed the symbol of product thickness.  
2. For more information about products with special capacitance or other data, please contact WTC local representative.  
Page 4 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  
Multilayer Ceramic Capacitors  
Approval Sheet  
DIELECTRIC  
SIZE  
X7R  
2225  
RATED VOLTAGE  
25  
50 100 200 250 500 630 1000 1500 2000 3000 4000  
(VDC)  
1,000pF (102)  
1,200pF (122)  
1,500pF (152)  
1,800pF (182)  
2,200pF (222)  
2,700pF (272)  
3,300pF (332)  
3,900pF (392)  
4,700pF (472)  
5,600pF (562)  
6,800pF (682)  
8,200pF (822)  
0.010µF (103)  
0.012µF (123)  
0.015µF (153)  
0.018µF (183)  
0.022µF (223)  
0.027µF (273)  
0.033µF (333)  
0.039µF (393)  
0.047µF (473)  
0.056µF (563)  
0.068µF (683)  
0.082µF (823)  
0.10µF (104)  
0.12µF (124)  
0.15µF (154)  
0.18µF (184)  
0.22µF (224)  
0.27µF (274)  
0.33µF (334)  
0.39µF (394)  
0.47µF (474)  
0.56µF (564)  
0.68µF (684)  
0.82µF (824)  
1.0µF (105)  
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
U
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
U
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
K
M
U
U
U
U
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
M
M
U
U
U
K
K
K
K
K
K
K
K
K
K
K
K
K
M
M
M
M
M
M
U
U
U
K
K
K
M
M
M
K
K
K
K
K
K
K
M
M
M
M
M
M
U
1.5µF (155)  
2.2µF (225)  
3.3µF (335)  
4.7µF (475)  
6.8µF (685)  
10µF (106)  
1. The letter in cell is expressed the symbol of product thickness.  
2. For more information about products with special capacitance or other data, please contact WTC local representative.  
5. PACKAGING STYLE AND QUANTITY  
Plastic tape  
Thickness/Symbol  
(mm)  
Size  
7” reel  
1000  
500  
13” reel  
2.00±0.20  
K
M
U
-
-
-
1825 (4563)  
2220 (5750)  
2225 (5763)  
2.50±0.30  
2.80±0.30  
500  
Unit: pieces  
Page 5 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  
Multilayer Ceramic Capacitors  
Approval Sheet  
6. RELIABILITY TEST CONDITIONS AND REQUIREMENTS  
No.  
1.  
Item  
Test Condition  
Requirements  
---  
* No remarkable defect.  
* Dimensions to conform to individual specification sheet.  
Visual and  
Mechanical  
Capacitance  
Class I: (NP0)  
* Shall not exceed the limits given in the detailed spec.  
2.  
3.  
C1000pF, 1.0±0.2Vrms1MHz±10%  
C>1000pF, 1.0±0.2Vrms1KHz±10%  
Class II: (X7R)  
C10µF, 1.0±0.2Vrms1KHz±10%  
C>10µF, 0.5±0.2Vrms120Hz±20%  
At 25°C ambient temperature.  
*To apply voltage (100V) 250%.  
*Duration: 1 to 5 sec.  
* Q/DF:  
Q/ D.F.  
NP0: Cap30pF, Q1000; Cap<30pF,Q400+20C.  
X7R: 2.5%.  
(Dissipation  
Factor)  
* No evidence of damage or flash over during test.  
Dielectric  
Strength  
4.  
*Charge & discharge current less than 50mA.  
*To apply voltage:  
200V ~ 300V  
500V ~ 999V  
1000V ~ 3000V  
4000V  
2 times V DC  
1.5 times V DC  
1.2 times V DC  
1.1 times V DC  
*Duration: 1 to 5 sec.  
*Charge & discharge current less than 50mA.  
UR100V: To apply voltage at UR for max. 120 sec.  
UR>100V: To apply voltage at UR (500V max.) for 60 sec.  
* 10Gor R•C100-F whichever is smaller.  
Insulation  
5.  
6.  
Resistance  
With no electrical load.  
* Capacitance change:  
NP0: Within ±30ppm/°C.  
X7R: Within ±15%.  
Temperature  
Coefficient  
T.C.  
NP0  
X7R  
Operating Temp  
-55~125°C at 25°C  
-55~125°C at 25°C  
Adhesive  
Strength of  
Termination  
* Pressurizing force10N  
* Test time: 10±1 sec.  
* No remarkable damage or removal of the terminations.  
7.  
* Vibration frequency: 10~55 Hz/min.  
* Total amplitude: 1.5mm  
* Test time: 6 hrs. (Two hrs each in three mutually perpendicular  
directions.)  
* No remarkable damage.  
* Cap change and Q/D.F.: To meet initial spec.  
8. Vibration  
Resistance  
* Solder temperature: 235±5°C  
* Dipping time: 2±0.5 sec.  
75% min. coverage of all metalized area.  
9. Solderability  
* The middle part of substrate shall be pressurized by means of the * No remarkable damage.  
Bending Test  
10.  
pressurizing rod at a rate of about 1 mm per second until the  
deflection becomes 1 mm and then the pressure shall be maintained  
for 5±1 sec.  
* Cap change: NP0: within ±5% or 0.5pF whichever is larger.  
X7R: within ±12.5%.  
(This capacitance change means the change of capacitance  
* Measurement to be made after keeping at room temp. for 24±2 hrs. under specified flexure of substrate from the capacitance  
measured before the test.)  
* Solder temperature: 260±5°C  
* Dipping time: 10±1 sec  
* Preheating: 120 to 150°C for 1 minute before imme rse the capacitor  
in a eutectic solder.  
* No remarkable damage.  
* Cap change:NP0: within ±2.5% or 0.25pF whichever is larger.  
X7R: within ±7.5%.  
Resistance to  
11.  
Soldering Heat  
* Q/D.F., I.R. and dielectric strength: To meet initial  
* Before initial measurement (Class II only): Perform 150+0/-10°C for requirements.  
1 hr and then set for 24±2 hrs at room temp.  
* 25% max. leaching on each edge.  
* Measurement to be made after keeping at room temp. for 24±2 hrs.  
* Conduct the five cycles according to the temperatures and time.  
* No remarkable damage.  
* Cap change:  
NP0: within ±2.5% or 0.25pF whichever is larger.  
X7R: within ±7.5%.  
12. Temperature  
Cycle  
Step  
Temp. (°C)  
Min. operating temp. +0/-3  
Room temp.  
Time (min.)  
30±3  
1
2
3
4
2~3  
* Q/D.F.:  
Max. operating temp. +3/-0  
Room temp.  
30±3  
2~3  
NP0: To meet initial requirements.  
X7R: 1.5 × Initial requirements.  
* I.R: To meet initial requirements.  
* Before initial measurement (Class II only): Perform 150+0/-10°C for  
1 hr and then set for 24±2 hrs at room temp.  
* Measurement to be made after keeping at room temp. for 24±2 hrs.  
Page 6 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  
Multilayer Ceramic Capacitors  
Approval Sheet  
No.  
Item  
Test Condition  
Requirements  
* Test temp.: 40±2°C  
* Humidity: 90~95% RH  
* Test time: 500+24/-0hrs.  
* No remarkable damage.  
* Cap change:  
NP0: within ±5% or 0.5pF whichever is larger.  
X7R: within ±12.5%.  
* Q/D.F.:  
13. Humidity  
(Damp Heat)  
Steady State  
*Before initial measurement (Class II only): To apply de-aging at  
150°C for 1hr then set for 24±2 hrs at room temp.  
* Cap. / DF(Q) / I.R. Measurement to be made after de-aging at  
150°C for 1hr then set for 24±2 hrs at room temp.  
NP0: More than 30pF Q350, 10pFC30pF, Q275+2.5C  
Less than 10pF Q200+10C.  
X7R: 2 × Initial requirements.  
* I.R.: 1Gor R•C50-F whichever is smaller.  
* No remarkable damage.  
14.  
*Test temp.40±2°C  
Humidity  
(Damp Heat)  
Load  
* Cap change:  
*Humidity90~95%RH  
NP0: ±7.5% or 0.75pF whichever is larger.  
X7R: within ±12.5%  
*Test time500+24/-0 hrs.  
*To apply voltage:  
* Q/D.F.:  
Rated voltage (MAX. 500V)  
NP0: More than 30pF,Q200;C<30pF, Q100+10/3C  
X7R: 2 × Initial requirements.  
* I.R.: 500Mor R•C5-F whichever is smaller.  
*Before initial measurement (Class II only): To apply de-aging at  
150°C for 1hr then set for 24±2 hrs at room temp.  
* Cap. / DF(Q) / I.R. Measurement to be made after de-aging at  
150°C for 1hr then set for 24±2 hrs at room temp.  
* Test temp.:125±3°C  
* No remarkable damage.  
15. High  
Temperature  
* To apply voltage:  
(1) Cap.1µF: 150% of rated voltage.  
(2) Ur250V: 200% of rated voltage.  
(3) 250V<Ur500V: 150% of rated voltage.  
(4) 500V<Ur3000V: 120% of rated voltage.  
(5) 4000V: 110% of rated voltage.  
* Cap change:  
NP0: within ±3% or 0.3pF whichever is larger.  
X7R: within ±12.5%.  
* Q/D.F.:  
NP0: More than 30pF Q350, 10pFC30pF, Q275+2.5C  
Less than 10pF Q200+10C  
X7R: 2 × Initial requirements.  
* I.R.: 1Gor R•C50-F whichever is smaller.  
Load  
(Endurance)  
*Test time: 1000+24/-0 hrs.  
*Before initial measurement (Class II only): To apply de-aging at  
150°C for 1hr then set for 24±2 hrs at room temp.  
* Cap. / DF(Q) / I.R. Measurement to be made after de-aging at 150°C  
for 1hr then set for 24±2 hrs at room temp.  
Page 7 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  
Multilayer Ceramic Capacitors  
Approval Sheet  
APPENDIXES  
Constructions  
No.  
1
2
3
4
5
Name  
NPO  
X7R  
Ceramic material  
Inner electrode  
CaZrO3 based  
BaTiO3 based  
Ni  
Cu  
Ni  
Inner layer  
Termination  
Middle layer  
Outer layer  
Sn  
Fig. 2 The construction of MLCC  
Tape & reel dimensions  
Fig. 3 The dimension of plastic tape  
Fig. 4 The dimension of reel  
2225  
Size  
1825  
2220  
Chip  
M(2.50)  
U(2.80)  
< 6.80  
M(2.50)  
U(2.80)  
< 5.80  
M(2.50)  
K(2.00)  
K(2.00)  
K(2.00)  
Thickness  
U(2.80)  
< 6.80  
< 5.30  
< 5.80  
< 6.50  
< 6.80  
< 6.50  
< 6.80  
A0  
B0  
T
< 5.30  
< 6.50  
< 6.50  
0.30  
+/-0.1  
0.30  
+/-0.1  
0.30  
+/-0.1  
0.30  
+/-0.1  
0.30  
+/-0.1  
0.30  
+/-0.1  
< 2.50  
< 3.50  
< 2.50  
< 3.50  
< 2.50  
< 3.50  
K0  
W
12.00  
+/-0.30  
12.00  
+/-0.30  
12.00  
+/-0.30  
12.00  
+/-0.30  
12.00  
+/-0.30  
12.00  
+/-0.30  
4.00  
+/-0.10  
4.00  
+/-0.10  
4.00  
+/-0.10  
4.00  
+/-0.10  
4.00  
+/-0.10  
4.00  
+/-0.10  
P0  
40.00  
40.00  
40.0  
40.0  
40.0  
40.0  
10xP0  
P1  
+/-0.20  
+/-0.20  
+/-0.20  
+/-0.20  
+/-0.20  
+/-0.20  
8.00  
+/-0.10  
8.00  
+/-0.10  
8.00  
+/-0.10  
8.00  
+/-0.10  
8.00  
+/-0.10  
8.00  
+/-0.10  
2.00  
+/-0.10  
2.00  
+/-0.10  
2.00  
+/-0.10  
2.00  
+/-0.10  
2.00  
+/-0.10  
2.00  
+/-0.10  
P2  
1.50  
1.50  
1.50  
1.50  
1.50  
1.50  
D0  
D1  
E
+0.1/-0  
+0.1/-0  
+0.1/-0  
+0.1/-0  
+0.1/-0  
+0.1/-0  
1.50  
+/-0.10  
1.75  
+/-0.10  
1.50  
+/-0.10  
1.75  
+/-0.10  
1.50  
+/-0.10  
1.75  
+/-0.10  
1.50  
+/-0.10  
1.75  
+/-0.10  
1.50  
+/-0.10  
1.75  
+/-0.10  
1.50  
+/-0.10  
1.75  
+/-0.10  
5.50  
+/-0.05  
5.50  
+/-0.05  
5.50  
+/-0.05  
5.50  
+/-0.05  
5.50  
+/-0.05  
5.50  
+/-0.05  
F
Size  
1825, 2220, 2225  
7”  
Reel size  
C
W1  
A
13.0+0.5/-0.2  
12.4+2.0/-0  
178.0±1.0  
60.0+1.0/-0  
N
Page 8 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  
Multilayer Ceramic Capacitors  
Approval Sheet  
APPLICATION NOTES  
Storage  
To prevent the damage of solderability of terminations, the following storage conditions are  
recommended:  
Indoors under 5 ~ 40°C and 20% ~ 70% RH.  
No harmful gases containing sulfuric acid, ammonia, hydrogen sulfide or chlorine.  
Packaging should not be opened until the capacitors are required for use. If opened, the pack should be  
re-sealed as soon as is practicable. Taped product should be stored out of direct sunlight, which might  
promote deterioration in tape or adhesion performance. The capacitors should be used within 6 months and  
checked the solderability before use.  
Handling  
Chip capacitors are dense, hard, brittle, and abrasive materials. They are liable to suffer mechanical  
damage, in the form of cracks or chips. Chip Capacitors should be handled with care to avoid contamination  
or damage. To use vacuum or plastic tweezers to pick up or plastic tweezers is recommended for manual  
placement. Tape and reeled packages are suitable for automatic pick and placement machine.  
Preheat  
In order to minimize the risk of thermal shock during soldering, a carefully controlled preheat is required.  
The rate of preheat should not exceed 4°C per secon d and the final preheat temperature should be within  
100°C of the soldering temperature for small chips such as 0402, 0603, 0805 and 1206, within 50°C of t he  
soldering temperature for bigger chips such as 1210, 1808, 1812, 1825, 2220 and 2225, etc.  
Soldering  
Use middy activated rosin RA and RMA fluxes do not use activated flux. The amount of solder in each  
solder joint should be controlled to prevent the damage of chip capacitors caused by the stress between  
solder, chips, and substrate.  
Hand soldering with temperature-controlled iron not exceeding 30 watts and diameter of tip less than 1.2  
mm is recommended, tip of iron should not contact the ceramic body directly, and the temperature of iron  
should be set to not more than 260°C.  
For bigger chips such as 1210, 1808, 1812, 2220 and 2225, etc. wave soldering and hand soldering are  
no recommended.  
Refer IPC/JEDEC J-STD-020D Method recommended soldering profiles:  
Reflow not sooner than 15 minutes and not longer than 4 hrs after removal from the  
temperature/humidity chamber, subject the sample to 3 cycle of the appropriate reflow conditions as defined  
as blow Table description.  
Profile Feature  
Preheat/Soak  
Temperature Min.(TS min  
Temperature Max.(TS max  
Pb-Free Assembly  
)
150°C  
200°C  
)
Time(tS) from (TS min to TS max  
)
60 to 120 seconds  
Ramp-up rate(TL to TP)  
3°C/second max.  
Liquidous temperature(TL)  
217°C  
Time(tL) maintained above TL  
60 to 150 seconds  
For user TP must not exceed the  
Classification temp 260°C  
For suppliers TP must equal or exceed the  
Classification temp 260°C  
Peak package body temperature(TP)  
Time(TP)* within 5°C of the specified  
classification temperature(TC)  
30* second  
Ramp-down rate (TP to TL)  
Time 25°C to peak temperature 260°C  
6°C/second max.  
8 minutes max.  
Page 9 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  
Multilayer Ceramic Capacitors  
Approval Sheet  
Lead-free: Soldering temperature = 235 to 260°C, de pending on product.  
Maximum temperature = Minimum temperature (235°C)+ T+ Tolerance for oven process and  
measurement(5 ~ 7°C)  
Time at peak temperature = 10sec, Dwell above 217°C = 90sec, Ramping rate = 3°C/sec (heating) and  
6°C/sec (heating).  
Classification Reflow Profiles  
Chip Size  
T  
0805,1206  
100 °C  
1210, 1808, 1812,  
1825, 2211, 2220, 2225  
50°C  
Solder  
Soldering  
Soldering  
Time (tP)  
Temp.(TC)  
Reflow  
235 – 260 °C  
< 15 sec.  
Note: For example, TC is 260°C and  
time P is 15 seconds.  
t
T  
For user: The peak temperature  
must not exceed 260°C. The time  
above 255°C must not exceed 15  
seconds.  
Cooling  
After soldering, cool the chips and the substrate gradually to room temperature. Natural cooling in air is  
recommended to minimize stress in the solder joint. A cooling rate not exceeding 4°C per second should be  
used when forced cooling is necessary.  
Cleaning  
All flux residues must be removed by using suitable electronic-grade vapor-cleaning solvents to  
eliminate contamination that could cause electrolytic surface corrosion. Good results can be obtained by  
using ultrasonic cleaning of the solvent. The choice of the proper system is depends upon many factors such  
as component mix, flux, and solder paste and assembly method. The ability of the cleaning system to remove  
flux residues and contamination from under the chips is very important.  
Page 10 of 10  
ASC_1825 2220 2225_025I_DS  
May. 2019  

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