5962-9679506MXA [WEDC]
Standard SRAM, 256KX16, 20ns, CMOS, FP-44;
| 型号： | 5962-9679506MXA |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Standard SRAM, 256KX16, 20ns, CMOS, FP-44 静态存储器 内存集成电路 |
| 文件： | 总25页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
B
Changes in accordance with NOR 5962-R159-97.
96-12-20
98-02-18
Raymond Monnin
Raymond Monnin
Change to Table I; ICCDR, device type column. Updated boilerplate.
ksr
C
D
Correct E2 dimension on package X from 3.85 min and 3.95 max to
.385 min and .395 max inches. Change the IOL test condition for VOL
from 8 mA to 6 mA in Table I. Updated boilerplate. ksr
04-10-27
09-01-21
Raymond Monnin
Robert Heber
Add device type 07, updated Table I for 07 device, corrected Figure
3, and added package Z. ksr
REV
SHEET
REV
D
D
D
D
D
D
D
21
D
D
22
D
D
23
D
D
24
D
SHEET
15
16
17
18
19
20
REV STATUS
OF SHEETS
REV
D
5
D
6
D
7
D
8
D
9
D
D
D
D
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SHEET
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2
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10
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PMIC N/A
PREPARED BY
Gary L. Gross
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
STANDARD
Jeff Bowling
MICROCIRCUIT
APPROVED BY
Michael A. Frye
DRAWING
THIS DRAWING IS
AVAILABLE
MICROCIRCUIT, MEMORY,
DIGITAL, 256K X 16 STATIC
RANDOM ACCESS MEMORY
(SRAM), MONOLITHIC SILICON
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
DRAWING APPROVAL DATE
96-05-17
REVISION LEVEL
SIZE
A
CAGE CODE
5962-96795
67268
D
SHEET
1 OF 24
DSCC FORM 2233
APR 97
5962-E129-09
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and
M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the
Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the
PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
-
96795
01
|
M
|
|
|
X
|
|
|
A
|
|
|
|
|
|
|
|
|
|
|
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and
are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number 1/
Circuit function
Data retention
Access time
01
02
03
04
05
06
07
256K X 16 CMOS SRAM
256K X 16 CMOS SRAM
256K X 16 CMOS SRAM
256K X 16 CMOS SRAM
256K X 16 CMOS SRAM
256K X 16 CMOS SRAM
256K X 16 CMOS SRAM
No
No
No
Yes
Yes
Yes
Yes
35 ns
25 ns
20 ns
35 ns
25 ns
20 ns
12 ns
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
M
Device requirements documentation
Vendor self-certification to the requirements for MIL-STD-883 compliant,
non-JAN class level B microcircuits in accordance with MIL-PRF-38535,
appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
X
Y
Z
See figure 1
See figure 1
See figure 1
44
44
44
flatpack package
CSOJ package
SO flatpack package
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
_______________
1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and
will also be listed in MIL-HDBK-103 (see 6.6.2 herein).
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
2
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 2/
Voltage on any input relative to VSS (devices 01 – 06) -----------------------
(device 07) -------------------------------
Storage temperature range ---------------------------------------------------------
Maximum power dissipation (PD)---------------------------------------------------
Lead temperature (soldering, 10 seconds) -------------------------------------
Thermal resistance, junction-to-case (ΘJC):
-0.5 V dc to +7.0 V dc
-0.5 V dc to +6.0 V dc
-65C to +150C
1.5 W
+260C
Case X ----------------------------------------------------------------------------------
Case Y ----------------------------------------------------------------------------------
Case Z ----------------------------------------------------------------------------------
Junction temperature (TJ) -----------------------------------------------------------
Output current --------------------------------------------------------------------------
5C/W
8C/W
7C/W
+150C 3/
20 mA
1.4 Recommended operating conditions.
Supply voltage range (VCC) ---------------------------------------------------------
Supply voltage (VSS) ------------------------------------------------------------------
Input high voltage range (VIH) ------------------------------------------------------
Input low voltage range (VIL) (devices 01 – 06)---------------------------------
(device 07) -------------------------------
4.5 V dc to 5.5 V dc
0 V
2.2 V dc to VCC + 0.5 V dc
-0.3 V dc to +0.8 V dc 4/
-0.5 V dc to +0.8 V dc 4/
-55C to +125C
Case operating temperature range (TC)------------------------------------------
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a
part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in
the solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
-
Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or from the Standardization
Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM Standard F1192-00
-
Standard Guide for the Measurement of Single Event Phenomena from
Heavy Ion Irradiation of Semiconductor Devices.
(Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr
Harbor Drive, West Conshohocken, PA 19428-2959; http://www.astm.org.)
______________
2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening
conditions in accordance with method 5004 of MIL-STD-883.
4/ VIL minimum = -3.0 V dc for pulse width less than 20 ns.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
3
DSCC FORM 2234
APR 97
ELECTRONICS INDUSTRIES ASSOCIATION (EIA)
JEDEC Standard EIA/JESD78 IC Latch-Up Test.
-
(Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA
22201; http://www.jedec.org.)
(Non-Government standards and other publications are normally available from the organizations that prepare or distribute
the documents. These documents also may be available in or through libraries or other informational services.)
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3.
3.2.4 Functional tests. Various functional tests used to test this device are contained in the appendix. If the test patterns
cannot be implemented due to test equipment limitations, alternate test patterns to accomplish the same results shall be
allowed. For device class M, alternate test patterns shall be maintained under document revision level control by the
manufacturer and shall be made available to the preparing or acquiring activity upon request. For device classes Q and V
alternate test patterns shall be under the control of the device manufacturer's Technology Review Board (TRB) in accordance
with MIL-PRF-38535 and shall be made available to the preparing or acquiring activity upon request.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full
case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table I.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required
in MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see
6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535
and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in
MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered
to this drawing.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
4
DSCC FORM 2234
APR 97
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2
herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain
the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 41 (see MIL-PRF-38535, appendix A).
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be
in accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in)
electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein.
b. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made
available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases,
and power dissipation, as applicable, in accordance with the intent specified in method 1015.
(1) Dynamic burn-in (method 1015 of MIL-STD-883, test condition D; for circuit, see 4.2.1b herein).
c. Interim and final electrical parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b. Interim and final electrical test parameters shall be as specified in table IIA herein.
c. Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for
groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Test
Symbol
Conditions
Group A
Subgroups
Device
type
Limits
Units
-55C TC +125C
4.5 V VCC 5.5 V
unless otherwise specified
Min
Max
300
95
Operating supply
current 1/
ICC1
1, 2, 3
1, 2, 3
01-06
07
mA
mA
all I/O's = 0 mA, WE , CE = VIL
VCC standby
current (TTL)
ICC2
01-06
07
60
25
CE = VIH, VIN < VIL
VIN > VIH
VCC standby
current (CMOS)
ICC3
1, 2, 3
1, 2, 3
01-03
25
mA
CE > VCC-0.2 V
IN > VCC-0.2 V or VIN < 0.2 V
V
04-06
07
10
15
Data retention
voltage
VDR
2.0
V
CE > VCC-0.2 V,
VIN > VCC-0.2 V or VIN < 0.2 V
04-07
04 - 06
07
Data retention
current
ICCDR
VCC = 2.0 V
2.0
12
mA
Input leakage
current (low)
IILK
VIN = 0.0 V to VCC
VI/O = 0.0 V to VCC
IOH = -4.0 mA
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
All
-10
-10
+10
+10
μA
μA
V
Output leakage
current (high)
IOLK
VOH
VOL
All
All
High level output
voltage
2.4
Low level output
voltage
IOL = 6.0 mA
01-06
07
V
0.4
0.4
I
OL = 8.0 mA
Input capacitance
CIN
4
All
12
14
pF
pF
V
IN = 0 V, TA = 25C,
f = 1.0 MHz, see 4.4.1e
Input/output
capacitance
CI/O
4
All
All
V
OUT = 0 V, TA = 25C,
f = 1.0 MHz, see 4.4.1e
Functional tests
See 4.4.1c
7, 8A, 8B
See footnotes at end of table.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
Group A
Subgroups
Device
type
Limits
Units
ns
-55C TC +125C
4.5 V VCC 5.5 V
unless otherwise specified
Min
35
Max
Read cycle time
tAVAV
See figures 4 and 5 as applicable 9, 10, 11
2/ 3/
01,04
02,05
25
03,06
07
20
12
Address access time tAVQV
9, 10, 11
01,04
35
ns
02,05
25
03,06
07
20
12
Chip enable access
time
tELQV
9, 10, 11
01,04
35
ns
02,05
25
03,06
07
20
12
Chip enable to
output in low Z
tELQX
9, 10, 11
9, 10, 11
01-06
5
3
ns
ns
07
Chip disable to
output in high Z
tEHQZ
01,04,
07
10
02,05
0
8
7
03,06
Output hold from
address change
tAVQX
9, 10, 11
01,02,
5
ns
04,05
03,06
4
3
07
See footnotes at end of table.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
Group A
Subgroups
Device
type
Limits
Units
-55C TC +125C
4.5 V VCC 5.5 V
unless otherwise specified
Min
Max
15
Output enable to
output valid
tOLQV
See figures 4 and 5 as
applicable 2/ 3/
01,04
02,05
03,06
07
9, 10, 11
ns
12
10
6
Output enable to
output in low Z 4/
tOLQX
tOHQZ
9, 10, 11
9, 10, 11
All
0
0
ns
ns
Output disable to
output in high Z 4/
01,04,
07
10
02,05
03,06
8
7
01,04,
02,05
03,06
07
15
12
10
6
tUBLQV
tLBLQV
LB , UB access time
9, 10, 11
ns
tUBLQX
ALL
0
0
LB , UB enable to low
Z output
ns
ns
9, 10, 11
9, 10, 11
tLBLQXV
01,04,
07
10
tUBHQZ
tLBHQZ
LB , UB disable to
high Z output
02,05
03,06
01,04
02,05
03,06
07
8
7
Write cycle time
See figures 4 and 5 as
applicable 2/
35
25
20
12
20
17
15
10
tAVAV
9, 10, 11
9, 10, 11
ns
ns
Chip enable to end of
write
01,04
02,05
03,06
07
tELWH
tELEH
Address setup time
tAVWL
tAVEL
tAVUBL
ALL
0
ns
ns
9, 10, 11
9, 10, 11
Address valid to end of
write
01,04
02,05
03,06
07
20
17
15
10
tAVWH
tAVEH
tAVUBH
See footnotes at end of table.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Conditions
Group A
Subgroups
Device
type
Limits
Units
-55C TC +125C
4.5 V VCC 5.5 V
unless otherwise specified
Min
20
Max
Write pulse width
See figures 4 and 5 as
applicable 2/
01,04
02,05
03,06
07
tWLWH
tWLEH
9, 10, 11
ns
17
15
10
0
Write recovery time
9, 10, 11
9, 10, 11
All
ns
ns
tWHAX
tEHAX
Data hold time in high
Z
tWHDX
tEHDX
All
0
Write to output in high
Z
tWLQZ
01-07
0
8
ns
ns
9, 10, 11
9, 10, 11
Data to write time
01,04
02,05
03,06
07
15
12
10
7
tDVWH
tDVEH
Output active from end
of write
01,04
02,05
03,06
07
15
12
10
3
tWHQX
9, 10, 11
9, 10, 11
ns
ns
LB, UB valid to end of
write
01,04
02,05
03,06
07
20
18
16
10
tAVAV
tLBLLBH
tUBLUBH
Operation recovery
time
9, 10, 11
9, 10, 11
04-07
ns
ns
tR
Chip disable to data
retention time
See figures 4 and 5 as
applicable 2/
tCDR
All
0
CE > VCC-0.2 V,
VIN > VCC-0.2 v or VIN < 0.2 V
1/ ICC is dependent on output loading and cycle rate. The specified values apply with output(s) unloaded.
2/ AC measurements assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 V to 3.0 V and output loading of 30 pF load capacitance, unless otherwise specified. Output timing reference is 1.5
V. See figure 4.
3/ For read cycles, WE is high for the entire cycle.
4/ Parameter, if not tested, shall be guaranteed to the limits specified in table I.
5/ Measured +500 mV from steady-state output voltage. Load capacitance is 5.0 pF.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
9
DSCC FORM 2234
APR 97
Case X (see notes)
Symbol
Millimeters
Min
Inches
Symbol
Max
Millimeters
Inches
Max
2.92
0.48
0.18
28.70
Min
---
Min
9.78
Max
Min
Max
.395
A
b
---
0.38
0.08
---
.115
.019
E2
e
10.03
.385
.015
.003
---
1.27 Typ.
25.40 Ref.
.050 Typ.
c
.007
H
Q
S
1.000 Ref.
D
D2
E
1.130
0.81
0.38
0.97
1.14
.032
.015
.038
.045
26.67 Ref.
1.050 Ref.
.505 .515
12.83
13.08
N
44
NOTES:
1. The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and inch-pound
units, the inch-pound units shall take precedence. Metric equivalents are for general information only.
2. Index area: a notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the
area shown. The manufacturer's identification shall not be used as pin one identification mark.
FIGURE 1. Case outlines.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
10
DSCC FORM 2234
APR 97
Case Y (see notes)
Symbol
Millimeters
Inches
Symbol
Millimeters
Inches
Min
Max
4.44
Min
---
Max
.175
Min
---
Max
Min
---
Max
.445
A
A2
b
---
E
E1
e
11.30
1.52 Ref.
.060 Ref.
10.16 Nom.
1.27 Bsc.
0.76 1.02
.400 Nom.
.050 Bsc.
0.41
0.51
0.16
0.19
D
28.45
28.70
1.120
1.130
S
.030
.040
D1
26.67 Ref.
1.050 Ref.
N
44
NOTES:
1. The U.S. Government preferred system of measurement is the metric SI system. However, since this item was
originally designed using inch-pound units of measurement, in the event of conflict between the metric and inch-
pound units, the inch-pound units shall take precedence. Metric equivalents are for general information only.
2. Index area: a notch or a pin one identification mark shall be located adjacent to pin one and shall be located within
the area shown. The manufacturer's identification shall not be used as pin one identification mark.
FIGURE 1. Case outlines - continued.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
11
DSCC FORM 2234
APR 97
Case Z (see notes)
Millimeters
Millimeters
0.80 BSC
Symbol
Symbol
Min
2.986
0.300
0.150
0.050
18.215
16.60
9.96
Max
3.842
0.400
0.250
---
Min
Max
A
b
E2
e
5.280
5.680
b2
c
f
0.406
0.597
L
0.839 NOM (ref)
11.735 11.938
D
18.615
17.00
10.36
M
N
D1
E
44
NOTES:
1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one and shall be located within
the area shown. The manufacturer's identification shall not be used as pin one identification mark.
FIGURE 1. Case outlines - continued.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
12
DSCC FORM 2234
APR 97
Device type
Case outline
All
X, Y, Z
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
2
3
4
5
A0
A1
A2
A3
A4
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
A10
A11
A12
A13
A14
NC
CE
6
7
8
9
10
11
12
13
14
15
16
DQ9
DQ10
DQ11
DQ12
VCC
VSS
DQ13
DQ14
DQ15
DQ16
DQ1
DQ2
DQ3
DQ4
VCC
VSS
DQ5
DQ6
DQ7
DQ8
LB
39
40
41
42
43
44
17
18
19
20
21
22
WE
A5
A6
A7
A8
A9
UB
OE
A15
A16
A17
FIGURE 2. Terminal connections.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-96795
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
13
DSCC FORM 2234
APR 97
MODE
I/O PIN
DQ1-DQ8
SUPPLY
CURRENT
CE
H
WE
X
OE
X
LB
X
UB
X
DQ9-DQ16
HIGH-Z
NOT
HIGH-Z
ICC2,ICC3
SELECT
L
L
H
X
H
X
X
H
L
X
H
H
L
OUTPUT
DISABLE
HIGH-Z
HIGH-Z
ICC
DOUT
HIGH-Z
DOUT
HIGH-Z
DOUT
DOUT
HIGH-Z
DIN
H
L
L
L
H
L
L
READ
ICC
L
L
H
L
DIN
H
L
HIGH-Z
DIN
X
WRITE
ICC
L
DIN
H = Logic "1" state
L = Logic "0" state
X = Don't care
FIGURE 3. Truth table.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
D
14
DSCC FORM 2234
APR 97
NOTES:
1.
2.
3.
Use these output load circuits or equivalent for testing.
Including scope and jig.
Minimum of 5 pF for t
, t
, and t
.
EHQZ WLQZ
OHQZ
AC test conditions
Input pulse levels
Input rise, fall times
VSS to 3.0 V
5 ns
Input timing reference levels
Output reference levels
1.5 V
1.5 V
FIGURE 4. Output load circuits.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
15
DSCC FORM 2234
APR 97
FIGURE 5. Timing waveforms.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-96795
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
16
DSCC FORM 2234
APR 97
FIGURE 5. Timing waveforms - continued.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
17
DSCC FORM 2234
APR 97
FIGURE 5. Timing waveforms - continued.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
18
DSCC FORM 2234
APR 97
TABLE IIA. Electrical test requirements. 1/ 2/ 3/ 4/ 5/ 6/ 7/
Line
no.
Test
requirements
Subgroups (per
method 5005,
table I)
Subgroups
(per MIL-PRF-38535,
table III)
Device
class
M
Device
class
Q
Device
class
V
1
2
Interim electrical
parameters
(see 4.2)
1,7,9
Static burn-in I
method 1015
Not
required
Not
required
Required
3
4
Same as line 1
1*,7* Δ
Dynamic burn-in
(method 1015)
Required
Required
Required
5
6
Same as line 1
1*,7* Δ
Final electrical
parameters
1*,2,3,7*,8A,8B,
9,10,11
1*,2,3,7*,
8A,8B,9,10,
11
1*,2,3,7*,
8A,8B,9,10,
11
7
8
Group A test
requirements
1,2,3,4**,7,8A,8
B,9,10,11
1,2,3,4**,7,
8A,8B,9,10,
11
1,2,3,4**,7,
8A,8B,9,10,
11
Group C end-point
electrical
parameters
2,3,7,
8A,8B
1,2,3,7,
8A,8B
1,2,3,7,
8A,8B,9,10,
11 Δ
9
Group D end-point
electrical
2,3,
8A,8B
2,3,
8A,8B
2,3,
8A,8B
parameters
10
Group E end-point
electrical
1,7,9
1,7,9
1,7,9
parameters
1/ Blank spaces indicate tests are not applicable.
2/ Any or all subgroups may be combined when using high-speed testers.
3/ Subgroups 7, 8A, and 8B functional tests shall verify the truth table.
4/ * indicates PDA applies to subgroup 1 and 7.
5/ ** see 4.4.1e.
6/ Δ indicates delta limit (see table IIB) shall be required where specified, and the delta values shall be
computed with reference to the previous interim electrical parameters (see line 1).
7/ See 4.4.1d.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
19
DSCC FORM 2234
APR 97
TABLE IIB. Delta limits at +25C.
Parameter 1/
ICC3 standby
All device types
+10% of specified
value in table I
IILK, IOLK
+10% of specified
value in table I
1/ The above parameter shall be recorded
before and after the required burn-in and
life tests to determine the delta.
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a. Tests shall be as specified in table IIA herein.
b. Subgroups 5 and 6 of table I of method 5005 of MIL-STD-883 shall be omitted.
c. For device class M, subgroups 7, 8A, and 8B tests shall be sufficient to verify the truth table. For device classes Q and
V, subgroups 7, 8A, and 8B shall include verifying the functionality of the device.
d. O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may
affect the performance of the device. For device class M, procedures and circuits shall be maintained under document
revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity
upon request. For device classes Q and V, the procedures and circuits shall be under the control of the device
manufacturer's TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or
acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be
considered destructive. Information contained in JEDEC Standard EIA/JESD78 may be used for reference.
e. Subgroup 4 (C and C
IN OUT
measurements) shall be measured only for initial qualification and after any process or
design changes which may affect input or output capacitance. Capacitance shall be measured between the
designated terminal and GND at a frequency of 1 MHz. Sample size is 15 devices with no failures, and all input and
output terminals tested.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a. Test condition D. The test circuit shall be maintained by the manufacturer under document revision level control and
shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs,
outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-
STD-883.
b. TA = +125ºC, minimum.
c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-
STD-883.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
20
DSCC FORM 2234
APR 97
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness
assured (see 3.5 herein).
a. End-point electrical parameters shall be as specified in table IIA herein.
b. For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All
device classes must meet the postirradiation end-point electrical parameter limits as defined in Table I at
TA = +25ºC ±5ºC, after exposure, to the subgroups specified in table IIA herein.
c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied.
4.5 Delta measurements for device class V. Delta measurements, as specified in table IIA, shall be made and recorded
before and after the required burn-in screens and steady-state life tests to determine delta compliance. The electrical
parameters to be measured, with associated delta limits are listed in table IIB. The device manufacturer may, at his option,
either perform delta measurements or within 24 hours after burn-in perform final electrical parameter tests, subgroups 1, 7,
and 9.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device
classes Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor
prepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA , Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331.
6.5.1 Timing limits. The table of timing values shows either a minimum or a maximum limit for each parameter. Input
requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the
system must supply at least that much time (even though most devices do not require it). On the other hand, responses from
the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never
provides data later than that time.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
21
DSCC FORM 2234
APR 97
6.5.2 Waveforms.
Waveform
symbol
Input
Output
MUST BE
WILL BE
VALID
VALID
CHANGE FROM
H TO L
WILL CHANGE
FROM
H TO L
CHANGE FROM
L TO H
WILL CHANGE
FROM
L TO H
DON'T CARE
ANY CHANGE
PERMITTED
CHANGING
STATE
UNKNOWN
HIGH
IMPEDANCE
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
22
DSCC FORM 2234
APR 97
APPENDIX A
Appendix A forms a part of SMD 5962-96795
FUNCTIONAL ALGORITHMS
A.1 SCOPE
A.1.1 Scope. Functional algorithms are test patterns which define the exact sequence of events used to verify proper
operation of a random access memory (RAM). Each algorithm serves a specific purpose for the testing of the device. It is
understood that all manufacturers do not have the same test equipment; therefore, it becomes the responsibility of each
manufacturer to guarantee that the test patterns described herein are followed as closely as possible, or equivalent patterns be
used that serve the same purpose. Each manufacturer should demonstrate that this condition will be met. Algorithms shall be
applied to the device in a topologically pure fashion. This appendix is a mandatory part of the specification. The information
contained herein is intended for compliance.
A.2 APPLICABLE DOCUMENTS. This section is not applicable to this appendix.
A.3 ALGORITHMS
A.3.1 Algorithm A (pattern 1).
A.3.1.1 Checkerboard, checkerboard-bar.
Step 1. Load memory with a checkerboard data pattern by incrementing from location 0 to maximum.
Step 2. Read memory, verifying the output checkerboard pattern by incrementing from location 0 to maximum.
Step 3. Load memory with a checkerboard-bar pattern by incrementing from location 0 to maximum.
Step 4. Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to maximum.
A.3.2 Algorithm B (pattern 2).
A.3.2.1 March.
Step 1. Load memory with background data, incrementing from minimum to maximum address locations (all "0's").
Step 2. Read data in location 0.
Step 3. Write complement data to location 0.
Step 4. Read complement data in location 0.
Step 5. Repeat steps 2 through 4 incrementing X-fast sequentially for each location in the array.
Step 6. Read complement data in maximum address location.
Step 7. Write data to maximum address location.
Step 8. Read data in maximum address location.
Step 9. Repeat steps 6 through 8 decrementing X-fast sequentially for each location in the array.
Step 10. Read data in location 0.
Step 11. Write complement data to location 0.
Step 12. Read complement data in location 0.
Step 13. Repeat steps 10 through 12 decrementing X-fast sequentially for each location in the array.
Step 14. Read complement data in maximum address location.
Step 15. Write data to maximum address location.
Step 16. Read data in maximum address location.
Step 17. Repeat steps 14 through 16 incrementing X-fast sequentially for each location in the array.
Step 18. Read background data from memory, decrementing X-fast from maximum to minimum address locations.
A.3.3 Algorithm C (pattern 3).
A.3.3.1 XY March.
Step 1. Load memory with background data, incrementing from minimum to maximum address locations (all "0's").
Step 2. Read data in location 0.
Step 3. Write complement data to location 0.
Step 4. Read complement data in location 0.
Step 5. Repeat steps 2 through 4 incrementing Y-fast sequentially for each location in the array.
Step 6. Read complement data in maximum address location.
Step 7. Write data to maximum address location.
Step 8. Read data in maximum address location.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
23
DSCC FORM 2234
APR 97
APPENDIX A – Continued.
Appendix A forms a part of SMD 5962-96795
Step 9. Repeat steps 6 through 8 decrementing X-fast sequentially for each location in the array.
Step 10. Read data in location 0.
Step 11. Write complement data to location 0.
Step 12. Read complement data in location 0.
Step 13. Repeat steps 10 through 12 decrementing Y-fast sequentially for each location in the array.
Step 14. Read complement data in maximum address location.
Step 15. Write data to maximum address location.
Step 16. Read data in maximum address location.
Step 17. Repeat steps 14 through 16 incrementing X-fast sequentially for each location in the array.
Step 18. Read background data from memory, decrementing Y-fast from maximum to minimum address locations.
A.3.4 Algorithm D (pattern 4).
A.3.4.1 CEDES - CE deselect checkerboard, checkerboard-bar.
Step 1. Load memory with a checkerboard data pattern by incrementing from location 0 to maximum.
Step 2. Deselect device, attempt to load memory with checkerboard-bar data pattern by incrementing from location 0 to
maximum.
Step 3. Read memory, verifying the output checkerboard pattern by incrementing from location 0 to maximum.
Step 4. Load memory with a checkerboard-bar pattern by incrementing from location 0 to maximum.
Step 5. Deselect device, attempt to load memory with checkerboard data pattern by incrementing from location 0 to
maximum.
Step 6. Read memory, verifying the output checkerboard-bar pattern by incrementing from location 0 to maximum.
SIZE
STANDARD
5962-96795
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
D
SHEET
24
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 09-01-21
Approved sources of supply for SMD 5962-96795 are listed below for immediate acquisition information only and
shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be
revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a
certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded
by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current
sources of supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard microcircuit
drawing PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
54230
54230
54230
54230
54230
54230
54230
54230
54230
54230
54230
54230
6S055
6S055
5962-9679501MXA
5962-9679501MYA
5962-9679502MXA
5962-9679502MYA
5962-9679503MXA
5962-9679503MYA
5962-9679504MXA
5962-9679504MYA
5962-9679505MXA
5962-9679505MYA
5962-9679506MXA
5962-9679506MYA
5962-9679507MZA
5962-9679507MZC
EDI816256CA35F44B
EDI816256CA35N44B
EDI816256CA25F44B
EDI816256CA25N44B
EDI816256CA20F44B
EDI816256CA20N44B
EDI816256LPA35F44B
EDI816256LPA35N44B
EDI816256LPA25F44B
EDI816256LPA25N44B
EDI816256LPA20F44B
EDI816256LPA20N44B
DPA71041D02A
DPA71041D02C
1/ The lead finish shown for each PIN representing a hermetic package
is the most readily available from the manufacturer listed for that part.
If the desired lead finish is not listed contact the vendor to determine
its availability.
2/ Caution. Do not use this number for item acquisition. Items acquired
to this number may not satisfy the performance requirements of this drawing.
Vendor CAGE
number
Vendor name
and address
54230
White Electronic Designs Inc.
3601 E University Drive
Phoenix, AZ 85034
6S055
DPA Components International
2251 Ward Avenue
Simi Valley, CA 93065
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
相关型号：
5962-9679601HYX
EEPROM, 128KX8, 300ns, Parallel, CMOS, CDIP32, 0.600 INCH, HERMETIC SEALED, SINGLE CAVITY, SIDE BRAZED, CERAMIC, DIP-32
MERCURY
5962-9679602HXX
EEPROM, 128KX8, 250ns, Parallel, CMOS, CDSO32, 0.400 INCH, HERMETIC SEALED, CERAMIC, SOJ-32
MERCURY
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