EDI7F292MC100BNC [WEDC]
Flash Module, 4MX8, 100ns, SIMM-80;
| 型号： | EDI7F292MC100BNC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Flash Module, 4MX8, 100ns, SIMM-80 |
| 文件： | 总33页 (文件大小：740K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI7F292MC
EDI7F492MC
PRELIMINARY*
White Electronic Designs
4MB/8MB (2x2Mx8 / 4x2Mx8) Flash Module 5.0V, Boot-Only
Sector Erase Flash Memory
• 100 mA typical active read current
ARCHITECHTURE
• 120 mA typical program/erase current
FEATURES
Enhanced power management for standby mode
5.0 Volt ± 10% fir read and write operations
• Minimizes system level power requirements
Compatible with JEDEC-standards
• <1 μA typical standby current
• Standard access time from standby mode
Hardware RESET# pin
• Pinout and software compatible with single-power
supply Flash
• Resets internal state machine to the read mode
• Superior inadvertent write protection
80 SIMM (JEDEC)
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Minimum 100,000 write/erase cycles guaranteed
High performance
DESCRIPTION
• 70 ns maximum access time
Sector erase architecture
The EDI7F292/492MC is a 32/64 Mbit, 5.0 Volt-only
Flash memory organized as 2 Megabytes of 8 bits each.
The 2Mbytes of data is divided into 32 sectors of 64
Kbytes for flexible erase capability. The 8 bits of data
appear on DQ0–DQ7. The EDI7F292/492MC is offered
in 80 Pin SIMM packages. This device is designed to be
programmed in-system with the standard system 5.0 Volt
VCC supply. 12.0 Volt VPP is not required for program or
erase operations. The device can also be reprogrammed
in standard EPROM programmers.
• Uniform sectors of 64 Kbytes each
• Any combination of sectors can be erased. Also
supports full chip erase
Group sector protection
• Hardware method that disables any combination
of sector groups from write or erase operations
(a sector group consists of 4 adjacent sectors of
64Kbytes each)
The standard EDI7F292/492MC offers access times of 100
ns, and 120 ns, allowing high-speed microprocessors to
operate without wait states. To eliminate bus contention,
the device has separate chip enable 4 CS#, write enable
WE#, and output enable OE# controls.
Embedded Erase Algorithms
• Automatically pre-programs and erases the chip
or any sector
Embedded Program Algorithms
• Automatically programs and verifies data at
specified address
The EDI7F292/492MC is entirely command set compatible
with the JEDEC single-power supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls
the erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from 12.0 Volt Flash or
EPROM devices.
Data# Polling and Toggle Bit feature for detection
of program or erase cycle completion
Ready/Busy# output (RY/BY#)
• Hardware method for detection of program or
erase cycle completion
Erase Suspend/Resume
• Supports reading or programming data to a
sector not being erased
The EDI7F292/492MC is programmed by executing
the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal
algorithm that automatically times the program pulse widths
and verifies proper cell margin. Erase is accomplished by
Low power consumption (EDI7292MC)
• 50 mA typical active read current
• 60 mA typical program/erase current
Low power consumption (EDI7492MC)
January 2006
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
executing the erase command sequence. This will invoke
the Embedded Erase Algorithm which is an internal
algorithm that automatically preprograms the array if it
is not already programmed before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
using the EPROM programming mechanism of hot electron
injection.
FLEXIBLE SECTOR-ERASE
Thirty two 64 Kbyte sectors
Eight sector groups each of which consists of 4
adjacent sectors in the following pattern: sectors 0-
3, 4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and
reprogrammed without affecting the data contents of
other sectors. A sector is typically erased and verified
within one second. The EDI7F292/492MC is erased when
shipped .
Individual-sector or multiple-sector erase capability
Sector group protection is user-definable
The EDI7F292/492MC device also features hardware
sector group protection. This feature will disable both
program and erase operations in any combination of
eight sector groups of memory. A sector group consists
of four adjacent sectors grouped in the following pattern:
sectors 0–3, 4–7, 8–11, 12–15, 16–19, 20–23, 24–27,
and 28–31.
SA31
SA30
SA29
SA28
1FFFFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
1FFFFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh
000000h
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
Sector
Group
7
WEDC has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from, or program data to, a sector that
was not being erased. Thus, true background erase can
be achieved.
32 Sectors Total
The device features single 5.0 Volt power supply operation
for both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations. A low VCC detector automatically inhibits write
operations during power transitions. The end of program
or erase is detected by the RY/BY# pin, Data# polling
of DQ7, or by the Toggle Bit I (DQ6). Once the end of a
program or erase cycle has been completed, the device
automatically resets to the read mode.
The EDI7F292/492MC also has a hardware RESET# pin.
When this pin is driven low, execution of any Embedded
Program Algorithm or Embedded Erase Algorithm will be
terminated. The internal state machine will then be reset
into the read mode. The RESET# pin may be tied to the
system reset circuitry. Therefore, if a system reset occurs
during the Embedded Program Algorithm or Embedded
Erase Algorithm, the device will be automatically
reset to the read mode. This will enable the system’s
microprocessor to read the boot-up firmware from the
Flash memory.
SA3
SA2
SA1
SA0
64 Kbyte
64 Kbyte
64 Kbyte
64 Kbyte
Sector
Group
0
The EDI7F292/492MC memory electrically erases all
bits within a sector simultaneously via Fowler-Nordheim
tunneling. The bytes are programmed one byte at a time
January 2006
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
PRODUCT SELECTOR GUIDE
Family Part No.
Symbol
Symbol
V
CC= 5.0 Volt ± 5%
Ordering Park No.
VCC= 5.0 Volt ± 10%
-100
100
100
-120
120
120
50
Max Access Time (ns)
CS# Access (ns)
OE# Access (ns)
PIN CONFIGURATIONS
FIG. 1
Pin
#
Pin
Name
Pin
#
Pin
Name
Pin
#
Pin
Name
Pin
#
Pin
Name
Block Diagrams
1
VSS
VCC
NC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
CS#
CS#
CS#
CS#
VSS
NC
41
42
43
44
45
461
47
48
49
50
51
52
53
54
55
56
57
58
59
60
A11
A10
A9
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
NC
NC
EDI7F292MC-BNC: 2x2Mx8 80 PIN SIMM
2
3
A0-A20
OE#
DQ7
RESET#
WE#
4
OE#
WE#
NC
A8
DQ6
5
A7
DQ5
6
A6
DQ4
2Mx8
7
RESET#
NC
NC
A5
DQ3
8
NC
A4
DQ2
CS
0
#
#
9
NC
NC
A3
DQ1
DQ0-DQ7
10
11
12
13
14
15
16
17
18
19
20
NC
NC
A2
DQ0
NC
NC
A1
NC
2Mx8
NC
A20
A19
A18
A17
A16
A15
A14
A13
A12
A0
VCC
CS
1
NC
NC
VSS
NC
NC
NC
NC
NC
NC
PD1/NC
PD2/NC
PD3/NC
PD4/NC
PD5/NC
PD6/NC
PD7/NC
VSS
NC
NC
EDI7F492MC-BNC: 4x2Mx8 80 PIN SIMM
NC
NC
A0-A20
OE#
RESET#
WE#
NC
NC
NC
2Mx8
Note: Pins 21 and 22 are not connected for EDI7F292MC.
CS
CS
0
1
#
#
A0-A20
CS0 - CS3#
WE#
Address input
Chip Enable
Write Enable
Output Enable
Data Input/Output
Presence Detect
Reset Pin
2Mx8
2Mx8
DQ0-D
OE#
DQ0-DQ7
PD1-PD7/NC*
RP
CS
CS
2
3
#
VCC
Power 5V±10%
Ground
VSS
2Mx8
NC
No Connect
#
*Contact factors if PD pin's are needed.
January 2006
Rev. 1
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
TABLE 1. EDI7F292/492MC USER BUS OPERATIONS
Module Organization
CS#
OE#
WE#
A0
A1
A6
A9
DQ0-DQ7 RESET#
Autoselect, WEDC Manuf. Code
(1)
L
L
H
L
L
L
VID
Code
H
Autoselect Device Code (1)
Read
L
L
H
L
L
L
L
X
X
L
L
H
X
X
H
L
H
A0
X
L
A1
X
L
A6
X
VID
A9
X
Code
DOUT
HIGH Z
HIGH Z
DIN
H
H
Standby
X
H
Output Disable
H
H
VID
L
X
X
X
X
H
Write
A0
X
A1
X
A6
X
A9
VID
VID
X
H
Enable Sector Group Protect (2)
Verify Sector Group Protect (2)
Temporary Sector Group Unprotect
Hardware Reset/Standby
Legend:
L
X
H
H
X
X
L
H
L
Code
X
H
X
X
X
X
VID
L
X
X
X
X
X
HIGH Z
L = logic 0, H = logic 1, X = Don’t Care. See DC Characteristics for voltage levels.
Notes:
1.
2.
Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5.
Refer to the section on Sector Group Protection.
current is typically reduced to 200 μA. The device can be
read with standard access time (tCS) from either of these
stanby modes.
READ MODE
The EDI7F292/492MC has two control functions which
must be satisfied in order to obtain data at the outputs.
CS# is the power control and should be used for device
selection . OE# is the output control and should be used to
gate data to the output pins if the device is selected.
When using the RESET# pin only, a CMOS standby mode
is achieved with RESET# input held at VSS ± 0.3V (CS#
= don't care). Under this condition the current is typically
reduced to less than 1 μA. ATTLstandby mode is achieved
with RESET# pin held at VIL (CS# = don't care). Under
this condition the current is typically reduced to less than
200 μA. One the RESET# pin is taken high, the device
requires 50 ns of wake up time before outputs are valid
for read access.
Address access time (tACC) is equal to the delay from stable
addresses to valid output data. The chip enable access
time (tCS) is the delay from stable addresses and stable
CS# to valid data at the output pins. The output enable
access time is the delay from the falling edge of OE# to
valid data at the output pins (assuming the addresses have
been stable for at lease tACC-tOE time).
In the standby mode the outputs are in the high impedance
state, independent of the OE# input.
STANDBY MODE
There are two ways to implement the standby mode on
the EDI7F292/492MC device, one using both the CS# and
RESET# pins; the other via the RESET# pin only.
OUTPUT DISABLE
With the OE# input at a logic high level (VIH), output from
the device is disabled. This will cause the output pins to
be in a high impedance state.
When using both pins, a CMOS standby mode is achieved
with CS# and RESET# inputs both held at VCC ± 0.3V.
Under this condition the current is typically reduced to
less than 1 μA. ATTL standby mode is achieved with CS#
and RESET# pins held at VIH. Under this condition the
January 2006
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
AUTOSELECT
The autoselect mode allows the reading of a binary code
from the device and will identify its manufacturer and
type. This mode is intended for use by programming
equipment for the purpose of automatically matching
the device to be programmed with its corresponding
programming algorithm. This mode is functional over the
entire temperature range of the device.
Byte 0 (A0 = VIL) ) represents the manufacturer’s code
(WEDC = 01h) and byte 1 (A0 = VIH) the device identifier
code for EDI7F292/492MC = ADh. These two bytes are
given in the table below. All identifiers for manufacturer
and device will exhibit odd parity with DQ7 defined as the
parity bit. In order to read the proper device codes when
executing the Autoselect, A1 must be VIL (see Table 2).
To activate this mode, the programming equipment must
force VID (11.5 V to 12.5 V) on address pin A9. Two
identifier bytes may then be sequenced from the device
outputs by toggling addressA0 from VIL to VIH All addresses
are don’t cares except A0, A1, and A6 (seeTable 2).
The autoselect mode also facilitates the determination
of sector group protection in the system. By performing
a read operation at the address location XX02h with the
higher order address bits A18, A19, and A20 set to the
desired sector group address, the device will return 01h
for a protected sector group and 00h for a non-protected
sector group.
The manufacturer and device codes may also be
read via the command register, for instances when
the EDI7F292/492MC is erased or programmed in a
system without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 5 (seeAutoselect
Command Sequence).
TABLE 2. EDI7F292/492MC SECTOR PROTECTION VERIFY AUTOSELECT CODES
Code
(HEX)
Type
A18 to A20
A6
A1
A0
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Manufacture Code-WEDC
EDI7F292/492MC Devis
X
X
X
X
X
X
VIL
VIL
VIL
VIL
01H
0
1
0
0
0
1
0
0
0
1
0
1
0
0
1
1
VIL VIH
VIL
ADH
Sector Group
Address
Sector Group Protection
VIL VIH
01H*
0
0
0
0
0
0
0
1
* Outputs 01H at protected sector addresses
January 2006
Rev. 1
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
TABLE 3. SECTOR ADDRESS TABLE
A20
A19
A18
A17
A16
Address Range
0
0
0
0
0
000000h-00FFFFh
SA0
SA1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A10000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
January 2006
Rev. 1
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
TABLE 4. SECTOR GROUP ADDRESS
A20
A19
A18
Sectors
0
0
0
SA0-SA3
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
SA4-SA7
SA8-SA11
SA12-SA15
SA16-SA19
SA20-SA23
SA24-SA27
SA28-SA31
WRITE
Device erasure and programming are accomplished via
the command register. The contents of the register serve
as inputs to the internal state machine. The state machine
outputs dictate the function of the device.
desired sector group address, will produce a logical “1”
at DQ0 for a protected sector group. See Table 2 for
Autoselect codes.
TEMPORARY SECTOR GROUP
UNPROTECT
The command register itself does not occupy any
addressable memory location. The register is a latch
used to store the commands, along with the address and
data information needed to execute the command. The
command register is written to by bringing WE# to VIL, while
CS# is at VIL and OE# is at VIH. Addresses are latched on
the falling edge of WE# or CS#, whichever happens later;
while data is latched on the rising edge of WE# or CS#,
whichever happens first. Standard microprocessor write
timings are used.
This feature allows temporary unprotection of previously
protected sector groups of the EDI7F292/492MC device
in order to change data in-system. The Sector Group
Unprotect mode is activated by setting the RESET# pin to
high voltage (12V). During this mode, formerly protected
sector groups can be programmed or erased by selecting
the sector group addresses. Once the 12 V is taken away
from the RESET# pin, all the previously protected sector
groups will be protected again. Refer to Figures 15 and
16.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing parameters.
COMMAND DEFINITIONS
SECTOR GROUP PROTECTION
Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in
the improper sequence will reset the device to the
read mode. Table 5 defines the valid register command
sequences. Note that the Erase Suspend (B0h) and Erase
Resume (30h) commands are valid only while the Sector
Erase operation is in progress. Moreover, both Reset/Read
commands are functionally equivalent, resetting the device
to the read mode.
The EDI7F292/492MC features hardware sector group
protection. This feature will disable both program and
erase operations in any combination of eight sector groups
of memory. Each sector group consists of four adjacent
sectors grouped in the following pattern: sectors 0-3,
4-7, 8-11, 12-15, 16-19, 20-23, 24-27, and 28-31 (see
Table 4). The sector group protect feature is enabled
using programming equipment at the user’s site. The
device is shipped with all sector groups unprotected. It is
possible to determine if a sector group is protected in the
system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where
the higher order address bits A18, A19, and A20 is the
January 2006
Rev. 1
7
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
TABLE 5. COMMAND DEFINITION
Command Sequence
Read/Reset
Bus Write
Cycles Req'd
Fourth Bus
Read/Write
Cycle
First Bus Write
Cycle
Second Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus Write Sixth Bus Write
Cycle
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr Data
Addr Data
Reset/Read
Reset/Read
Autoselect
1
3
3
4
6
6
1
1
XXXXH F0H 2AAAH
5555H AAH 2AAAH 55H 5555H F0H
5555H AAH 2AAAH 55H 5555H 90H
5555H AAH 2AAAH 55H 5555H A0H
RA
RD
Byte Program
Chip Erase
Sector Erase
Erase Suspend
Erase Suspend
Notes:
PA
Data
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
SA
30H
XXXXH B0H
XXXXH 30H
1.
2.
Bus operations are defined in Table 1.
RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE#
SA= Address of the sector to be erased. The combination of A20, A19, A18, A17, and A16 will uniquely select any sector.
RD = Data read from location RA during read operation.
3.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#
Read and Byte program functions to non-erasing sectors are allowed in the Erase Suspend mode.
Address bits A15, A14, A13, A12 and A11 = X, X = don’t care.
4.
5.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the
memory. The device remains enabled for reads until the
command register contents are altered.
operation to supplement traditional PROM programming
methodology. The operation is initiated by writing the
autoselect command sequence into the command register.
Following the command write, a read cycle from address
XX00h retrieves the manufacturer code of 01h. A read
cycle from address XX01h returns the device code ADh
(see Table 2).
The device will automatically power-up in the read/reset
state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will
retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during
the power transition. Refer to theAC Read Characteristics
and Waveforms for the specific timing parameters.
All manufacturer and device codes will exhibit odd parity
with DQ7 defined as the parity bit.
Furthermore, the write protect status of sectors can be
read in this mode. Scanning the sector group addresses
(A18, A19, and A20) while (A6, A1, A0) = (0, 1, 0) will
produce a logical “1” at device output DQ0 for a protected
sector group.
AUTOSELECT COMMAND
Flash memories are intended for use in applications
where the local CPU can alter memory contents. As such,
manufacture and device codes must be such, manufacture
and device codes must be tem. PROM programmers
typically access the signature codes by raising A9 to a
high voltage. However, multiplexing high voltage onto the
address lines is not generally a desirable system design
practice. The device contains an autoselect command
To terminate the operation, it is necessary to write the
read/reset command sequence into the register.
BYTE PROGRAMMING
The device is programmed on a byte-by-byte basis.
Programming is a four bus cycle operation. There are two
“unlock” write cycles. These are followed by the program
set-up command and data write cycles. Addresses are
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latched on the falling edge of CS# OR WE#, whichever
happens later and the data is latched on the rising edge of
CS# or WE#, whichever happens first. The rising edge of
CS# or WE# (whichever happens first) begins programming
using the Embedded Program Algorithm. Upon executing
the algorithm, the system is not required to provide further
controls or timings. The device will automatically provide
adequate internally generated program pulses and verify
the programmed cell margin.
section) at which time the device returns to read mode.
Figure 2 illustrates the Embedded Erase Algorithm using
typical command strings and bus operations.
SECTOR ERASE
Sector erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE#, while the command
(30h) is latched on the rising edge of WE#. After a time-
out of 50 μs from the rising edge of the last sector erase
command, the sector erase operation will begin.
This automatic programming operation is completed when
the data on DQ7 (also used as Data# Polling) is equivalent
to the data written to this bit at which time the device returns
to the read mode and addresses are no longer latched (see
Table 6, Write Operation Status). Therefore, the device
requires that a valid address to the device be supplied
by the system at this particular instance of time for Data#
Polling operations. Data# Polling must be performed at the
memory location which is being programmed.
Multiple sectors may be erased sequentially by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
concurrently erased. The time between writes must be less
than 50 μs otherwise that command will not be accepted
and erasure will start. It is recommended that processor
interrupts be disabled during this time to guarantee this
condition. The interrupts can be re-enabled after the last
Sector Erase command is written.Atime-out of 50 μs from
the rising edge of the last WE# will initiate the execution
of the Sector Erase command(s). If another falling edge
of the WE# occurs within the 50 μs time-out window the
timer is reset. (Monitor DQ3 to determine if the sector
erase timer window is still open, see section DQ3, Sector
Erase Timer.) Any command other than Sector Erase or
Erase Suspend during this period will reset the device to
the read mode, ignoring the previous command string. In
that case, restart the erase on those sectors and allow
them to complete.(Refer to the Write Operation Status
section for DQ3, Sector Erase Timer, operation.) Loading
the sector erase buffer may be done in any sequence and
with any number of sectors (0 to 31).
Any commands written to the chip during the Embedded
Program Algorithm will be ignored. If a hardware reset
occurs during the programming operation, the data at that
particular location will be corrupted.
Programming is allowed in any sequence and across sector
boundaries. Beware that a data “0” cannot be programmed
back to a “1”. Attempting to do so may either hang up the
device or result in an apparent success according to the
data polling algorithm but a read from reset/read mode will
show that the data is still “0”. Only erase operations can
convert “0”s to “1”s.
Figure 1 illustrates the Embedded ProgrammingAlgorithm
using typical command strings and bus operations.
CHIP ERASE
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are
then followed by the chip erase command.
Sector erase does not require the user to program the
device prior to erase. The device automatically programs
all memory locations in the sector(s) to be erased prior
to electrical erase. When erasing a sector or sectors the
remaining unselected sectors are not affected. The system
is not required to provide any controls or timings during
these operations.
Chip erase does not require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device will
automatically program and verify the entire memory for an
all zero data pattern prior to electrical erase. The system
is not required to provide any controls or timings during
these operations.
The automatic sector erase begins after the 50 μs time out
from the rising edge of the WE# pulse for the last sector
erase command pulse and terminates when the data on
The automatic erase begins on the rising edge of the last
WE# pulse in the command sequence and terminates
when the data on DQ7 is “1” (see Write Operation Status
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DQ7, Data# Polling, is “1” (see Write Operation Status
section) at which time the device returns to the read mode.
Data# Polling must be performed at an address within any
of the sectors being erased.
the erase operation has been suspended. Further writes
of the Erase Suspend command are ignored.
When the erase operation has been suspended, the device
defaults to the erase-suspend-read mode. Reading data in
this mode is the same as reading from the standard read
mode except that the data must be read from sectors that
have not been erase-suspended. Successively reading
from the erase-suspended sector while the device is in
the erase-suspend-read mode will cause DQ2 to toggle.
(See the section on DQ2).
Figure 2 illustrates the Embedded Erase Algorithm using
typical command strings and bus operations.
ERASE SUSPEND
The Erase Suspend command allows the user to interrupt
a Sector Erase operation and then perform data reads or
programs to a sector not being erased. This command is
applicable ONLY during the Sector Erase operation which
includes the time-out period for sector erase. The Erase
Suspend command will be ignored if written during the Chip
Erase operation or Embedded ProgramAlgorithm. Writing
the Erase Suspend command during the Sector Erase
time-out results in immediate termination of the time-out
period and suspension of the erase operation.
After entering the erase-suspend-read mode, the user can
program the device by writing the appropriate command
sequence for Byte Program. This program mode is
known as the erase-suspend-program mode. Again,
programming in this mode is the same as programming in
the regular Byte Program mode except that the data must
be programmed to sectors that are not erase-suspended.
Successively reading from the erase-suspended sector
while the device is in the erase-suspend-program mode
will cause DQ2 to toggle. The end of the erase-suspended
program operation is detected by the RY/BY# output pin,
Data# Polling of DQ7, or by the Toggle Bit I (DQ6) which
is the same as the regular Byte Program operation. Note
that DQ7 must be read from the byte program address
while DQ6 can be read from any address.
Any other command written during the Erase Suspend
mode will be ignored except the Erase Resume command.
Writing the Erase Resume command resumes the erase
operation. The addresses are “don’t-cares” when writing
the Erase Suspend or Erase Resume command.
When the Erase Suspend command is written during the
Sector Erase operation, the device will take a maximum
of 15 μs to suspend the erase operation. When the device
has entered the erase-suspended mode, the RY/BY#
output pin and the DQ7 bit will be at logic ‘1’, and DQ6
will stop toggling. The user must use the address of the
erasing sector for reading DQ6 and DQ7 to determine if
To resume the operation of Sector Erase, the Resume
command (30h) should be written.Any further writes of the
Resume command at this point will be ignored. Another
Erase Suspend command can be written after the chip
has resumed erasing.
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TABLE 6. WRITE OPERATION STATUS
Status
DQ7
DQ7#
0
CQ6
Toggle
Toggle
1
DQ5
DQ3
DQ2
1
Byte Program in Embedded Program Algorithm
Embedded Program Algorithm
0
0
0
0
1
1
Toggle
Erase Suspended Read
1
Toggle
In Progress
(Erase Suspended Sector)
(Note 1)
Erase Suspended Read
Erase Suspended Mode
Data
Data
Data
0
Data
1
Data
(Non-Erase Suspended Sector)
Erase Suspended Read
DQ7#
Toggle
1
(Non-Erase Suspended Sector)
(Note 2)
(Note 3)
Byte Program in Embedded Program Algorithm
DQ7#
0
Toggle
Toggle
Toggle
1
1
1
0
1
1
1
Exceeded Time
Limits
Program/Erase Program in Embedded Program Algorithm
N/A
N/A
Erase Suspended Read
Erase Suspended Mode
DQ7#
(Non-Erase Suspended Sector)
Notes:
1.
2.
3.
Performing successive read operations from the erase-suspended sector will cause DQ2 to toggle.
Performing successive read operations from any address will cause DQ6 to toggle.
Reading the byte address being programmed while in the erase-suspend program mode will indicate logic ‘1’ at the DQ2 bit.
However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
DQ7
DATA# POLLING
sequence. For sector erase, the Data# Polling is valid after
the last rising edge of the sector erase WE# pulse. Data#
Polling must be performed at sector addresses within any
of the sectors being erased and not a sector that is within
a protected sector group. Otherwise, the status may not
be valid.
The EDI7F292/492MC device features Data# Polling
as a method to indicate to the host that the embedded
algorithms are in progress or completed. During the
Embedded Program Algorithm, an attempt to read the
device will produce the complement of the data last written
to DQ7. Upon completion of the Embedded Program
Algorithm, an attempt to read the device will produce the
true data last written to DQ7. During the Embedded Erase
Algorithm, an attempt to read the device will produce a
“0” at the DQ7 output. Upon completion of the Embedded
EraseAlgorithm an attempt to read the device will produce
a “1” at the DQ7 output. The flowchart for Data# Polling
(DQ7) is shown in Figure 3.
Just prior to the completion of Embedded Algorithm
operations DQ7 may change asynchronously while the
output enable (OE#) is asserted low. This means that the
device is driving status information on DQ7 at one instant
of time and then that byte’s valid data at the next instant
of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the
device has completed the EmbeddedAlgorithm operations
and DQ7 has a valid data, the data outputs on DQ0–DQ6
may be still invalid. The valid data on DQ0–DQ7 can be
read on the successive read attempts.
Data# Polling will also flag the entry into Erase Suspend.
DQ7 will switch “0” to “1” at the start of the Erase Suspend
mode. Please note that the address of an erasing sector
must be applied in order to observe DQ7 in the Erase
Suspend Mode.
The Data# Polling feature is only active during the
Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, erase-suspend-program mode,
or sector erase time-out (see Table 6).
During Program in Erase Suspend, Data# Polling will
perform the same as in regular program execution outside
of the suspend mode.
See Figure 11 for the Data# Polling timing specifications
and diagrams.
For chip erase, the Data# Polling is valid after the
rising edge of the sixth WE# pulse in the six write pulse
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DQ6
TOGGLE BIT I
DQ3
SECTOR ERASE TIMER
The EDI7F292/492MC also features the “Toggle Bit I” as a
method to indicate to the host system that the embedded
algorithms are in progress or completed.
After the completion of the initial sector erase command
sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data# Polling
and Toggle Bit I are valid after the initial sector erase
command sequence. If Data# Polling or the Toggle Bit I
indicates the device has been written with a valid erase
command, DQ3 may be used to determine if the sector
erase timer window is still open. If DQ3 is high (“1”) the
internally controlled erase cycle has begun; attempts to
write subsequent commands (other than Erase Suspend)
to the device will be ignored until the erase operation is
completed as indicated by Data# Polling or Toggle Bit I. If
DQ3 is low (“0”), the device will accept additional sector
erase commands. To insure the command has been
accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase
command. If DQ3 were high on the second status check,
the command may not have been accepted.
During an Embedded Program or Erase Algorithm cycle,
successive attempts to read (OE# toggling) data from the
device at any address will result in DQ6 toggling between
one and zero. Once the Embedded Program or Erase
Algorithm cycle is completed, DQ6 will stop toggling and
valid data will be read on the next successive attempts.
During programming, the Toggle Bit I is valid after the
rising edge of the fourth WE# pulse in the four write pulse
sequence. For chip erase, the Toggle Bit I is valid after the
rising edge of the sixth WE# pulse in the six write pulse
sequence. For Sector Erase, the Toggle Bit I is valid after
the last rising edge of the sector erase WE# pulse. The
Toggle Bit I is active during the sector erase time out.
Either CS# or OE# toggling will cause the DQ6 to toggle.
In addition, an Erase Suspend/Resume command will
cause DQ6 to toggle. See Figure 12 for the Toggle Bit I
timing specifications and diagrams.
Refer to Table 6: Write Operation Status.
DQ2
TOGGLE BIT II
DQ5
EXCEEDED TIMING LIMITS
This toggle bit, along with DQ6, can be used to determine
whether the device is in the Embedded Erase Algorithm
or in Erase Suspend.
DQ5 will indicate if the program or erase time has
exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure
condition which indicates that the program or erase cycle
was not successfully completed. Data# Polling is the only
operating function of the device under this condition. The
CS# circuit will partially power down the device under these
conditions (to approximately 2 mA). The OE# and WE#
pins will control the output disable functions as described
in Table 1.
Successive reads from the erasing sector will cause DQ2
to toggle during the Embedded Erase Algorithm. If the
device is in the erase-suspended-read mode, successive
reads from the erase-suspend sector will cause DQ2
to toggle. When the device is in the erase-suspended-
program mode, successive reads from the byte address
of the non-erase suspended sector will indicate a logic ‘1’
at the DQ2 bit.
The DQ5 failure condition will also appear if a user tries to
program a “1” to a location that is previously programmed
to “0”. In this case the device locks out and never
completes the Embedded Program Algorithm. Hence, the
system never reads a valid data on DQ7 bit and DQ6 never
stops toggling. Once the device has exceeded timing limits,
the DQ5 bit will indicate a “1.” Please note that this is not
a device failure condition since the device was incorrectly
used. If this occurs, reset the device.
DQ6 is different from DQ2 in that DQ6 toggles only
when the standard Program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these
two status bits, along with that of DQ7, is summarized as
follows:
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RESET#
HARDWARE RESET
Mode
DQ7
DQ6
DQ2
The EDI7F292/492MC device may be reset by driving the
RESET# pin to VIL. The RESET# pin must be kept low
(VIL) for at least 500 ns. Any operation in progress will be
terminated and the internal state machine will be reset to
the read mode 20 μs after the RESET# pin is driven low.
If a hardware reset occurs during a program operation, the
data at that particular location will be indeterminate.
DQ7#
toggles
1
Program
Erase
0
1
toggles
1
toggles
toggles
Erase Suspend Read (1)
(Erase-Suspend Sector)
Erase Suspend Program
DQ7# (2)
toggles
1 (2)
Notes:
1.
These status flags apply when outputs are read from a sector that has been
erase-suspended.
These status flags apply when outputs are read from the byte address of the
non-erase suspended sector.
When the RESET# pin is low and the internal reset is
complete, the device goes to standby mode and cannot
be accessed. Also, note that all the data output pins are
tri-stated for the duration of the RESET# pulse. Once
the RESET# pin is taken high, the device requires
500 ns of wake up time until outputs are valid for read
access. The RESET# pin may be tied to the system
reset input. Therefore, if a system reset occurs during the
Embedded Program or Erase Algorithm, the device will
be automatically reset to read mode and this will enable
the system’s microprocessor to read the boot-up firmware
from the Flash memory.
2.
For example, DQ2 and DQ6 can be used together to
determine the erase-suspend-read mode (DQ2 toggles
while DQ6 does not). See also Table 6 and Figure 17.
Furthermore, DQ2 can also be used to determine which
sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from the erasing
sector.
RY/BY#
READY/BUSY#
DATA PROTECTION
The EDI7F292/492MC is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during power
transitions. During power up the device automatically
resets the internal state machine in the Read mode. Also,
with its control register architecture, alteration of the
memory contents only occurs after successful completion
of specific multi-bus cycle command sequences.
The EDI7F292/492MC provides a RY/BY# open-drain
output pin as a way to indicate to the host system that
the Embedded Algorithms are either in progress or has
been completed. If the output is low, the device is busy
with either a program or erase operation. If the output is
high, the device is ready to accept any read/write or erase
operation. When the RY/BY# pin is low, the device will
not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the
EDI7F292/492MC is placed in an Erase Suspend mode,
the RY/BY# output will be high.
The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up and
power-down transitions or system noise.
During programming, the RY/BY# pin is driven low after
the rising edge of the fourth WE# pulse. During an erase
operation, the RY/BY# pin is driven low after the rising
edge of the sixth WE# pulse. The RY/BY# pin will indicate
a busy condition during the RESET# pulse. Refer to Figure
13 for a detailed timing diagram. The RY/BY# pin is pulled
high in standby mode.
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up and
power-down, a write cycle is locked out for VCC less than
3.2 V (typically 3.7 V). If VCC < VLKO, the command register
is disabled and all internal program/erase circuits are
disabled. Under this condition the device will reset to the
read mode. Subsequent writes will be ignored until the VCC
level is greater than VLKO. It is the user’s responsibility to
ensure that the control pins are logically correct to prevent
unintentional writes when VCC is above 3.2 V.
Since this is an open-drain output, several RY/BY# pins
can be tied together in parallel with a pull-up resistor to
VCC
.
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WRITE PULSE "GLITCH" PROTECTION
POWER-UP WRITE INHIBIT
Noise pulses of less than 5 ns (typical) on OE#, CS# or
WE# will not initiate a write cycle.
Power-up of the device with WE# = CS# = VIL, and OE#
= VIH will not accept command on the rising edge of WE#
The internal state machine is automatically reset to the
read mode on power-up.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE# = VIL, CS#
=VIH or WE# = VIH. To initiate a write cycle CS# and WE#
must be a logical zero while OE# is a logical one.
FIGURE 1. EMBEDDED PROGRAMMING ALGORITHM
Program Command Sequence (Address/Command):
Start
Write Program Command Sequence
(see below)
Data# Poll Device
No
Increment Address
Last Address
?
Yes
Programming Completed
5555h/AAh
2AAAh/55h
5555h/A0h
Program Address/Program Data
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FIGURE 2. EMBEDDED ERASE ALGORITHM
Start
Write Erase Command Sequence
(see below)
Data# Polling or Toggle Bit I
Successfully Completed
Erasure Completed
Chip Erase Command Sequence Individual Sector/Multiple Sector
(Address/Command):
Erase Command Sequence
(Address/Command):
5555h/AAh
5555h/AAh
2AAAh/55h
2AAAh/55h
5555h/80h
5555h/80h
5555h/AAh
5555h/AAh
2AAAh/55h
2AAAh/55h
5555h/10h
Sector Address/30h
Sector Address/30h
Additional sector
erase commands
are optional
Sector Address/30h
NOTE:
To insure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 were high on
the second status check, the command may not have been accepted.
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FIGURE 3 DATA# POLLING ALGORITHM
Start
VA = Byte address for programming
= Any of the sector addresses within the sector being
erased during sector erase operation
= Valid address equals any non-protected sector group
address during chip erase
Read Byte
(DQ0–DQ7)
Addr = VA
Yes
DQ7 = Data
?
No
No
DQ5 = 1
?
Yes
Read Byte
(DQ0–DQ7)
Addr = VA
Yes
DQ7 = Data
?
No
Pass
Fail
DQ7 is rechecked even if DQ5 = “1” because DQ7 may change simultaneously with DQ5.
FIGURE 5 MAXIMUM NEGATIVE OVERSHOOT WAVEFORM
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
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FIGURE 4 TOGGLE BIT I ALGORITHM
Start
Read Byte
(DQ0–DQ7)
Addr = Don’t Care
No
DQ6 = Toggle
?
Yes
No
DQ5 = 1
?
Yes
Read Byte
(DQ0–DQ7)
Addr = Don’t Care
No
DQ6 = Toggle
?
Yes
Pass
Fail
DQ6 is rechecked even if DQ5 = “1” because DQ6 may stop toggling at the same time as DQ5 changing to “1”.
FIGURE 6 MAXIUM POSITIVE OVERSHOOT WAVEFORM
20 ns
VCC + 2.0 V
VCC + 0.5 V
2.0 V
20 ns
20 ns
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ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Commercial (C) Devices
Storage Temperature
Plastic Packages..................................–65°C to +150°C
Case Temperature (TC) ..............................0°C to +70°C
Industrial (I) Devices
Ambient Temperature
with Power Applied...............................–65°C to +125°C
Case Temperature (TC) ..........................–40°C to +85°C
Voltage with Respect to Ground
V
V
V
CC Supply Voltages
VCC (Note 1) ...................................... –2.0 V to +7.0 V
CC for EDI7F292/492MC ................ +4.75 V to +5.25 V
CC for EDI7F292/492MC 100, 120 .. +4.50 V to +5.50 V
A9, OE#, and RESET# (Note 2)....... –2.0 V to +13.5 V
All other pins (Note 1) ........................ –2.0 V to +7.0 V
Output Short Circuit Current (Note 3) .................200 mA
Operating ranges define those limits between which the functionality of the device is
guaranteed.
Notes:
1.
2.
3.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions,
input may overshoot VSS to –2.0 V for periods of up to 20 ns. Maximum DC
voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.
Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During
voltage transitions, A9, OE#, and RESET# may overshoot VSS to –2.0 V for
periods of up to 20 ns. Maximum DC input voltage on pin A9 is +12.5 V which
may overshoot to 14.0 V for periods up to 20 ns.
No more than one output may be shorted to ground at a time. Duration of the
short circuit should not be greater than one second.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
data sheet is not implied. Exposure of the device to absolute maximum rating conditions
for extended periods may affect device reliability.
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DC CHARACTERISTICS (EDI7F292MC)
TTL/NMOS COMPATIBLE
Parameter
Symbol
Parameter Description
Test Description
VIN = VSS to VCC = VCCMAX
Min
Max
Units
ILI
Input Load Current
±1.0
50
μA
μA
μA
mA
mA
mA
mA
mA
V
ILIT
ILO
A9 Input Load Current
Output Leakage Current
VCC Active Current (Note 1)
VCC Active Current (Notes 2, 3)
VCC Standby Current
VCC Standby Current (Reset)
Input Low Level
VCC = VCCMAX, A9 = 12.0 Volt
VOUT = VSS to VCC, VCC = VCCMAX
CS# = VIL, OE# = VIH
±1.0
80
ICC1
ICC2
ICC3
ICC4
VIL
CS# = VIL, OE# = VIH
120
2
VCC = VCCMAX, CS# = VIL, RESET# = VIH
VCC = VCCMAX, RESET# = VIL
2
-0.5
2.0
0.8
VIH
VID
Input High Level
VCC + 0.5
12.5
Voltage for Autoselect and
Sector Protect
VCC = 5.0 Volt
11.5
V
VOL
Output Low Voltage
Output High Level
IOL = 12 mA VCC = VCCMIN
IOH = -2.5 mA VCC = VCCMIN
0.45
4.2
V
V
V
VOH
VLKO
2.4
3.2
Low VCC Lock-out Voltage
Notes:
1.
The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz,
with OE# at VIH
CC active while Embedded Program or Erase Algorithm is in progress.
Not 100% tested.
.
2.
3.
I
DC CHARACTERISTICS (EDI7F292MC)
CMOS COMPATIBLE
Parameter
Symbol
Parameter Description
Test Description
Min
Typ
Max
Units
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCCMAX
VCC = VCCMAX, A9 = 12.0 Volt
VOUT = VSS to VCC, VCC = VCCMAX
CS# = VIL, OE# = VIH
±1.0
50
μA
μA
μA
mA
mA
mA
ILIT
A9 Input Load Current
Output Leakage Current
VCC Active Current (Note 1)
VCC Active Current (Notes 2, 3)
VCC Standby Current
ILO
±1.0
80
ICC1
ICC2
ICC3
50
60
2
CS# = VIL, OE# = VIH
80
VCC = VCCMAX, CS# = VCC ± 0.3 V, RESET#
= VCC ± 0.3 V
10
ICC4
VIL
VCC Standby Current (Reset)
Input Low Level
VCC = VCCMAX, RESET# = VCC ± 0.3 V
2
10
0.8
mA
mA
V
-0.5
0.7 X VCC
11.5
VIH
VID
Input High Level
VCC + 0.3
12.5
Voltage for Autoselect and
Sector Protect
VCC = 5.0 Volt
V
VOL
Output Low Voltage
IOL = 12 mA VCC = VCCMIN
IOH = -2.5 mA VCC = VCCMIN
0.85 VCC
2.4
0.45
V
V
V
V
VOH
VLKO
Output High Level
IOH = -100 μA, VCC = VCCMIN
VCC - 0.4
3.2
Low VCC Lock-out Voltage
4.2
Notes:
1.
The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz,
with OE# at VIH
CC active while Embedded Program or Erase Algorithm is in progress.
Not 100% tested.
.
2.
3.
I
January 2006
Rev. 1
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
DC CHARACTERISTICS (EDI7F492MC)
TTL/NMOS COMPATIBLE
Parameter
Symbol
Parameter Description
Test Description
VIN = VSS to VCC = VCCMAX
Min
Max
Units
ILI
Input Load Current
±1.0
50
μA
μA
μA
mA
mA
mA
mA
mA
V
ILIT
ILO
A9 Input Load Current
Output Leakage Current
VCC Active Current (Note 1)
VCC Active Current (Notes 2, 3)
VCC Standby Current
VCC Standby Current (Reset)
Input Low Level
VCC = VCCMAX, A9 = 12.0 Volt
VOUT = VSS to VCC, VCC = VCCMAX
CS# = VIL, OE# = VIH
±1.0
160
240
4
ICC1
ICC2
ICC3
ICC4
VIL
CS# = VIL, OE# = VIH
VCC = VCCMAX, CS# = VIL, RESET# = VIH
VCC = VCCMAX, RESET# = VIL
4
-0.5
2.0
0.8
VIH
VID
Input High Level
VCC + 0.5
12.5
Voltage for Autoselect and
Sector Protect
VCC = 5.0 Volt
11.5
V
VOL
Output Low Voltage
Output High Level
IOL = 12 mA VCC = VCCMIN
IOH = -2.5 mA VCC = VCCMIN
0.45
4.2
V
V
V
VOH
VLKO
2.4
3.2
Low VCC Lock-out Voltage
Notes:
1.
The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz,
with OE# at VIH
CC active while Embedded Program or Erase Algorithm is in progress.
Not 100% tested.
.
2.
3.
I
DC CHARACTERISTICS (EDI7F492MC)
CMOS COMPATIBLE
Parameter
Symbol
Parameter Description
Test Description
Min
Typ
Max
Units
ILI
Input Load Current
VIN = VSS to VCC, VCC = VCCMAX
VCC = VCCMAX, A9 = 12.0 Volt
VOUT = VSS to VCC, VCC = VCCMAX
CS# = VIL, OE# = VIH
±1.0
50
μA
μA
μA
mA
mA
mA
ILIT
A9 Input Load Current
Output Leakage Current
VCC Active Current (Note 1)
VCC Active Current (Notes 2, 3)
VCC Standby Current
ILO
±1.0
160
160
20
ICC1
ICC2
ICC3
100
120
4
CS# = VIL, OE# = VIH
VCC = VCCMAX, CS# = VCC ± 0.3 V, RESET#
= VCC ± 0.3 V
ICC4
VIL
VCC Standby Current (Reset)
Input Low Level
VCC = VCCMAX, RESET# = VCC ± 0.3 V
4
20
0.8
mA
mA
V
-0.5
0.7 X VCC
11.5
VIH
VID
Input High Level
VCC + 0.3
12.5
Voltage for Autoselect and
Sector Protect
VCC = 5.0 Volt
V
VOL
Output Low Voltage
IOL = 12 mA VCC = VCCMIN
IOH = -2.5 mA VCC = VCCMIN
0.85 VCC
2.4
0.45
V
V
V
V
VOH
VLKO
Output High Level
IOH = -100 μA, VCC = VCCMIN
VCC - 0.4
3.2
Low VCC Lock-out Voltage
4.2
Notes:
1.
The ICC current listed includes both the DC operating current and the frequency dependent component (at 6 MHz). The frequency component typically is less than 1 mA/MHz,
with OE# at VIH
CC active while Embedded Program or Erase Algorithm is in progress.
Not 100% tested.
.
2.
3.
I
January 2006
Rev. 1
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
AC CHARACTERISTICS
READ-ONLY OPERATIONS CHARACTERISTICS
Parameter Symbol
Speed Options (Notes 1 and 2)
Parameter Desription
Read Cycle Time 4
Test Setup
CS# = VIL
JEDEC
Standard
-100
-120
tAVAV
tRC
Min
100
120
OE# = VIL
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tACC
tCS
tOE
tDF
Address to Output Delay
OE# = VIL
Max
Max
Max
Max
Max
Min
100
100
40
20
20
0
120
120
50
30
30
0
Chip Enable to Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z (Notes 3, 4)
Output Enable to Output High Z (Notes 3, 4)
tDF
tOH
Output Hold Time From Addresses CS# or
OE# Which Ever Occurs First
tReady
RESET# Pin Low to Read Mode 4
Max
20
20
Notes:
1.
Test Conditions (for all others): Output Load: 1 TTL gate and 100 pF Input rise and fall times: 20 ns Input pulse levels: 0.45 V to 2.4 V Timing measurement reference level: 0.8 V
and 2.0 V input and output.
Output driver disable time.
Not 100% tested.
2.
3.
FIGURE 7 TEST CONDITIONS
5.0 Volt
1N3064
2.7 kΩ
or Equivalent
Device
Under
Test
6.2 kΩ
CL
Diodes = 1N3064
or Equivalent
Note:
CL = 100 pF including jig capacitance
January 2006
Rev. 1
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
AC CHARACTERISTICS
WRITE/ERASE/PROGRAM OPERATIONS
Parameter Symbol
Speed Options (Notes 1 and 2)
Parameter Desription
JEDEC
tAVAV
Standard
tWC
-100
100
0
-120
120
0
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
Min
Min
tAVWL
tAS
tWLAX
tDVWH
tWHDX
tAH
45
45
0
50
50
0
tDS
tDH
Output Enable Hold
Time
Read 2
0
0
tOEH
Toggle Bit I and
Data# Polling 2
10
10
tGHWL
tGHWL
Read Recover Time Before Write OE# high to
WE# low
Min
0
0
tELWL
tCS
CS# Setup Time
Min
Min
Min
Min
Typ
Typ
Max
Min
Min
Min
Min
Min
Min
0
0
0
0
tWHEH
tWLWH
tWHWL
tWHWH1
tCH
CS# Hold Time
tWP
Write Pulse Width
45
20
7
50
20
7
tWPH
tWHWH1
Write Pulse Width High
Byte Programming Operation
1
1
tWHWH2
tWHWH2
Sector Erase Operation 1
8
8
tVCS
VCC Set Up Time 2
50
500
4
50
500
4
tVIDR
tVLHT
tOESP
tRP
Rise Time to VID (Notes 2, 3)
Voltage Transition Time (Notes 2, 3)
OE# Setup Time to WE# Active ( 2, 3)
RESET# Pulse Width
4
4
500
40
500
50
tBUSY
Program/Erase Valid to RY/BY# Delay
Notes:
1.
2.
3.
This does not include the preprogramming time.
Not 100% tested.
These timings are for Temporary Sector Group Unprotect operation.
January 2006
Rev. 1
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
SWITCHING TEST WAVEFORM
FIGURE 8. AC WAVEFORM FOR READ OPERATION
t
RC
Addresses Stable
Addresses
t
ACC
CS#
(t
)
DF
t
OE
OE#
WE#
t
OEH
(t
)
CE
(t
)
OH
High Z
High Z
Outputs
Output Valid
January 2006
Rev. 1
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
SWITCHING WAVEFORMS
FIGURE 9. PROGRAM OPERATION TIMINGS
Data# Polling
3rd Bus Cycle
5555H
Addresses
PA
PA
t
t
AH
RC
t
t
WC
AS
CE#
t
GHWL
OE
t
t
WHWH1
WP
WE#
t
WPH
t
CS
t
DF
t
t
DH
OE
Data
PD
DQ7
A0H
D
OUT
t
t
DS
OH
5.0 Volt
t
CE
Notes:
1.
2.
3.
4.
5.
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7# is the output of the complement of the data written to the device.
OUT is the output of the data written to the device.
Figure indicates last two bus cycles of four bus cycle sequence.
D
FIGURE 10. AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
t
AH
5555H
Addresses
2AAAH
5555H
5555H
2AAAH
SA
t
AS
CS#
t
GHWL
OE#
WE#
t
WP
t
WPH
t
CS
t
DH
Data
AAH
55H
80H
AAH
55H
10H/30H
t
DS
V
CC
t
VCS
Notes:
1.
SA is the sector address for Sector Erase. Addresses = don’t care for Chip Erase.
January 2006
Rev. 1
24
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
SWITCHING WAVEFORMS
FIGURE 11. AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED
ALGORITHM OPERATION
tCH
CS#
tDF
tOE
OE#
tOEH
tCE
WE#
tOH
*
High Z
DQ7 =
Valid Data
DQ7
DQ7
tWHWH 1 or 2
DQ0–DQ7
Valid Data
DQ0–DQ6
DQ0–DQ6 = Invalid
Notes:
DQ7 = Valid Data (The device has completed the Embedded operation).
FIGURE 12. AC WAVEFORMS FOR TOGGLE BIT I DURING EMBEDDED
ALGORITHM OPERATIONS
CS#
t
OEH
WE#
OE#
*
DQ6 =
DQ0–DQ7
Valid
DQ6 = Toggle
DQ6 = Toggle
Data (DQ0–DQ7)
Stop Toggling
t
OE
Notes:
• DQ6 stops toggling (The device has completed the Embedded operation).
January 2006
Rev. 1
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
FIGURE 13. BY/RY# TIMING DIAGRAM DURING PROGRAM/ERASE OPERATIONS
CS#
The rising edge of the last WE# signal
WE#
Entire programming
or erase operations
RY/BY#
t
BUSY
FIGURE 14. RESET# TIMING DIAMGRAM
RESET#
tRP
tReady
FIGURE 15. TEMPORARY SECTOR GROUP UNPORTECT ALGORITHM
Start
RESET# = V
ID
(Note 1)
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector Group
Unprotect Completed
(Note 2)
Notes:
1.
2.
All protected sector groups unprotected.
All previously protected sector groups are protected once
again.
January 2006
Rev. 1
26
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
FIGURE 16. TEMPORARY SECTOR GROUP UNPORTECT TIMING DIAMGRAM
12V
0 or 5V
0V or 5 V
RESET#
CS#
t
VIDR
WE#
Program or Erase Command Sequence
RY/BY#
FIGURE 17. DQ2 VS. DQ6
Enter
Erase
Suspend
Enter Erase
Suspend Program
Embedded
Erasing
Erase
Resume
Erase
Erase Suspend
Read
Erase
Erase
Complete
WE#
Erase
Erase Suspend
Read
Suspend
Program
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE#
Notes:
• DQ2 is read from the erase-suspended sector.
January 2006
Rev. 1
27
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
AC CHARACTERISTICS
WRITE/ERASE/PROGRAM OPERATIONS
Alternate CS# Controlled Writes
Parameter Symbol
Speed Options (Notes 1 and 2)
Parameter Desription
JEDEC
tAVAV
Standard
tWC
-100
100
0
-120
120
0
Write Cycle Time
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Min
Min
Min
Min
Min
Min
Min
tAVWL
tAS
tWLAX
tDVWH
tWHDX
tAH
45
45
0
50
50
0
tDS
tDH
Output Enable Hold
Time
Read (Note 2)
0
0
Toggle Bit I and
Data# Polling
(Note 2)
10
10
tOEH
tGHWL
tGHWL
Read Recover Time Before Write OE# high to
WE# low
Min
0
0
tELWL
tCS
CS# Setup Time
Min
Min
Min
Min
Typ
Typ
Max
0
0
0
0
tWHEH
tWLWH
tWHWL
tWHWH1
tCH
CS# Hold Time
tWP
Write Pulse Width
45
20
7
50
20
7
tWPH
tWHWH1
Write Pulse Width High
Byte Programming Operation
1
1
tWHWH2
tWHWH2
Sector Erase Operation (Note 1)
8
8
Notes:
1.
2.
This does not include the preprogramming time.
Not 100% tested.
January 2006
Rev. 1
28
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
FIGURE 18. ALTERNATE CS# CONTROLLED PROMGRAM OPERATION TIMING
Data# Polling
5555H
PA
PA
Addresses
t
AH
t
t
WC
AS
WE#
OE#
t
GHEL
t
t
CP
WHWH1
CS#
t
CPH
t
WS
t
DH
D
Data
PD
DQ7#
A0H
OUT
t
DS
5.0 Volt
Notes:
1.
2.
3.
4.
5.
PA is address of the memory location to be programmed.
PD is data to be programmed at byte address.
DQ7# is the output of the complement of the data written to the device.
OUT is the output of the data written to the device.
Figure indicates last two bus cycles of four bus cycle sequence.
D
ERASE AND PROGRAMMING PERFORMANCE
Limits
Parameter
Unit
Comments
Min
Typ
1 (Note 1)
32
Max
8
Sector Erase Time
sec
sec
μs
Excludes 00H programming prior to erasure
Excludes 00H programming prior to erasure
Excludes system-level overhead
Chip Erase Time
256
Byte Programming Time
Chip Programming Time
7
300 ( Note 3)
43.2 (Notes 2, 3)
14.4 (Note 1)
sec
Excludes system-level overhead
Notes:
1.
2.
25°C, 5V VCC, 100,000 cycles.
Although Embedded Algorithms allow for a longer chip program and erase time, the actual time will be considerably less since bytes program or erase significantly faster than the
worst case byte.
3.
Under worst case condition of 90°C, 4.5 V VCC, 100,000 cycles.
January 2006
Rev. 1
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EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
LATCHUP CHARACTERISTIC
Min
Max
Input Voltage with respect to VSS on I/O pin
VCC Current
-1.0 V
-100mA
VCC + 1.0 V
+100 mA
Notes:
• Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.
CAPACITANCE
(f = 1.0 MHz, VIN = VCC or VSS
)
2x2xMx8
4x2Mx8
Parameter
Sym
Unit
Max
20
Max
35
Address Lines
Data Lines
CA
CDQ
CC
pF
pF
pF
pF
30
50
Chip & Write Enable Lines
Output Enable Lines
12
12
CG
20
40
January 2006
Rev. 1
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
ORDERING INFORMATION
EDI7292MC
Part Number
Speed (ns)
100
Package
361
TA Commercial Range
0°C to +70°C
Height*
EDI7292MC100BNC
EDI7292MC120BNC
21.59 (0.850")
21.59 (0.850")
120
361
0°C to +70°C
EDI7492MC
Part Number
EDI7492MC100BNI
EDI7492MC120BNI
Notes:
Speed (ns)
100
Package
361
TA Industrial Range
0°C to +70°C
Height*
21.59 (0.850")
21.59 (0.850")
120
361
0°C to +70°C
• Consult factors for availability of lead-free or RoHS products.
• Consult factors for availability of industrail temp (-40°C to 85°C) option.
EDI7292MC
118.24
(4.655) MAX.
3.05
(0.120)
MAX
111.35
(4.384)
21.59
R1 R3
J3
(0.850)
J1
MAX
10.16
6.35
153
(0.400)
(0.250)
1.27
6.35 (0.250)
1.57 (0.062) R
(0.050) TYP
3.18 5.72
(0.125) (0.225)
MIN MIN
105.41
(4.150)
1.57
(0.062) R
55.68
57.02
(2.192)
(2.245)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
EDI7492MC
118.24
(4.655) MAX.
4.32
111.35
(4.384)
(0.170)
MAX
21.59
R1 R3
J3
(0.850)
MAX
J1
10.16
6.35
153
(0.400)
(0.250)
1.27
(0.050) TYP
6.35 (0.250)
1.57 (0.062) R
3.18 5.72
105.41
(4.150)
1.57
(0.125) (0.225)
MIN MIN
(0.062) R
55.68
57.02
(2.245)
(2.192)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
January 2006
Rev. 1
31
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
PART NUMBERING GUIDE
EDI 7 F 292M/492M C xxx BN X
WEDC
FLASH
FR4 WITH TIN LEAD CONTACTS
MODULE BUS WIDTH: x8
VOLTAGE; 5V (CMOS)
SPEED: 100, 120ns
PACKAGE: 80 Pin SIMM
TEMPERATURE RANGE
C = 0˚C to 70˚C Commercial
I = -40˚C to 85˚C Industrial
January 2006
Rev. 1
32
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI7F292MC
EDI7F492MC
PRELIMINARY
White Electronic Designs
Document Title
4MB/8MB Flash Module (2x2Mx8) & (4x2Mx8)
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Created
5-02
1-06
Advanced
Final
Updated datasheet
January 2006
Rev. 1
33
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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