EDI88257CA55CB [WEDC]

Standard SRAM, 256KX8, 55ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32;
EDI88257CA55CB
型号: EDI88257CA55CB
厂家: WHITE ELECTRONIC DESIGNS CORPORATION    WHITE ELECTRONIC DESIGNS CORPORATION
描述:

Standard SRAM, 256KX8, 55ns, CMOS, CDIP32, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-32

CD 静态存储器
文件: 总6页 (文件大小:258K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
EDI88257CA  
White Electronic Designs  
256Kx8 Monolithic SRAM  
FEATURES  
The EDI88257CA is a 2 Megabit 256Kx8 bit Monolithic  
CMOS Static RAM.  
„
„
„
„
„
„
Access Times of 20, 25, 35, 45, 55ns  
Data Retention Function (LPA Versions)  
TTL Compatible Inputs and Outputs  
Fully Static, No Clocks  
The 32 pin DIP pinout adheres to the JEDEC evolutionary  
standard for the two megabit device. The device is  
upgradeable to the 512Kx8 SRAM, the EDI88512CA. Pin  
1 becomes the higher order address.  
Organized as 256Kx8  
ALow Power version, EDI88257LPA, offers a data retention  
function for battery back-up opperation. Military product is  
available compliant to Appendix A of MIL-PRF-38535.  
Commercial, Industrial and Military Temperature  
Ranges  
„
„
JEDEC Approved Evolutionary Pinout  
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)  
Single +5V (±10%) Supply Operation  
This product is subject to change without notice.  
FIGURE 1 – PIN CONFIGURATION  
32 DIP  
PIN DESCRIPTION  
TOP VIEW  
I/O0-7  
A0-17  
WE#  
CS#  
OE#  
VCC  
Data Inputs/Outputs  
Address Inputs  
Write Enable  
NC  
A16  
A14  
A12  
A7  
1
2
3
4
5
6
7
8
9
32 VCC  
31 A15  
30 A17  
29 WE#  
28 A13  
27 A8  
Chip Selects  
Output Enable  
Power (+5V ±10%)  
Ground  
A6  
A5  
26 A9  
VSS  
A4  
25 A11#  
24 OE  
A3  
NC  
Not Connected  
A2 10  
A1 11  
A0 12  
I/O0 13  
I/O1 14  
I/O2 15  
VSS 16  
23 A10  
22 CS#  
21 I/O7  
20 I/O6  
19 I/O5  
18 I/O4  
17 I/O3  
BLOCK DIAGRAM  
Memory Array  
Address  
Buffer  
Address  
Decoder  
I/O  
Circuits  
A
0-17  
I/O0-7  
WE#  
CS  
OE#  
White Electronic Designs Corp. reserves the right to change products or specications without notice.  
May 2000  
Rev. 2  
1
White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com  
EDI88257CA  
White Electronic Designs  
ABSOLUTE MAXIMUM RATINGS  
TRUTH TABLE  
Parameter  
Voltage on any pin relative to Vss  
Value  
-0.5 to 7.0  
Unit  
V
OE#  
X
H
L
X
CS#  
H
L
L
L
WE#  
X
H
H
L
Mode  
Standby  
Output Deselect  
Read  
Output  
High Z  
High Z  
Data Out  
Data In  
Power  
CC2, ICC3  
ICC1  
ICC1  
ICC1  
I
Operating Temperature TA (Ambient)  
Industrial  
Military  
Storage Temperature, Ceramic  
Power Dissipation  
-40 to +85  
-55 to +125  
-65 to +150  
1.5  
°C  
°C  
°C  
W
Write  
RECOMMENDED OPERATING CONDITIONS  
Output Current  
Junction Temperature, TJ  
20  
175  
mA  
°C  
Parameter  
Symbol  
VCC  
VSS  
Min  
4.5  
0
Typ  
5.0  
0
Max  
5.5  
0
Unit  
V
V
Supply Voltage  
Supply Voltage  
Input High Voltage  
Input Low Voltage  
NOTE:  
Stress greater than those listed under “Absolute Maximum Ratings” may cause  
permanent damage to the device. This is a stress rating only and functional operation  
of the device at these or any other conditions greater than those indicated in the  
operational sections of this specication is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect reliability.  
VIH  
VIL  
2.2  
-0.3  
VCC +0.5  
+0.8  
V
V
CAPACITANCE  
Parameter  
Address Lines  
Data Lines  
Symbol  
CI  
CO  
Condition  
VIN = Vcc or Vss, f = 1.0MHz  
VOUT = Vcc or Vss, f = 1.0MHz 14  
Max Unit  
12  
pF  
pF  
These parameters are sampled, not 100% tested.  
DC CHARACTERISTICS  
VCC = 5V, TA = +25°C  
Parameter  
Input Leakage Current  
Output Leakage Current  
Symbol  
ILI  
ILO  
Conditions  
VIN = 0V to VCC  
VI/O = 0V to VCC  
Min  
-10  
-10  
2.4  
Typ  
Max  
+10  
+10  
225  
200  
60  
25  
20  
0.4  
Units  
μA  
μA  
mA  
mA  
mA  
mA  
mA  
V
(20-25ns)  
(35-55ns)  
Operating Power Supply Current  
Standby (TTL) Power Supply Current  
Full Standby Power Supply Current  
ICC1  
ICC2  
ICC3  
WE#, CS# = VIL, II/O = 0mA, Min Cycle  
CS# VIH, VIN VIL, VIN VIH  
CS# VCC -0.2V  
VIN Vcc -0.2V or VIN 0.2V  
IOL = 8.0mA  
IOH = -4.0mA  
C
LP  
Output Low Voltage  
Output High Voltage  
VOL  
VOH  
V
AC TEST CONDITIONS  
Input Pulse Levels  
VSS to 3.0V  
5ns  
Figure 1  
Figure 2  
Vcc  
Vcc  
Input Rise and Fall Times  
Input and Output Timing Levels  
Output Load  
1.5V  
480Ω  
480Ω  
Figure 1  
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2  
Q
Q
30pF  
5pF  
255Ω  
255Ω  
White Electronic Designs Corp. reserves the right to change products or specications without notice.  
May 2000  
Rev. 2  
2
White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com  
EDI88257CA  
White Electronic Designs  
AC CHARACTERISTICS – READ CYCLE  
VCC = 5.0V, Vss = 0V, -55°C TA +125°C  
Symbol  
20ns 25ns  
35ns  
45ns  
55ns  
Parameter  
JEDEC Alt.  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max Units  
Read Cycle Time  
tAVAV  
tAVQV  
tELQV  
tELQX  
tEHQZ  
tAVQX  
tGLQV  
tGLQX  
tGHQZ  
tRC  
tAA  
20  
25  
35  
45  
55  
ns  
Address Access Time  
20  
20  
25  
25  
35  
35  
45  
45  
55  
55  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable Access Time  
tACS  
tCLZ  
tCHZ  
tOH  
Chip Enable to Output in Low Z (1)  
Chip Disable to Output in High Z (1)  
Output Hold from Address Change  
Output Enable to Output Valid  
Output Enable to Output in Low Z (1)  
Output Disable to Output in High Z(1)  
3
0
0
3
0
0
3
0
0
3
0
0
3
0
0
8
10  
8
10  
12  
10  
15  
15  
15  
20  
25  
20  
20  
25  
20  
tOE  
tOLZ  
tOHZ  
0
0
0
0
0
0
0
0
0
0
1. This parameter is guaranteed by design but not tested.  
AC CHARACTERISTICS – WRITE CYCLE  
VCC = 5.0V, VSS = 0V, -55°C TA +125°C  
Symbol  
20ns  
25ns  
35ns  
45ns  
55ns  
Parameter  
JEDEC Alt.  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max Units  
Write Cycle Time  
tAVAV  
tWC  
20  
25  
35  
45  
55  
ns  
Chip Enable to End of Write  
tELWH  
tELEH  
tCW  
tCW  
15  
15  
17  
17  
25  
25  
30  
30  
30  
30  
ns  
ns  
Address Setup Time  
tAVWL  
tAVEL  
tAS  
tAS  
0
0
0
0
0
0
0
0
0
0
ns  
ns  
Address Valid to End of Write  
Write Pulse Width  
tAVWH  
tAVEH  
tAW  
tAW  
15  
15  
17  
17  
25  
25  
30  
30  
30  
30  
ns  
ns  
tWLWH  
tWLEH  
tWP  
tWP  
15  
15  
17  
17  
25  
25  
30  
30  
30  
30  
ns  
ns  
Write Recovery Time  
Data Hold Time  
tWHAX  
tEHAX  
tWR  
tWR  
0
0
0
0
0
0
0
0
0
0
ns  
ns  
tWHDX  
tEHDX  
tDH  
tDH  
0
0
0
0
0
0
0
0
0
0
ns  
ns  
Write to Output in High Z (1)  
Data to Write Time  
tWLQZ  
tWHZ  
0
30  
0
30  
0
25  
0
30  
0
30  
ns  
tDVWH  
tDVEH  
tDW  
tDW  
10  
10  
12  
12  
20  
20  
25  
25  
25  
25  
ns  
ns  
Output Active from End of Write (1)  
tWHQX  
tWLZ  
0
0
0
0
0
ns  
1. This parameter is guaranteed by design but not tested.  
White Electronic Designs Corp. reserves the right to change products or specications without notice.  
May 2000  
Rev. 2  
3
White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com  
EDI88257CA  
White Electronic Designs  
FIGURE 2 – TIMING WAVEFORM - READ CYCLE  
tAVAV  
ADDRESS  
CS#  
tAVQV  
tAVAV  
tEHQZ  
tELQV  
tELQX  
ADDRESS  
DATA I/O  
ADDRESS 1  
ADDRESS 2  
OE#  
tGLQV  
tGLQX  
tGHQZ  
tAVQV  
t
AVQX  
DATA OUT  
DATA 1  
DATA 2  
READ CYCLE 2 (WE# HIGH)  
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)  
FIGURE 3 – WRITE CYCLE - WE# CONTROLLED  
tAVAV  
ADDRESS  
tAVWH  
tWHAX  
tELWH  
CS#  
tAVWL  
tWLWH  
WE#  
tDVWH  
tWHDX  
DATA IN  
DATA VALID  
tWLQZ  
tWHQX  
HIGH Z  
DATA OUT  
WRITE CYCLE 1, WE# CONTROLLED  
FIGURE 4 – WRITE CYCLE - CS# CONTROLLED  
tAVAV  
ADDRESS  
tAVEH  
tEHAX  
tELEH  
CS#  
tAVEL  
tWLEH  
WE#  
tDVEH  
tEHDX  
DATA IN  
DATA VALID  
HIGH Z  
WRITE CYCLE 2, CS# CONTROLLED  
DATA OUT  
White Electronic Designs Corp. reserves the right to change products or specications without notice.  
May 2000  
Rev. 2  
4
White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com  
EDI88257CA  
White Electronic Designs  
DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY)  
-55°C TA +125°C  
Characteristic  
Sym  
Conditions  
Min  
Typ  
Max  
Units  
Low Power Version only  
Data Retention Voltage  
Data Retention Quiescent Current  
VCC  
ICCDR  
VCC = 2.0V  
CS# VCC -0.2V  
2
2
V
μA  
Chip Disable to Data Retention Time  
Operation Recovery Time  
tCDR  
TR  
VIN VCC -0.2V  
or VIN 0.2V  
0
tAVAV  
ns  
ns  
FIGURE 5 – DATA RETENTION - CS# CONTROLLED  
DATA RETENTION MODE  
4.5V  
4.5V  
VCC  
VCC  
tCDR  
tR  
CS#  
CS# = VCC -0.2V  
DATA RETENTION, CS# CONTROLLED  
White Electronic Designs Corp. reserves the right to change products or specications without notice.  
May 2000  
Rev. 2  
5
White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com  
EDI88257CA  
White Electronic Designs  
PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600mils wide)  
1.616  
1.584  
0.620  
0.600  
0.060  
0.040  
Pin 1 Indicator  
0.200  
0.125  
0.155  
0.115  
0.600  
NOM  
0.020  
0.016  
0.100  
TYP  
0.061  
0.017  
15 x 0.100 = 1.500  
ALL DIMENSIONS ARE IN INCHES  
ORDERING INFORMATION  
EDI 8 8257 CA X X X  
WHITE ELECTRONIC DESIGNS  
SRAM  
ORGANIZATION, 256Kx8  
TECHNOLOGY:  
CA = CMOS Standard Power  
LPA = Low Power  
ACCESS TIME (ns)  
PACKAGE TYPE:  
C = 32 lead Sidebrazed DIP, 600 mil (Package 9)  
DEVICE GRADE:  
B = MIL-STD-883 Compliant  
M= Military Screened  
I = Industrial  
C = Commercial  
-55°C to +125°C  
-40°C to +85°C  
0°C to +70°C  
White Electronic Designs Corp. reserves the right to change products or specications without notice.  
May 2000  
Rev. 2  
6
White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com  

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