EDI88512LPA17RJCG [WEDC]
Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, ROHS COMPLIANT, PLASTIC, SOJ-36;
| 型号： | EDI88512LPA17RJCG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Standard SRAM, 512KX8, 17ns, CMOS, PDSO36, ROHS COMPLIANT, PLASTIC, SOJ-36 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI88512CA-XMXG
WPS512K8X-XRJXG
White Electronic Designs
512Kx8 Plastic Monolithic SRAM CMOS
WEDC's ruggedized plastic 512Kx8 SRAM that allows
the user to capitalize on the cost advantage of using a
plastic component while not sacrificing all of the reliability
available in a full military device.
FEATURES
■
512Kx8 bit CMOS Static
■
Random Access Memory
Extended temperature testing is performed with the test
patterns developed for use on WEDC’s fully compliant
512Kx8 SRAMs. WEDC fully characterizes devices
to determine the proper test patterns for testing at
temperature extremes. This is critical because the
operating characteristics of device change when it is
operated beyond the commercial guarantee a device that
operates reliably in the field at temperature extremes.
Users of WEDC’s ruggedized plastic benefit from WEDC’s
extensive experience in characterizing SRAMs for use in
military systems.
• Access Times of 17, 20, 25ns
• Data Retention Function (LPA version)
• Extended Temperature Testing
• Data Retention Functionality Testing
36 lead JEDEC Approved Revolutionary Pinout
• Plastic SOJ (Package 319)
■
■
■
Single +5V (±10%) Supply Operation
RoHS compliant
WEDC ensures Low Power devices will retain data in Data
Retention mode by characterizing the devices to determine
the appropriate test conditions. This is crucial for systems
operating at -40°C or below and using dense memories
such as 512Kx8s.
WEDC’s ruggedized plastic SOJ is footprint compatible
with WEDC’s full military ceramic 36 pin SOJ.
FIG. 1 – PIN CONFIGURATION
PIN Description
TOP VIEW
I/O0-7
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
A0-18
WE#
CS#
OE#
VCC
A0
A1
1
2
3
4
5
6
7
8
9
36 NC
35 A18
34 A17
33 A16
32 A15
31 OE#
30 I/O7
29 I/O6
28 VSS
27 VCC
26 I/O5
25 I/O4
24 A14
23 A13
22 A12
21 A11
20 A10
19 NC
A2
A3
A4
CS#
I/O0
I/O1
VCC
Output Enable
Power (+5V ±10%)
Ground
BLOCK DIAGRAM
36pin
VSS
VSS 10
I/O2 11
I/O3 12
WE# 13
A5 14
Revolutionary
NC
Not Connected
Memory Array
A6 15
A7 16
A8 17
Address
Buffer
Address
Decoder
I/O
A
Ø-18
I/OØ-7
Circuits
A9 18
WE#
CS#
OE#
December 2008
Rev. 7
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512CA-XMXG
WPS512K8X-XRJXG
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Mode
Standby
Output
High Z
Power
Icc2, Icc3
Icc1
Parameter
Unit
OE# CS# WE#
Voltage on any pin relative to Vss
Operating Temperature TA (Ambient)
Commercial
-0.5 to 7.0
V
X
H
L
H
L
L
L
X
H
H
L
Output Deselect
Read
High Z
0 to +70
-40 to +85
-55 to +125
-65 to +150
1.5
°C
°C
°C
°C
W
Data Out
Data In
Icc1
Industrial
Write
Icc1
X
Military
Storage Temperature, Plastic
Power Dissipation
RECOMMENDED OPERATING CONDITIONS
Output Current
20
mA
°C
Parameter
Symbol Min
Typ
5.0
0
Max
5.5
Unit
Junction Temperature, TJ
175
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
VCC
VSS
VIH
VIL
4.5
0
V
V
V
V
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
0
2.2
-0.3
—
VCC + 0.5
+0.8
—
CAPACITANCE
TA = +25°C
Parameter Symbol
Condition
Max Unit
Address Lines
Data Lines
CI
VIN = Vcc or Vss, f = 1.0MHz
VIN = Vcc or Vss, f = 1.0MHz
6
8
pF
pF
CO
These parameters are sampled, not 100% tested.
DC CHARACTERISTICS
VCC = 5V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
ILI
ILO
ICC
ISB
Conditions
Min
Max
Units
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
VCC = 5.5, VIN = VSS to VCC
10
10
μA
μA
mA
mA
V
CS# = VIL, OE# = VIH, VOUT = VSS to VCC
CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5
CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
IOH = -4.0mA, VCC = 4.5
180
15
Output High Volltage
Output Low Voltage
VOH
VOL
2.4
IOL = 8.0mA, VCC = 4.5
0.4
V
NOTE: DC test conditions: VIL = 0.3V, VIH = VCC -0.3V
AC TEST CONDITIONS
Figure 1
Figure 2
Vcc
Vcc
Input Pulse Levels
Input Rise and Fall Times
VSS to 3.0V
5ns
1.5V
480Ω
30pF
480Ω
5pF
Input and Output Timing Levels
Output Load
Figure 1
Q
Q
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF (Figure 2)
255Ω
255Ω
December 2008
Rev. 7
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512CA-XMXG
WPS512K8X-XRJXG
White Electronic Designs
AC CHARACTERISTICS – READ CYCLE
VCC = 5.0V, VSS = 0V, 0°C ≤ TA ≤ +70°C
Symbol 17ns
20ns
25ns
Parameter
JEDEC
tAVAV
Alt.
tRC
Min
Max
Min
Max
Min
Max
Units
ns
Read Cycle Time
17
20
25
Address Access Time
tAVQV
tELQV
tAA
17
17
20
20
25
25
ns
Chip Enable Access Time
tACS
tCLZ
tCHZ
tOH
ns
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
1. This parameter is guaranteed by design but not tested.
tELQX
3
0
0
3
0
0
3
0
0
ns
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
7
8
7
8
10
8
10
12
10
ns
ns
tOE
ns
tOLZ
tOHZ
0
0
0
0
0
0
ns
ns
AC CHARACTERISTICS – WRITE CYCLE
VCC = 5.0V, VSS = 0V, 0°C ≤ TA ≤ +70°C
Symbol
JEDEC
17ns
20ns
25ns
Parameter
Alt.
tWC
Min
17
Max
Min
20
Max
Min
25
Max
Units
ns
Write Cycle Time
Chip Enable to End of Write
tAVAV
tELWH
tELEH
tCW
tCW
14
14
15
15
17
17
ns
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAVWL
tAVEL
tAS
tAS
0
0
0
0
0
0
ns
ns
tAVWH
tAVEH
tAW
tAW
14
14
15
15
17
17
ns
ns
tWLWH
tWLEH
tWP
tWP
14
14
15
15
17
17
ns
ns
Write Recovery Time
Data Hold Time
tWHAX
tEHAX
tWR
tWR
0
0
0
0
0
0
ns
ns
tWHDX
tEHDX
tDH
tDH
0
0
0
0
0
0
ns
ns
Write to Output in High Z (1)
Data to Write Time
tWLQZ
tWHZ
0
8
0
8
0
10
ns
tDVWH
tDVEH
tDW
tDW
8
8
10
10
12
12
ns
ns
Output Active from End of Write (1)
tWHQX
tWLZ
0
0
0
ns
1. This parameter is guaranteed by design but not tested.
December 2008
Rev. 7
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512CA-XMXG
WPS512K8X-XRJXG
White Electronic Designs
FIG. 2 – TIMING WAVEFORM — READ CYCLE
tAVAV
ADDRESS
tAVQV
CS#
tAVAV
tEHQZ
tELQV
tELQX
ADDRESS
DATA I/O
ADDRESS 1
ADDRESS 2
OE#
tGLQV
tGLQX
tGHQZ
tAVQV
tAVQX
DATA OUT
DATA 1
DATA 2
READ CYCLE 2 (WE# HIGH)
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
FIG. 3 – WRITE CYCLE — WE# CONTROLLED
tAVAV
ADDRESS
tAVWH
tWHAX
tELWH
CS#
tAVWL
tWLWH
WE#
tDVWH
tWHDX
DATA IN
DATA VALID
tWLQZ
tWHQX
HIGH Z
DATA OUT
WRITE CYCLE 1, WE# CONTROLLED
FIG. 4 – WRITE CYCLE — CS# CONTROLLED
tAVAV
ADDRESS
WS32K32-XHX
tAVEH
tEHAX
tELEH
CS#
tAVEL
tWLEH
WE#
tDVEH
tEHDX
DATA IN
DATA VALID
HIGH Z
DATA OUT
WRITE CYCLE 2, CS# CONTROLLED
December 2008
Rev. 7
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512CA-XMXG
WPS512K8X-XRJXG
White Electronic Designs
DATA RETENTION CHARACTERISTICS (EDI88512LPA ONLY)
-55°C ≤ TA ≤ +125°C
Characteristic
Sym
Conditions
Min
Typ
Max
Units
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
VDD
ICCDR
VDD = 2.0V
CS# ≥ VDD -0.2V
2
–
–
–
–
15
V
mA
Chip Disable to Data Retention Time
Operation Recovery Time
TCDR
TR
VIN ≥ VDD -0.2V
or VIN ≤ 0.2V
0
–
–
–
ns
ns
TAVAV
FIG. 5 – DATA RETENTION - CS# CONTROLLED
Data Retention Mode
4.5V
4.5V
Vcc
VDD
tCDR
tR
CS#
CS# = VDD -0.2V
DATA RETENTION, CS# CONTROLLED
December 2008
Rev. 7
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512CA-XMXG
WPS512K8X-XRJXG
White Electronic Designs
FIG. 6 – NORMALIZED OPERATING GRAPHS
Write Pulse Width vs. Temp.
ICC1 (20ns) vs Temp
14
13
12
11
10
9
220
210
200
190
180
170
160
8
7
6
-55
25
125
-55
25
125
Temp. (C)
Temp. (C)
TAVQV vs. Temp
ICC3 vs. Temp
10
1
22
20
18
190
16
14
12
0.1
0.01
-55
25
Temp. (C)
125
-55
25
Temp. (C)
125
ICCDR vs. Temp
10
1
Normalized curves are offered
as a service to our customers.
They are not to be construed
as a guarantee of operating
characterics.
0.1
Characteristics of actual
devices will vary.
0.01
0.001
-55
25
125
Temp. (C)
IDR, 2V
IDR, 3V
December 2008
Rev. 7
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512CA-XMXG
WPS512K8X-XRJXG
White Electronic Designs
PACKAGE 319: 36 LEAD, PLASTIC SMALL OUTLINE J-LEAD (SOJ)
0.920
0.930
0.395
0.405
0.360 0.435
0.380 0.445
0.026
0.032
Pin 1 Indicator
0.027
min.
0.148
max.
0.375
TYP.
0.050
TYP.
0.015
0.021
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION
EDI 8 8 512 CA X X X G
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 512Kx8
TECHNOLOGY:
CA = CMOS Standard Power
LPA = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
M = 36 lead Plastic SOJ
RJ = Relvoutionary
DEVICE GRADE:
B = MIL-STD-883 Compliant
M= Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
RoHS COMPLIANT:
December 2008
Rev. 7
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512CA-XMXG
WPS512K8X-XRJXG
White Electronic Designs
ORDERING INFORMATION
W P S 512K 8 X X - XXX RJ X G
WHITE ELECTRONIC DESIGNS CORP.
PLASTIC PLUS®
SRAM
ORGANIZATION, 512K x 8
Blank = Standard Power
L = Low Power
IMPROVEMENT MARK:
B = Burn-in
T = Temperature Cycling
C = Burn-in and Temperature Cycle
ACCESS TIME (ns):
PACKAGE:
RJ = Revolutionary
DEVICE GRADE:
M = Military Temperature
I = Industrial Temperature
-55°C to +125°C
-40°C to +85°C
RoHS COMPLIANT:
December 2008
Rev. 7
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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