概述
数据手册EDI88512LPXCI 概述
512Kx8 Monolithic SRAM, CMOS 512Kx8单片SRAM ， CMOS
EDI88512LPXCI 数据手册
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White Electronic Designs
512Kx8 Monolithic SRAM, CMOS
FEATURES
The EDI88512C is a 4 megabit Monolithic CMOS Static
RAM.
ꢀ
512Kx8 bit CMOS Static
ꢀ
Random Access Memory
The 32 pin DIP pinout adheres to the JEDEC evolutionary
standard for the four megabit device. Both the DIP and
CSOJ packages are pin for pin upgrades for the single chip
enable 128K x 8, the EDI88128C. Pins 1 and 30 become
the higher order addresses.
• Access Times of 70, 85, 100ns
• Data Retention Function (LP version)
• TTL Compatible Inputs and Outputs
• Fully Static, No Clocks
A Low Power version with Data Retention (EDI88512LP)
is also available for battery backed applications. Military
product is available compliant to Appendix A of MIL-PRF-
38535.
ꢀ
ꢀ
32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic SOJ (Package 140)
Single +5V ( 10ꢀ) Supply Operation
* This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
PIN DESCRIPTION
I/O0-7
A0-18
WE#
CS#
OE#
VCC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V 10ꢀ%
Ground
32 PIN
TOP VIEW
32 Vcc
31 A15
30 A17
29 WE#
28 A13
27 A8
A18
A16
A14
A12
A7
1
2
3
VSS
4
5
NC
Not Connected
A6
6
26 A9
A5
7
32 pin
Evolutionary
25 A11
24 OE#
23 A10
22 CS#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
8
A4
9
A3
BLOCK DIAGRAM
10
11
12
13
14
A2
A1
A0
Memory Array
I/O0
I/O1
I/O2 15
Vss
16
Address
Buffer
Address
Decoder
I/O
A0-18
I/O0-7
Circuits
WE#
CS#
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2001
Rev. 11
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512C
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Value
Unit
OE#
X
CS#
H
WE#
X
Mode
Output
High Z
High Z
Data Out
Data In
Power
ICC2, ICC3
ICC1
Voltage on any pin relative to Vss
Operating Temperature TA (Ambient%
Commercial
-0.5 to 7.0
V
Standby
H
L
H
Output Deselect
0 to +70
-40 to +85
-55 to +125
-65 to +150
1
°C
°C
°C
°C
W
mA
°C
L
X
L
L
H
L
Read
Write
ICC1
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, TJ
NOTE:
Stress greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
ICC1
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
20
175
Symbol
Min
4.5
0
2.2
-0.3
Typ
5.0
0
Max
Unit
VCC
5.5
V
VSS
0
V
VIH
VIL
—
VCC +0.5
+0.8
V
—
V
CAPACITANCE
TA = +25°C
Parameter
Address Lines
Data Lines
Symbol
Condition
Max Unit
CI
VIN = Vcc or Vss, f = 1.0MHz
12
pF
pF
CO
VOUT = Vcc or Vss, f = 1.0MHz 14
These parameters are sampled, not 100ꢀ tested.
DC CHARACTERISTICS
VCC = 5V, -55°C ≤ *TA ≤ +125°C
Parameter
Symbol
ILI
Conditions
Min
—
Typ*
—
—
45
3
—
—
—
—
Max
10
10
75
10
5
Units
µA
µA
mA
mA
mA
mA
V
Input Leakage Current
VIN = 0V to VCC
Output Leakage Current
ILO
VI/O = 0V to VCC
WE#, CS# = VIL, II/O = 0mA, Min Cycle (70-100ns%
CS# ≥ VIH, VIN ≤ VIL, VIN ≥ VIH
—
Operating Power Supply Current
Standby (TTL% Power Supply Current
Full Standby Power Supply Current
ICC1
ICC2
ICC3
—
—
CS# ≥ VCC -0.2V
VIN ≥ Vcc -0.2V or VIN ≤ 0.2V
IOL = 2.1mA
C
LP
—
—
2
Output Low Voltage
Output High Voltage
VOL
VOH
—
0.4
—
IOH = -1.0mA
2.4
V
NOTE: DC test conditions: Vil = 0.3V, Vih = Vcc -0.3V
AC TEST CONDITIONS
Input Pulse Levels
VSS to 3.0V
5ns
Figure 1
Figure 2
Vcc
Vcc
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
1.5V
480Ω
480Ω
Figure 1
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
Q
Q
30pF
5pF
255Ω
255Ω
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2001
Rev. 11
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512C
White Electronic Designs
AC CHARACTERISTICS – READ CYCLE
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Symbol 70ns
JEDEC
85ns
100ns
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1%
Alt.
tRC
Min
Max
Min
85
Max
Min
100
Max
Units
ns
ns
ns
ns
tAVAV
tAVQV
tELQV
tELQX
70
tAA
tACS
tCLZ
70
70
85
85
100
100
10
10
10
10
10
10
Chip Disable to Output in High Z (1%
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1%
Output Disable to Output in High Z(1%
1. This parameter is guaranteed by design but not tested.
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tCHZ
tOH
25
35
25
30
45
30
30
50
30
ns
ns
ns
ns
ns
tOE
tOLZ
tOHZ
5
0
5
0
5
0
AC CHARACTERISTICS – WRITE CYCLE
VCC = 5.0V, VSS = 0V, -55°C≤ TA ≤ +125°C
Symbol
JEDEC
70ns
85ns
100ns
Parameter
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
tAVAV
tWC
70
85
100
ns
Chip Enable to End of Write
tELWH
tELEH
tCW
tCW
60
60
70
70
80
80
ns
ns
Address Setup Time
tAVWL
tAVEL
tAS
tAS
0
0
0
0
0
0
ns
ns
Address Valid to End of Write
Write Pulse Width
tAVWH
tAW
tAW
tWP
tWP
65
65
50
50
70
70
55
55
80
80
60
60
ns
ns
ns
ns
tAVEH
tWLWH
tWLEH
Write Recovery Time
Data Hold Time
tWHAX
tEHAX
tWR
tWR
tDH
tDH
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
tWHDX
tEHDX
Write to Output in High Z (1%
Data to Write Time
tWLQZ
tWHZ
tDW
tDW
0
40
30
25
0
40
35
30
0
40
40
30
ns
ns
ns
tDVWH
tDVEH
Output Active from End of Write (1%
tWHQX
tWLZ
5
0
0
ns
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2001
Rev. 11
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512C
White Electronic Designs
FIGURE 2 – TIMING WAVEFORM - READ CYCLE
tAVAV
ADDRESS
tAVQV
CS#
tAVAV
tEHQZ
tELQV
ADDRESS
DATA I/O
tELQX
ADDRESS 1
ADDRESS 2
OE#
tGLQV
tGLQX
tGHQZ
tAVQV
tAVQX
DATA OUT
DATA 1
DATA 2
READ CYCLE 2 (WE# HIGH)
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
FIGURE 3 – WRITE CYCLE - WE# CONTROLLED
tAVAV
ADDRESS
tAVWH
tWHAX
tELWH
CS#
tAVWL
tWLWH
WE#
tDVWH
tWHDX
DATA IN
DATA VALID
tWLQZ
tWHQX
HIGH Z
DATA OUT
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE - CS# CONTROLLED
tAVAV
ADDRESS
tAVEH
tEHAX
tELEH
CS#
tAVEL
tWLEH
WE#
tDVEH
tEHDX
DATA IN
DATA VALID
HIGH Z
WRITE CYCLE 2, CS# CONTROLLED
DATA OUT
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2001
Rev. 11
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512C
White Electronic Designs
DATA RETENTION CHARACTERISTICS (EDI88512LP ONLY)
-55°C ≤ TA ≤ +125°C
Characteristic
Low Power Version only
Sym
Conditions
Min
Typ
Max
Units
Data Retention Voltage
Data Retention Quiescent Current
VCC
ICCDR
VCC = 2.0V
CS# ≥ VCC -0.2V
2
–
–
–
–
185
V
µA
Chip Disable to Data Retention Time
Operation Recovery Time
tCDR
TR
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
0
tAVAV
–
–
–
–
ns
ns
FIGURE 5 – DATA RETENTION - CS# CONTROLLED
DATA RETENTION MODE
4.5V
4.5V
VCC
VCC
tCDR
tR
CS#
CS# = VCC -0.2V
DATA RETENTION, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2001
Rev. 11
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512C
White Electronic Designs
PACKAGE 9: 32 LEAD SIDEBRAZED CERAMIC DIP
1.616
1.584
0.620
0.600
0.060
0.040
Pin 1 Indicator
0.200
0.125
0.155
0.115
0.600
NOM
0.020
0.016
0.100
TYP
0.061
0.017
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
PACKAGE 140: 32 LEAD CERAMIC SOJ
0.010
0.006
0.019
0.015
0.840
0.820
0.050
TYP
0.444
0.430
0.379
0.155
0.106
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2001
Rev. 11
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88512C
White Electronic Designs
ORDERING INFORMATION
EDI 8 8512 C X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 512Kx8
TECHNOLOGY:
C
= CMOS Standard Power
LP = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
C
N
= 32 lead Sidebrazed DIP, 600 mil (Package 9)
= 32 lead Ceramic SOJ (Package 140)
DEVICE GRADE:
B
M
I
= MIL-STD-883 Compliant
= Military Screened
= Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C
= Commercial
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2001
Rev. 11
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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