EDI9LC644V [WEDC]
128Kx32 SSRAM/1Mx32 SDRAM; 128Kx32 SSRAM / SDRAM 1Mx32
| 型号： | EDI9LC644V |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 128Kx32 SSRAM/1Mx32 SDRAM |
| 文件： | 总25页 (文件大小：1544K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS TMS320C6000 DSP
n Clock speeds:
The EDI9LC644VxxBC is a 3.3V, 128K x 32 Synchronous
Pipeline SRAM and a 1Mx32 Synchronous DRAM array con-
structed with one 128K x 32 SBSRAM and two 1Mx16
SDRAM die mounted on a multilayer laminate substrate. The
device is packaged in a 153 lead, 14mm by 22mm, BGA.
• SSRAM: 200, 166,150, and 133 MHz
• SDRAMs: 125 and 100 MHz
n DSP Memory Solution
• Texas Instruments TMS320C6201
• Texas Instruments TMS320C6701
n Packaging:
The EDI9LC644VxxBC provides a total memory solution for
the Texas Instruments TMS320C6201 and the
TMS320C6701 DSPs
The Synchronous Pipeline SRAM is available with clock
speeds of 200, 166,150, and 133 MHz, allowing the user
to develop a fast external memory for the SSRAM inter-
face port .
• 153 pin BGA, JEDEC MO-163
n 3.3V Operating supply voltage
n Direct control interface to both the SSRAM and SDRAM
ports on the “C6x”
The SDRAM is available in clock speeds of 125 and 100
MHz, allowing the user to develop a fast external memory
for the SDRAM interface port .
n Common address and databus
n 65% space savings vs. monolithic solution
n Reduced system inductance and capacitance
PIN CONFIGURATION
A0-16
DQ0-31
SSCLK
SSADC
SSWE
Address Bus
Data Bus
DQ19 DQ23
DQ18 DQ22
VCCQ VCCQ
DQ17 DQ21
DQ16 DQ20
VCCQ VCCQ
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
A2
DQ24 DQ28
DQ25 DQ29
VCCQ VCCQ
DQ26 DQ30
DQ27 DQ31
VCCQ VCCQ
VSS SDCE VSS
SSRAM Clock
VCC SDWE SDA10 NC
SSRAM Address Status Control
SSRAM Write Enable
VCC
VCC
VCC
VSS
VSS SDCLK VSS
VSS VSS VSS
VSS
VSS
SSOE
SSRAM Output Enable
SDRAM Clock
SDCLK
SDRAS
SDCAS
SDWE
SDA10
BWE0-3
SDRAM Row Address Strobe
SDRAM Column Address Strobe
SDRAM Write Enable
NC
NC
A6
NC
NC
A7
NC SDRAS SDCAS VSS
A4
A3
A5
A8
VSS
VSS
NC
NC
NC
A1
A10
A9
VSS VSS
A0
A11 A12
SDRAM Address 10/auto precharge
NC/A17 NC/A18 NC/A19 VSS
VSS
NC
NC
VCC
VCC
VCC
VCC
VCC
VCC
A13
A15
A14
A16
SSRAM Byte Write Enables
SDRAM SDQM 0 - 3
NC
NC
NC BWE2 BWE3 NC
VCC BWE0 BWE1 NC
VCCQ VCCQ
DQ12 DQ11
DQ13 DQ10
VCCQ VCCQ
DQ14 DQ9
DQ15 DQ8
VCCQ VCCQ
DQ4 DQ0
DQ5 DQ1
VCCQ VCCQ
DQ6 DQ2
DQ7 DQ3
SSCE
SDCE
VCC
Chip Enable SSRAM Device
Chip Enable SDRAM Device
Power Supply pins, 3.3V
VCC
VCC
VCC
VSS
VSS SSCLK VSS
VSS VSS VSS
VSS
VSS
VCCQ
Data Bus Power Supply pins,
3.3V (2.5V future)
VCC SSADC SSWE NC
VCC SSOE SSCE NC
VSS
NC
Ground
No Connect
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
January 2002 Rev. 4
ECO# 14667
FIG. 2 BLOCK DIAGRAM
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
SSCLK
Input
Input
Pulse
Pulse
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
SSADS
SSOE
SSWE
When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation
Active Low to be executed by the SSRAM.
SSCE
SDCLK
SDCE
Input
Input
Input
Pulse
Pulse
Pulse
Active Low SSCE disable or enable SSRAM device operation.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3.
SDRAS
SDCAS
SDWE
When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the
Active Low operation to be executed by the SDRAM.
Input
Input
Pulse
Level
Address bus for SSRAM and SDRAM
A0 and A1 are the burst address inputs for the SSRAM
During a Bank Active command cycle, A0-9, SDA10 defines the row address (RA0-10) when sampled
at the rising clock edge.
A0-16
,
—
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at
the rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge
operation at the end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and
SDA10
A
11 defines the bank to be precharged (low = bank A, high = bank B). If SDA10 is low,
autoprecharge is disabled.
During a Precharge command cycle, SDA10 is used in conjunction with A11 to control which bank(s)
to precharge. If SDA10 is high, both bank A and Bank B will be precharged regardless of the state of
A11. If SDA10 is low, then A11 is used to define which bank to precharge.
DQ0-31
BWE0-3
Input
Output
Level
Pulse
—
Data Input/Output are multiplexed on the same pins.
Input
BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM.
BWE0 is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31
.
VCC, VSS
VCCQ
Supply
Supply
Power and ground for the input buffers and the core logic.
Data base power supply pins, 3.3V (2.5V future).
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
Voltage on Vcc Relative to Vss
Vin (DQx)
-0.5V to +4.6V
-0.5V to Vcc +0.5V
-55°C to +125°C
+175°C
Storage Temperature (BGA)
Junction Temperature
Short Circuit Output Current
Supply Voltage1
Input High Voltage1,2
Input Low Voltage1,2
VCC
VIH
VIL
ILI
3.135
2.0
3.6
VCC +0.3
0.8
V
V
100 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in operational sections of this specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
-0.3
-10
V
Input Leakage Current
0 - VIN - Vcc
10
µA
Output Leakage (Output Disabled)
0 - VIN - Vcc
ILO
-10
10
µA
Output High (IOH = -4mA)1
Output Low (IOL = 8mA)1
VOH
VOL
2.4
—
—
V
V
0.4
1. All voltages referenced to Vss (GND).
2. Overshoot: VIH
Underershoot: VIL
+6.0V for t - tKC/2
-2.0V for t - tKC/2
Power Supply Current:
133MHz
400
450
500
TBD
300
350
400
TBD
220
235
255
20.0
550
Operating (1,2,3)
SSRAM Active / DRAM Auto Refresh
SSRAM Active / DRAM Idle
ICC
150MHz
166MHz
200MHz
133MHz
150MHz
166MHz
200MHz
83MHz
580
625
TBD
450
480
525
TBD
240
250
280
40.0
mA
1
2
3
Power Supply Current
Operating1,2,3
ICC
mA
Power Supply Current
Operating1,2,3
SDRAM Active / SSRAM Idle
SSCE and SDCE VCC -0.2V,
ICC
ISB
100MHz
125MHz
mA
mA
1
2
CMOS Standby
All other inputs at VSS +0.2
VCC -0.2V, Clk frequency = 0
SSCE and SDCE VIH min
All other inputs at VIL max
VCC -0.2V, Clk frequency = 0
VIN or
VIN
ISB
30.0
190
55.0
250
TTL Standby
Auto Refresh
VIN or
mA
mA
VIN
ICC
5
1. ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading.
2. “Device idle” means device is deselected (CE VIH) Clock is running at max frequency and Addresses are switching each cycle.
3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency.
Address Input Capacitance1
Input/Output Capacitance (DQ)1
Control Input Capacitance1
Clock Input Capacitance1
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
CI
5
8
5
4
8
pF
CO
CA
CCK
10
8
pF
pF
pF
6
1. This parameter is sampled.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Clock to output valid
tKHKH
tKLKH
tKHKL
tKHQV
tKHQX
tKQLZ
tKQHZ
tOELQV
tOELZ
tOEHZ
tS
5
1.6
1.6
6
2.4
2.4
7
2.6
2.6
8
2.8
2.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2.5
3.5
3.8
4.0
Clock to output invalid
1.5
0
1.5
1.5
0
1.5
1.5
0
1.5
1.5
0
1.5
Clock to output on Low-Z
Clock to output in High-Z
Output Enable to output valid
Output Enable to output in Low-Z
Output Enable to output in High-Z
Address, Control, Data-in Setup Time to Clock
Address, Control, Data-in Hold Time to Clock
3
2.5
3.5
3.5
3.8
3.8
4.0
4.0
0
0
0
0
3.0
3.5
3.5
3.8
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
tH
Deselected Cycle, Power Down
WRITE Cycle, Begin Burst
None
H
L
L
L
X
L
X
X
L
High-Z
External
External
External
Current
Current
Current
Current
Current
Current
D
Q
READ Cycle, Begin Burst
L
L
H
H
H
H
H
H
L
READ Cycle, Begin Burst
L
L
H
L
High-Z
Q
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
H
H
H
H
H
H
H
L
High-Z
Q
H
X
X
High-Z
D
L
D
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying
HIGH though out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
READ
H
L
X
L
X
H
L
X
H
L
X
H
L
WRITE one Byte (DQ0-7
)
WRITE all Bytes
L
L
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
SSRAM READ TIMING
SSRAM WRITE TIMING
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
Clock Cycle Time1
CL = 3
CL = 2
tCC
tCC
8
10
1000
1000
6
10
12
1000
1000
7
12
15
1000
1000
8
ns
Clock to valid Output delay1,2
Output Data Hold Time2
Clock HIGH Pulse Width3
Clock LOW Pulse Width3
Input Setup Time3
Input Hold Time3
CLK to Output Low-Z2
CLK to Output High-Z
Row Active to Row Active Delay4
RAS to CAS Delay4
Row Precharge Time4
Row Active Time4
Row Cycle Time - Operation4
Row Cycle Time - Auto Refresh4,8
Last Data in to New Column Address Delay5
Last Data in to Row Precharge5
Last Data in to Burst Stop5
Column Address to Column Address Delay6
Number of Valid Output Data7
tSAC
tOH
tCH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
2
1
2
3
3
3
2
1
2
3
3
3
2
1
2
tCL
tSS
tSH
tSLZ
tSHZ
tRRD
tRCD
tRP
7
7
8
20
20
20
50
70
70
1
1
1
1.5
2
1
20
20
20
50
80
80
1
1
1
1.5
2
2
24
24
24
60
90
90
1
1
1
1.5
2
1
tRAS
tRC
10,000
10,000
10,000
tRFC
tCDL
tRDL
tBDL
tCCD
ns
CLK
CLK
CLK
CLK
ea
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (tRISE/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If tRISE of tFALL are longer than 1ns. [(tRISE = tFALL)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the
next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHZ SDRAM
125MHz (8.0ns)
100MHz (10.0ns)
83MHz (12.0ns)
3
3
2
9
7
6
6
5
4
3
2
2
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHZ SDRAM
100MHz (12.0ns)
83MHz (12.0ns)
3
2
7
6
5
5
2
2
2
2
2
2
1
1
1
1
1
1
Refresh Period1,2
1. 4096 cycles
tREF
—
64
—
64
ms
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up” the device.
Mode Register Set
Auto Refresh (CBR)
L
L
L
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
L
OP CODE
X
BA
X
X
L
Precharge
Single Bank
Precharge all Banks
L
L
H
H
H
L
2
L
L
L
H
Bank Activate
Write
L
L
H
L
BA
BA
BA
BA
BA
X
Row Address
2
2
2
2
2
3
L
H
H
H
H
H
H
X
X
X
L
H
L
Write with Auto Precharge
Read
L
L
L
L
L
L
Read with Auto Precharge
Burst Termination
No Operation
L
L
H
L
H
X
X
X
X
X
L
H
H
X
X
X
L
H
X
X
X
X
Device Deselect
H
X
X
X
Data Write/Output Disable
Data Mask/Output Disable
NOTES:
X
4
4
H
X
1. All of the SDRAM operations are defined by states of SDCE, SDWE, SDRAS, SDCAS, and BWE0-3 at the positive rising edge of the clock.
2. Bank Select (BA), if A11 = 0 then bank A is selected, if BA = 1 then bank B is selected.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are
disabled and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write
operation at the clock is prohibited (zero clock latency).
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
Set the Mode Register
1
1
X
X
X
Start Auto
No Operation
L
H
H
L
X
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Activate the specified bank and row
ILLEGAL
Idle
H
H
H
H
X
L
Column
2
1
1
L
H
L
Column
ILLEGAL
H
H
X
L
X
X
X
No Operation
H
X
L
X
No Operation
X
No Operation
OP Code
ILLEGAL
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Precharge
3
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
1
Row Active
H
H
H
H
X
L
Column
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation
4,5
4,5
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
No Operation
X
No Operation
OP Code
ILLEGAL
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Terminate Burst; Start the Precharge
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
2
Read
H
H
H
H
X
L
Column
Terminate Burst; Start the Write cycle
Terminate Burst; Start a new Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
5,6
5,6
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Terminate Burst; Start the Precharge
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
2
Write
H
H
H
H
X
L
Column
Terminate Burst; Start a new Write cycle
Terminate Burst; Start the Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
5,6
5,6
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
X
OP Code
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
2
2
Read with
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Auto Precharge
H
H
H
H
X
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
ILLEGAL
H
X
X
Continue the Burst
Continue the Burst
X
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
X
X
X
X
ILLEGAL
L
H
H
L
ILLEGAL
2
2
Write with
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Auto Precharge
H
H
H
H
X
L
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
H
X
L
X
Continue the Burst
X
Continue the Burst
OP Code
ILLEGAL
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
No Operation; Bank(s) idle after tRP
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
2
2
2
Precharging
H
H
H
H
X
L
Column
ILLEGAL
L
H
L
Column
ILLEGAL
H
H
X
L
X
X
X
No Operation; Bank(s) idle after tRP
H
X
L
X
No Operation; Bank(s) idle after tRP
X
No Operation; Bank(s) idle after tRP
OP Code
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
L
L
H
L
X
X
X
L
H
H
L
X
2
2
2
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
Row Activating
H
H
H
H
X
L
Column
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination No Operation; Row active after tRCD
H
X
L
X
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
No Operation; Row active after tRCD
X
No Operation; Row active after tRCD
OP Code
ILLEGAL
L
L
H
L
X
X
X
ILLEGAL
ILLEGAL
L
H
H
L
X
2
2
6
6
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Write Recovering
H
H
H
H
X
L
Column
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination No Operation; Row active after tDPL
H
X
L
X
No Operation
Device Deselect
Mode Register Set
Auto orSelf Refresh
Precharge
No Operation; Row active after tDPL
X
No Operation; Row active after tDPL
OP Code
ILLEGAL
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
ILLEGAL
ILLEGAL
2
Write Recovering
with Auto
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
2
H
H
H
H
X
Column
ILLEGAL
2,6
2,6
Precharge
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
H
X
X
X
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
L
L
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
X
X
X
X
ILLEGAL
L
L
H
H
L
ILLEGAL
L
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Refreshing
L
H
H
H
H
X
L
Column
ILLEGAL
L
L
H
L
Column
Read
ILLEGAL
L
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
No Operation; Idle after tRC
L
H
X
L
X
No Operation; Idle after tRC
H
L
X
No Operation; Idle after tRC
OP Code
ILLEGAL
L
L
L
H
L
X
X
X
ILLEGAL
L
L
H
H
L
X
ILLEGAL
Mode Register
Accessing
L
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
L
H
H
H
H
X
Column
ILLEGAL
L
L
H
L
Column
Read
ILLEGAL
ILLEGAL
L
H
H
X
X
X
X
Burst Termination
No Operation
L
H
X
X
No Operation; Idle after two clock cycles
H
X
Device Deselect No Operation; Idle after two clock cycles
NOTES:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the
Current State then the action may be legal depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfied.
4. The RAS to CAS Delay (tRCD) must occur before the command is given.
5. Address SDA10 is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank
delay time (tRRD) is not satisfied.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE)
@ CAS LATENCY = 3, BURST LENGTH = 1
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
SDRAM POWER UP SEQUENCE
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
SDRAM READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2 Row precharge can interrupt burst on any cycle. (CAS Latency - 1) number of valid output data is available after Row precharge. Last valid output will
be Hi-Z (tSHZ) after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS Latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
1. To write data before burst read ends. BWE should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge
cycle will be masked internally.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
NOTES:
1. SDCE can be “don’t care” when SDRAS, SDCAS and SDWE are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
Notes:
1. To interrupt burst write by Row precharge, BWE should be asserted to mask invalid input data.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
NOTES:
1. tCDL should be met to complete write.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @ BURST LENGTH
= 4
NOTES:
1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ BURST
STOP @ BURST LENGTH = FULL PAGE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is the same as the case of SDRAS interrupt. Both cases are illustrated in the above timing diagram. See the label
1, 2 on each of them. But at burst write, burst stop and SDRAS interrupt should be compared carefully. Refer to the timing diagram of “Full page write
burst stop cycle”.
3. Burst stop is valid at every burst length.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND & WRITE BURST
STOP @ BURST LENGTH = FULL PAGE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL.
BWE at write interrupt by precharge command is needed to prevent invalid write.
BWE should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge
cycle will be masked internally.
3. Burst stop is valid at every burst length.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
SDRAM BURST READ SINGLE BIT WRITE CYCLE @ BURST LENGTH = 2
NOTES:
1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the
burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
HIGH
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle.
NOTES:
1. SDCE, SDRAS, SDCAS & SDWE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new SDRAS activation.
7. Please refer to Mode Register Set table.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
153 LEAD BGA (17 X 9 BALL ARRAY)
JEDEC MO-163
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Note:
Ball attach pad for above BGA is 480 microns, in diameter. Pad is solder mask defined.
EDI9LC644V2012BC
EDI9LC644V2010BC
EDI9LC644V1612BC
EDI9LC644V1610BC
EDI9LC644V1512BC
EDI9LC644V1510BC
EDI9LC644V1312BC
EDI9LC644V1310BC
200MHz
200MHz
166MHz
166MHz
150MHz
150MHz
133MHz
133MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
Address Bus
EA2-21
EDI9LC644V
128K x 32 SSRAM
1M x 32 SDRAM
EA
EA
2
3
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ0-7
DQ8-15
Texas Instruments
TMS320C6x
DSP
DQ16-23
DQ24-31
SSWE\
SSCE\
SSOE\
SSADC\
SSCLK
SSWE\
CE
SSOE\
SSADS\
SSCLK
2\
SSRAM
Control
BWE
BWE
BWE
BWE
0\
1\
2\
3\
BE0
BE1
BE2
BE3
\
\
\
\
Shared
Controls
SDA10
SDA10
CE
SDRAS\
SDCAS\
SDWE\
SDCLK
SDCE\
SDRAS\
0\
SDRAM
SDCAS\ Control
SDWE\
SDCLK
Data Bus
ED0-31
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
相关型号：
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