W3EG128M72ETSU-JD3 [WEDC]
1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL; 1GB - 128Mx72 DDR SDRAM非缓冲ECC W / PLL
| 型号： | W3EG128M72ETSU-JD3 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 1GB - 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL |
| 文件： | 总14页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED*
1GB – 128Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
FEATURES
DESCRIPTION
ꢀ
ꢀ
Double-data-rate architecture
The W3EG128M72ETSU is a 128Mx72 Double Data Rate
SDRAM memory module based on 1Gb DDR SDRAM
components. The module consists of nine 128Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
DDR200, DDR266, DDR333 and DDR400
• JEDEC design specification
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges and Burst Lengths allow the same device to
be useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
Serial presence detect
Power supply:
• VCC = VCCQ = +2.5V 0.2V (100, 133 and
166MHz)
• VCC = VCCQ = +2.6V 0.1V (200MHz)
JEDEC standard 184 pin DIMM package
ꢀ
• Package height options:
JD3: 30.48 mm (1.20”)
AJD3: 28.70 mm (1.13”)
NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option
OPERATING FREQUENCIES
DDR400@CL=3
DDR333@CL=2.5
166MHz
DDR266@CL=2
133MHz
DDR266@CL=2.5
133MHz
DDR200@CL=2
100MHz
Clock Speed
CL-tRCD-tRP
200MHz
3-3-3
2.5-3-3
2-2-2
2.5-3-3
2-2-2
January 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
A0-A12
Address input (Multiplexed)
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
PIN#
SYMBOL
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS17
CK0
Bank Select Address
Data Input/Output
Check bits
Data Strobe Input/Output
Clock Input
1
2
3
VREF
DQ0
VSS
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQS8
A0
CB2
VSS
CB3
93
94
95
96
97
98
99
VSS
DQ4
DQ5
VCCQ
DQS9
DQ6
DQ7
VSS
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VSS
DQS17
A10
CB6
VCCQ
CB7
4
5
6
7
DQ1
DQS0
DQ2
VCC
CK0#
Clock input
BA1
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
VCC
VCCQ
VSS
VREF
VCCSPD
SDA
SCL
SA0-SA2
VCCID
NC
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Power Supply
Power Supply for DQS
Ground
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
VSS
8
9
DQ3
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
DQ36
DQ37
VCC
DQS13
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
CS1#
DQS14
VSS
DQ46
DQ47
NC
VCCQ
DQ52
DQ53
NC
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
RESET#
VSS
DQ8
DQ9
DQS1
VCCQ
NC
VCCQ
DQ12
DQ13
DQS10
VCC
DQ14
DQ15
CKE1
VCCQ
NC
DQ20
A12
VSS
DQ21
A11
DQS11
VCC
BA0
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
VCC
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
NC
VSS
Serial clock
Address in EEPROM
VCC Indentification Flag
No Connect
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
RESET#
Reset Enable
NC
DQ48
DQ49
VSS
NC
NC
DQ22
A8
DQ23
VSS
VCC
VCCQ
DQS6
DQ50
DQ51
VSS
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
DQS15
DQ54
DQ55
VCCQ
NC
DQ60
DQ61
VSS
DQS16
DQ62
DQ63
VCCQ
SA0
SA1
A6
DQ28
DQ29
VCCQ
DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
DQ25
DQS3
A4
VCC
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VCC
NC
SDA
SCL
VCCQ
CK0
CK0#
SA2
VCCSPD
January 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
S0#
DQS0
DM0
DQS4
DM4
DM CS# DQS
DM CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS1
DM1
DQS5
DM5
DM CS# DQS
DM CS# DQS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS6
DM6
DM CS# DQS
DM CS# DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
120
CK0
DDR SDRAM
CK0#
DQS3
DM3
DQS7
DM7
120
CK1
DM CS# DQ
DM CS# DQ
DDR SDRAM
CK1#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
120
CK2
DDR SDRAM
CK2#
DQS8
DM8
SERIAL PD
SCL
WP
SDA
DM CS# DQS
A0 A1 A2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
VCC
SA0 SA1 SA2
120
CK0A
FREQ_SEL
CK0
DDR
SDRAM
PLL
CK0A#
CK0#
BA0, BA1
A0-A12
RAS#
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE0: DDR SDRAMs
WE#: DDR SDRAMs
V
CCSPD
CC
REF
SS
SPD/EEPROM
V
DDR SDRAMS
DDR SDRAMS
DDR SDRAMS
CAS#
CKE0
WE#
V
V
NOTE: All resistor values are 22 ohms unless otherwise specified
January 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
– 0.5 ~ 3.6
–1.0 ~ 3.6
– 55 ~ +150
9
Units
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
V
°C
W
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V 0.2V (100, 133 and 166MHz), VCCQ = 2.6V 0.1V (200MHz)
Parameter
Symbol
VCC
Min
2.3
Max
2.7
Unit
V
Supply Voltage
Supply Voltage
VCCQ
VREF
VTT
2.3
2.7
V
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
1.15
1.35
V
1.15
1.35
V
VIH
VREF + 0.15
– 0.3
VCCQ + 0.3
VREF – 0.15
—
V
VIL
V
VOH
VTT + 0.76
—
V
VOL
VTT – 0.76
V
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 2.5V 0.2V (100, 133 and 166MHz), VCCQ = 2.6V 0.1V (200MHz)
Parameter
Symbol
CIN1
Max
29
29
29
5.5
29
8
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0,CKE1)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#,CS1#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
29
8
Data input/output Capacitance (DQ0-DQ63)(DQS)
Data input/output Capacitance (CB0-CB7)
COUT
COUT
8
January 2005
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V 0.2V (100, 133, 166MHz), VCC = VCCQ = +2.6V 0.1V (200MHz)
DDR400@
CL=3
DDR333@
CL=2.5
DDR266@
CL=2, 2.5
DDR200@
CL=2
Parameter
Symbol Conditions
IDD0
Max
Max
Max
Max
Units
Operating Current
One device bank; Active - Precharge;
TBD
TBD
TBD
TBD
mA
(MIN); DQ,DM and DQS inputs
changing once per clock cycle;
Address and control inputs changing
once every two cycles. TRC=TRC(MIN);
TCK=TCK
Operating Current
IDD1
One device bank; Active-
TBD
TBD
TBD
TBD
mA
Read-Precharge; Burst = 2;
TRC=TRC(MIN);TCK=TCK (MIN); Iout
= 0mA; Address and control inputs
changing once per clock cycle.
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power-down
mode; TCK=TCK(MIN); CKE=(low)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
TCK=TCK(MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
Active Power-Down
Standby Current
IDD3P
IDD3N
One device bank active; Power-down
mode; TCK(MIN); CKE=(low)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
Active Standby
Current
CS# = High; CKE = High; One
device bank; Active-Precharge;
TRC=TRAS(MAX); TCK=TCK(MIN); DQ,
DM and DQS inputs changing twice
per clock cycle; Address and other
control inputs changing once per clock
cycle.
Operating Current
Operating Current
IDD4R
Burst = 2; Reads; Continous burst;
One device bank active;Address
andcontrol inputs changing once
per clock cycle; TCK=TCK(MIN); IOUT
= 0mA.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
IDD4W
Burst = 2; Writes; Continous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; TCK=TCK(MIN); DQ,DM and
DQS inputs changing twice per clock
cycle.
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5
IDD6
TRC=TRC(MIN)
CKE ≤ 0.2V
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
mA
mA
mA
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with TRC=TRC
(MIN); TCK=TCK(MIN); Address and
control inputs change only during
Active Read or Write commands
January 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
4. Timing Patterns :
•
•
•
•
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR400 (200MHz, CL=3) : tCK=5ns, BL=4,
tRCD=15*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR400 (200MHz, CL=3) : tCK=5ns,
BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend : A = Activate, R = Read, W = Write, P = Precharge,
N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
January 2005
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: VCC = VCCQ = +2.6V 0.1V
AC CHARACTERISTICS
403
335
262
265
202
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
tAC
tCH
tCL
-0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 0.75 -0.8
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55
0.8
ns
tCK
tCK
25
25
Clock cycle time
CL = 3
CL = 2.5
CL = 2
tCK (3)
tCK (2.5)
tCK (2)
tDH
5
6
7.5
0.4
0.4
1.75
7.5
13
13
6
7.5
13
13
7.5
7.5
13
7.5
13
8
10
13
13
ns 38, 43
ns 38, 43
ns 37, 42
ns 22, 26
ns 22, 26
13 7.5/10 13
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
0.45
0.45
1.75
0.5
0.5
1.75
0.6
0.6
2
tDS
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
ns
ns
tCK
tCK
ns
26
-0.6 +0.6 -0.60 +0.60 -0.75 +0.75 +0.75 -0.8 +0.8
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.35
0.5
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per
0.40
0.45
0.5
0.6
22
access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
tDQSS
tDSS
tDSH
tHP
0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25
tCK
tCK
tCK
ns
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
tCH,tCL
29
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (1 V/ns)
Address and control input setup time (1 V/ns)
Address and control input hold time (0.5 V/ns)
Address and control input setup time (0.5 V/ns)
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
tHZ
tLZ
tIHF
tISF
tIHS
tISS
tIPW
tMRD
tQH
+0.70
+0.70
+0.75
+0.75
+0.8
ns 16, 36
ns 16, 36
-0.70
0.6
0.6
0.6
0.6
2.20
2
-0.70
0.75
0.75
0.80
0.80
2.2
-0.75
0.90
0.90
1
1
2.2
15
-0.75
-0.8
ns
0.90 1.1
12
ns
ns
ns
ns
ns
ns
ns
12
12
12
12
0.90
1
1
2.2
15
1.1
1.1
1.1
2.2
16
12
DQ-DQS hold, DQS to first DQ to go non-valid, per
tHP
tHP
tHP
tHP
tHP
22
30
access
- tQHS
- tQHS
- tQHS
- tQHS
- tQHS
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
tQHS
tRAS
tRAP
tRC
0.50
0.60
0.75
0.75
1
ns
40 70,000 42 70,000 40 120,000 40 120,000 40 120,000 ns
15
55
15
60
15
60
20
65
20
70
ns
ns
ACTIVE to ACTIVE/AUTO REFRESH command
period
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tRFC
tRCD
tRP
tRPRE
tRPST
tRRD
tWPRE
tWPRES
70
15
15
0.9
0.4
10
0.25
0
72
15
15
0.9
0.4
12
0.25
0
75
15
15
0.9
0.4
15
0.25
0
72
20
20
0.9
0.4
15
0.25
0
75
20
20
0.9
0.4
15
0.25
0
ns
ns
ns
tCK
tCK
ns
tCK
41
1.1
0.6
1.1
0.6
1.1
0.6
1.1
0.6
1.1
0.6
36
36
DQS write preamble setup time
ns 17, 19
January 2005
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS (Continued)
DDR400: VCC = VCCQ = +2.6V 0.1V
AC CHARACTERISTICS
403
355
262
265
202
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
DQS write postamble
Write recovery time
tWPST
tWR
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
tCK
ns
17
Internal WRITE to READ command delay
tWTR
2
1
1
1
1
tCK
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VCC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
na
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
ns
µs
µs
ns
ns
tCK
22
21
21
tQH - tDQSQ
tQH - tDQSQ
tREFC
tREFI
tVTD
tXSNR
tXSRD
70.3
7.8
70.3
7.8
70.3
7.8
70.3
7.8
70.3
7.8
0
75
200
0
75
200
0
75
200
0
75
200
0
80
200
January 2005
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
Notes
1. All voltages referenced to VSS
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specifications
and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load:
.
17. The intent of the Don’t Care state after completion of the postamble is the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high [above VIHDC (MIN)] then it must not transition low (below
VIHDC) prior to tDQSH (MIN).
18. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
V
TT
19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
50Ω
RReeffeerreennccee
Output
Point
30pF
progress, DQS could be HIGH during this time, depending on tDQSS
.
(VOUT
)
20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter. tRAS (MAX) for IDD
measurements is the largest multiple of tCK that meets the maximum absolute value
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The mini-mum slew rate for the input signals
used to test the device is 1V/ns in the range between VIL (AC) and VIH (AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
for tRAS
.
21. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs.
However, an AUTO REFRESH command must be as-serted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
22. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ
and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with
the clock duty cycle and a practical data valid window can be derived. The clock
is allowed a maximum duty cycle variation of 45/55, beyond which functionality
is uncertain. Figure 7, Derating Data Valid Window, shows derating curves are
provided below for duty cycles ranging between 50/50 and 45/55.
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
25. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
,
6.
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations
in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may
not exceed 2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed 25mV
for DC error and an additional 25mV for AC noise. This measurement is to be
taken at the nearest VREF bypass capacitor.
7.
8.
V
TT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track variations
in the DC level of VREF
DD is dependent on output loading and cycle rates. Specified values are obtained
with mini-mum cycle time at CL = 2 for 262 and 202, CL = 2.5 for 265, 335 and
CL = 3 for 403 with the outputs open.
.
I
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
9. Enables on-chip refresh and address counters.
10. DD specifications are tested after the device is properly initialized, and is averaged
at the defined cycle rate.
11. This parameter is sampled. VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V, VREF = VSS
f = 100 MHz, TA = 25°C, VOUT (DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input
is grouped with I/O pins, reflecting the fact that they are matched in loading.
12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing
must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew
rate from 500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns,
functionality is uncertain. For 403, slew rates must be 0.5 V/ns.
I
26. JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns
differentially).
,
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.
If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps
must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate
exceeds 4 V/ns, functionality is uncertain. For 403, slew rates must be ≥ 0.5 V/ns.
28.
VCC must not vary more than 4 percent if CKE is not active while any bank is active.
29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary
by the same amount.
13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK and CK# cross; the input reference level for signals other than CK/CK# is
30.
t
HP min is the lesser of tCL minimum and tCH minimum actually applied to the device
CK and CK/ inputs, collectively during bank active.
31. READs and WRITEs with auto precharge are not allowed to be issued until
RAS(MIN) can be satisfied prior to the internal precharge command being issued.
VREF
.
14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period
before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW.
15. The output timing reference level, as measured at the timing reference point
t
32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and
not more than +400mV or 2.9V maximum, whichever is less. Any negative glitch
must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V
mini-mum, whichever is more positive.
indicated in Note 3, is VTT
.
16. tHZ and tLZ transitions occur in the same access time windows as data valid
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
January 2005
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
33. The voltage levels used are derived from a mini-mum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus will
provide significantly different voltage values.
40. Random addressing changing and 50 percent of data changing at every transfer.
41. Random addressing changing and 100 percent of data changing at every transfer.
42. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tREF later.
34.
VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width < 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.
43.
I
I
DD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.
DD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to
35.
36.
V
CC and VCCQ must track each other.
HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
RPST end point and tRPRE begin point are not referenced to a specific voltage level
t
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
44. Whenever the operating frequency is altered, not including jitter, the DLL is required
to be reset. This is followed by 200 clock cycles (before READ commands).
45. Leakage number reflects the worst case leakage possible through the module pin,
not what each memory device contributes.
37.
t
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
38. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ
are 0V, provided a minimum of 42 0 of series resistance is used between the VTT
supply and the input pin.
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.
47. The 403 speed grade will operate with tRAS (MIN) = 40 ns and tRAS (MAX) =
120,000ns at any slower frequency.
39. The current part operates below the slowest JEDEC operating frequency of 83
MHz. As such, future die may not reflect this option.
January 2005
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR JD3
Part Number
Speed
Height*
Commercial Operating Range
0°C to 70°C
W3EG128M72ETSU403JD3
W3EG128M72ETSU335JD3
W3EG128M72ETSU262JD3
W3EG128M72ETSU265JD3
W3EG128M72ETSU202JD3
200MHz/400Mbps, CL=3
166MHz/333Mbps, CL=2.5
133MHz/266Mbps, CL=2
133MHz/266Mbps, CL=2.5
100MHz/200Mbps, CL=2
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE:
1
2
3
* Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant)
* Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.
* Consult factory for availability for industrial temperature (-40°C to 85°C) options
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
2.54
(0.100 MAX)
3.99
(0.157 (2x))
30.48
(1.20 MAX)
17.78
(0.700)
1.27
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
10.0
(0.050 TYP.)
(0.394)
3.99
6.35
(0.250)
49.53
1.27
(0.157)
(MIN)
(1.950)
0.10
(0.050)
( 0.004)
64.77
(2.550)
6.36
1.78
(0.070)
(0.250)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
January 2005
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR AJD3
Part Number
Speed
Height*
Commercial Operating Range
0°C to 70°C
W3EG128M72ETSU403AJD3
W3EG128M72ETSU335AJD3
W3EG128M72ETSU262AJD3
W3EG128M72ETSU265AJD3
W3EG128M72ETSU202AJD3
200MHz/400Mbps, CL=3
166MHz/333Mbps, CL=2.5
133MHz/266Mbps, CL=2
133MHz/266Mbps, CL=2.5
100MHz/200Mbps, CL=2
28.70 (1.13") MAX
28.70 (1.13") MAX
28.70 (1.13") MAX
28.70 (1.13") MAX
28.70 (1.13") MAX
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE:
1
2
3
* Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant)
* Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.
* Consult factory for availability for industrial temperature (-40°C to 85°C) options
PACKAGE DIMENSIONS FOR AJD3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
2.54
(0.100 MAX)
3.99
(0.157 (2x))
28.70
(1.13 MAX)
17.78
(0.700)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27
10.0
(0.050 TYP.)
(0.394)
3.99
6.35
(0.250)
49.53
1.27
(0.157)
(MIN)
(1.950)
0.10
(0.050)
( 0.004)
64.77
(2.550)
6.35
1.78
(0.070)
(0.250)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
January 2005
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D3
Part Number
Speed
Height*
Commercial Operating Range
0°C to 70°C
W3EG128M72ETSU403D3
W3EG128M72ETSU335D3
W3EG128M72ETSU262D3
W3EG128M72ETSU265D3
W3EG128M72ETSU202D3
200MHz/400Mbps, CL=3
166MHz/333Mbps, CL=2.5
133MHz/266Mbps, CL=2
133MHz/266Mbps, CL=2.5
100MHz/200Mbps, CL=2
28.58 (1.125") MAX
28.58 (1.125") MAX
28.58 (1.125") MAX
28.58 (1.125") MAX
28.58 (1.125") MAX
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE:
1
2
3
* Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant)
* Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.
* Consult factory for availability for industrial temperature (-40°C to 85°C) options
PACKAGE DIMENSIONS FOR D3
Note: D3 Not Recommended For New Designs
133.48
(5.255" MAX.)
131.34
(5.171")
2.54
(0.100 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
28.58
(1.125 MAX)
17.78
(0.700)
2.31
1.27
10.0
(0.091)
(0.050 TYP.)
(0.394)
3.99
(0.157)
(MIN)
6.35
(0.250)
49.53
1.27
0.10
(2x)
(1.950)
64.77
3.00
(0.118)
(4x)
(0.050)
0.004)
(2.550)
6.35
(
1.78
(0.070)
(0.250)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
January 2005
Rev. 0
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG128M72ETSU-D3
-JD3
-AJD3
White Electronic Designs
ADVANCED
Document Title
1GB – 128Mx72, DDR, SDRAM Unbuffered ECC, w/PLL
Revision History
Rev #
History
Release Date Status
Rev 0
Created
1-04-05
Advanced
January 2005
Rev. 0
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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