W3EG2256M72ASSR202JD3MG [WEDC]
DDR DRAM Module, 512MX72, 0.8ns, CMOS, ROHS COMPLIANT, DIMM-184;
| 型号： | W3EG2256M72ASSR202JD3MG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | DDR DRAM Module, 512MX72, 0.8ns, CMOS, ROHS COMPLIANT, DIMM-184 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总14页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
4GB – 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL
FEATURES
DESCRIPTION
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Double-data-rate architecture
The W3EG2256M72ASSR is a 2x256Mx72 Double
Data Rate SDRAM memory module based on 1Gb DDR
SDRAM components. The module consists of eighteen
512Mx4 stacks, in 66 pin TSOP packages mounted on
a 184 pin FR4 substrate.
DDR200, DDR266, and DDR333
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges and Burst Lengths allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Serial presence detect
Dual Rank
* This product is subject to change without notice.
Power supply: VCC = 2.5V ± 0.2V
JEDEC standard 184 pin DIMM package
• Package height options:
JD3: 30.48mm (1.2"),
AJD3: 28.70mm (1.13")
BJD3: 28.70mm (1.13")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR333 @CL=2.5
DDR266 @CL=2
133MHz
DDR266 @CL=2
133MHz
DDR266 @CL=2.5
133MHz
DDR200 @CL=2
100MHz
Clock Speed
CL-tRCD-tRP
166MHz
2.5-3-3
2-2-2
2-3-3
2.5-3-3
2-2-2
March, 2007
Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
PIN CONFIGURATION
PIN NAMES
A0-A13
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS17 Data Strobe Input/Output
CK0
1
VREF
DQ0
VSS
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQS8
A0
93
VSS
DQ4
DQ5
VCCQ
DQS9
DQ6
DQ7
VSS
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VSS
DQS17
A10
2
94
3
CB2
95
4
5
6
7
8
9
DQ1
DQS0
DQ2
VCC
DQ3
NC
VSS
CB3
BA1
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
96
97
98
99
CB6
VCCQ
CB7
Clock Input
Clock Input
CK0#
CKE0, CKE1 Clock Enable input
VSS
CS0#, CS1#
RAS#
CAS#
WE#
VCC
VCCQ
VSS
VREF
VCCSPD
SDA
SCL
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Power Supply
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
DQ36
DQ37
VCC
DQS13
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
CS1#
DQS14
VSS
DQ46
DQ47
NC
VCCQ
DQ52
DQ53
A13
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
RESET#
VSS
DQ8
DQ9
DQS1
VCCQ
NC
VCCQ
DQ12
DQ13
DQS10
VCC
DQ14
DQ15
CKE1
VCCQ
NC
DQ20
A12
VSS
DQ21
A11
DQS11
VCC
BA0
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
VCC
NC
VSS
Serial clock
SA0-SA2
VCCID
NC
Address in EEPROM
VCC Indentification Flag
No Connect
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
RESET#
Reset Enable
NC
DQ48
DQ49
VSS
NC
NC
DQ22
A8
DQ23
VSS
VCC
VCCQ
DQS6
DQ50
DQ51
VSS
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
DQS15
DQ54
DQ55
VCCQ
NC
DQ60
DQ61
VSS
DQS16
DQ62
DQ63
VCCQ
SA0
A6
DQ28
DQ29
VCCQ
DQS12
A3
DQ30
VSS
DQ31
CB4
DQ25
DQS3
A4
VCC
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VCC
CB5
VCCQ
CK0
NC
SDA
SCL
SA1
SA2
VCCSPD
CK0#
March, 2007
Rev. 4
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
VSS
RCS1#
RCS0#
DQS0
DQS9
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQ0
DQ1
DQ2
DQ3
I/O 3
I/O 3
DQ4
DQ5
DQ6
DQ7
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQS1
DQS2
DQS10
DQS11
DQS CS# DM
I/O 3
I/O 2
I/O 1
I/O 0
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQ8
DQ9
DQ10
DQ11
I/O 3
DQ12
DQ13
DQ14
DQ15
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQ16
DQ17
DQ18
DQ19
I/O 3
I/O 3
DQ20
DQ21
DQ22
DQ23
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQS3
DQS12
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQS CS# DM
DQ24
DQ25
DQ26
I/O 3
I/O 3
DQ28
DQ29
DQ30
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQ27
DQ31
DQS4
DQS5
DQS6
DQS13
DQS14
DQS15
DQS CS# DM
DQS
CS# DM
CS# DM
CS# DM
DQS CS# DM
DQS CS# DM
DQ32
DQ33
DQ34
I/O 3
I/O 3
DQ36
DQ37
DQ38
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQ35
DQ39
DQS
CS# DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
DQS CS# DM
I/O 3
I/O 2
I/O 1
I/O 0
DQS CS# DM
I/O 3
I/O 2
I/O 1
I/O 0
DQ40
DQ41
DQ42
DQ43
I/O 3
I/O 2
I/O 1
I/O 0
DQ44
DQ45
DQ46
DQ47
DQS
CS# DM
DQS
DQS CS# DM
DQS CS# DM
DQ48
DQ49
DQ50
I/O 3
I/O 3
DQ52
DQ53
DQ54
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQ51
DQ55
DQS7
DQS8
DQS16
DQS17
DQS
CS# DM
DQS
CS# DM
DQS CS# DM
DQS CS# DM
DQ56
DQ57
DQ58
I/O 3
I/O 3
DQ60
DQ61
DQ62
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
DQ59
DQ63
DQS
CS# DM
DQS CS# DM
DQS CS# DM
DQS CS# DM
CB0
CB1
CB2
I/O 3
I/O 3
CB4
CB5
CB6
I/O 3
I/O 3
I/O 2
I/O 2
I/O 2
I/O 2
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
I/O 1
I/O 0
CB3
CB7
SERIAL PD
SPD
VCCSPD
VCC/VCCQ
VREF
CK0
SDRAM
SDA
SCL
WP
PLL
A1
A2
A0
DDR SDRAM
SA1 SA2
SA0
CK0#
REGISTER
DDR SDRAM
DDR SDRAM
R
E
G
I
S
T
E
R
CS0#
RCS0#
VSS
CS1#
BA0,BA1
A0-A13
RAS#
RCS1#
RBA0,RBA1
RA0-RA13
RRAS#
BA0,BA1: DDR SDRAMs
A0-A13: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE: DDR SDRAMs
CKE: DDR SDRAMs
WE#: DDR SDRAMs
RCAS#
CAS#
NOTES:
RCKE0
CKE0
RCKE1
CKE1
1. DQ-to-I/O wiring is shown as
recommended but may be changed.
RWE#
WE#
RESET#
Note: All resistor values are 22 ohms
PCK
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
PCK#
unless otherwise specified.
March, 2007
Rev. 4
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Units
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
-0.5 - 3.6
-1.0 - 3.6
-55 - +150
27
V
°C
W
Power Dissipation
PD
Short Circuit Current
I0S
50
mA
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V
Parameter
Symbol
VCC
Min
2.3
Max
2.7
Unit
V
Supply Voltage
Supply Voltage
VCCQ
VREF
VTT
2.3
2.7
V
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
1.15
1.35
1.35
V
1.15
V
VIH
VREF + 0.15
-0.3
VCCQ + 0.3
V
VIL
VREF - 0.15
—
V
VOH
VTT + 0.76
—
V
VOL
VTT - 0.76
V
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 2.5V ± 0.2V
Parameter
Symbol
CIN1
Max
6.25
6.25
6.25
5.5
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A13)
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
CIN2
CIN3
CIN4
CIN5
6.25
13
CIN6
CIN7
6.25
13
Data input/output capacitance (DQ0-DQ63)(DQS)
COUT
COUT
Data input/output capacitance (CB0-CB7)
13
Note: These parameters serve to support SAMSUNG components based modules
March, 2007
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
DDR333@
CL=2.5
Max
DDR266@
CL=2, 2.5
Max
DDR200@
CL=2
Max
Rank 2
Units Standby
State
Rank 1
Conditions
Parameter
Symbol
One device bank; Active - Precharge; tRC = tRC
(MIN); tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address and control
inputs changing once every two cycles.
Operating Current
IDD0
2,340
2,340
2,140
mA
IDD2F
One device bank; Active-Read-Precharge Burst
= 2; tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA;
Address and control inputs changing once per
clock cycle.
Operating Current
IDD1
3,060
540
2,700
540
2,500
540
mA
rnA
IDD2F
Precharge Power-
Down Standby
Current
All device banks idle; Power-down mode; tCK = tCK
(MIN); CKE = (low)
IDD2P
IDD2P
CS# = High; All device banks idle;
Idle Standby
Current
tCK = tCK (MIN); CKE = High; Address and other
control inputs changing once per clock cycle. VIN
VREF for DQ, DQS and DM.
IDD2F
1,260
810
1,080
810
1,080
810
mA
mA
IDD2F
=
Active Power-Down
Standby Current
One device bank active; Power-Down mode; tCK
(MIN); CKE = (low)
IDD3P
IDD2P
CS# = High; CKE = High; One device bank;
Active-Precharge;tRC = tRAS (MAX); tCK = tCK (MIN);
Active Standby
Current
IDD3N DQ, DM and DQS inputs changing twice per clock
cycle; Address and other control inputs changing
once per clock cycle.
1,890
1,710
1,610
mA
IDD2F
Burst = 2; Reads; Continuous burst; One device
IDD4R bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); lOUT = 0mA.
Operating Current
Operating Current
3,780
3,780
3,420
3,420
3,300
3,300
mA
rnA
IDD3N
Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing
once per clock cycle; tCK = tCK (MIN); DQ,DM and
IDD4W
IDD3N
DQS inputs changing once per clock cycle.
Auto Refresh
Current
IDD5
IDD6
tRC = tRC (MIN)
5,040
540
4,680
540
4,500
540
mA
mA
IDD2F
IDD6
Self Refresh
Current
CKE ≤ 0.2V
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN);
Address and control inputs change only during
Active Read or Write commands.
Operating Current
IDD7A
7,200
6,660
6,500
mA
IDD3N
Note: These parameters serve to support SAMSUNG components based modules
March, 2007
Rev. 4
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT: ONE BANK
IDD7A: OPERATING CURRENT: FOUR BANKS
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lOUT = 0mA
4. Timing patterns
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Four banks are being interleaved with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
not changing.
lout = 0mA
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4,
tRCD = 2*tCK, tRAg = 5*tCK
Read: A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing; 50% of data
changing at every burst
4. Timing patterns
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4,
tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5,
BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL =
2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with
autoprecharge
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL
= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2, BL
= 4, tRRD = 2*tCK, tRCD = 3*tCK
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
March, 2007
Rev. 4
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
AC Characteristics
335
262
263/265
Min
202
Symbol
Units Notes
Parameter
Min
-0.7
0.45
0.45
6
Max
+0.7
0.55
0.55
12
Min
-0.7
0.45
0.45
7.5
Max
+0.7
0.55
0.55
12
Max
+0.75
0.55
0.55
12
Min
-0.8
0.45
0.45
8
Max
+0.8
0.55
0.55
12
Access window of DQs from CK, CK#
CK high-level width
tAC
-0.75
0.45
0.45
7.5
ns
tCH
tCL
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
16
16
CK low-level width
CL=2.5 tCK (2.5)
22
Clock cycle time
CL=2
tCK (2)
tDH
7.5
12
7.5
12
10
12
10
12
22
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
0.45
0.45
1.75
-0.6
0.35
0.35
0.45
0.45
1.75
-0.6
0.35
0.35
0.5
0.6
0.6
2
14,17
14,17
17
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
1.75
-0.75
0.35
0.35
+0.60
+0.60
+0.75
-0.8
0.35
0.35
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
tDQSQ
0.45
1.25
0.5
0.5
0.5
ns
13,14
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
tDQSS
tDSS
tDSH
tHP
0.75
0.2
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
tCK
tCK
tCK
ns
ns
ns
0.2
0.2
0.2
0.2
tCH(MIN), tCL(MIN)
tCH(MIN), tCL(MIN)
tCH(MIN), tCL(MIN)
tCH(MIN), tCL(MIN)
18
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
tHZ
-0.70
-0.70
+0.70
+0.70
-0.70
-0.70
+0.70
+0.70
-0.75
-0.75
+0.75
+0.75
-0.80
-0.80
+0.80
+0.80
8,19
8,20
tLZ
Address and control input hold time (fast slew
rate)
tIHf
tISf
tIHs
tISs
0.75
0.75
0.80
0.80
0.75
0.75
0.80
0.80
0.90
0.90
1
1.1
1.1
1.1
1.1
ns
ns
ns
ns
6
6
6
6
Address and control input set-up time (fast slew
rate)
Address and control input hold time (slow slew
rate)
Address and control input setup time (slow slew
rate)
1
Address and control input pulse width (for each
input)
tIPW
tMRD
tQH
2.2
12
2.2
15
2.2
15
2.2
16
ns
ns
ns
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
tHP-tQHS
tHP-tQHS
tHP-tQHS
tHP-tQHS
13,14
15
Data hold skew factor
tQHS
tRAS
0.55
0.75
0.75
1
ns
ns
ACTIVE to PRECHARGE command
45
18
70,000
45
15
70,000
45
20
70,000
45
20
70,000
ACTIVE to READ with Auto precharge
command
tRAP
ns
Note: These parameters serve to support SAMSUNG components based modules
March, 2007
Rev. 4
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W3EG2256M72ASSR-JD3
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DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
AC Characteristics
Parameter
335
262
263/265
202
Units Notes
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
ACTIVE to ACTIVE/AUTO REFRESH
command period
tRC
60
60
65
70
ns
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
tRFC
tRCD
120
18
120
20
120
20
120
20
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
μs
μs
ns
ns
tCK
21
19
tRP
18
20
20
20
tRPRE
tRPST
tRRD
0.9
0.4
12
1.1
0.6
0.9
0.4
15
1.1
0.6
0.9
0.4
15
1.1
0.6
0.9
0.4
15
1.1
0.6
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
0.25
0
0.25
0
0.25
0
DQS write preamble setup time
DQS write postamble
10,11
9
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
0.4
15
0.6
Write recovery time
Internal WRITE to READ command delay
Data valid output window
tWTR
NA
1
1
1
1
tQH-tDQSQ
70.3
7.8
tQH-tDQSQ
70.3
7.8
tQH-tDQSQ
tQH-tDQSQ
70.3
7.8
13
12
12
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VCC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tREFC
tREFI
tVTD
70.3
7.8
0
0
0
0
tXSNR
tXSRD
126
200
75
75
75
200
200
200
Note: These parameters serve to support SAMSUNG components based modules
March, 2007
Rev. 4
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Notes
11. It is recommended that DQS be valid (HIGH or LOW) on or before the
WRITE command. The case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in progress on the
bus. If a previous WRITE was in progress, DQS could be high during
1. All voltages referenced to VSS
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be
conducted at normal reference / supply voltage levels, but the related specifications
and device operations are guaranteed for the full voltage range specified.
this time, depending on tDQSS
.
3. Outputs are measured with equivalent load:
12. The refresh period is 64ms. This equates to an average refresh
rate of 7.8125µs. However, an AUTO REFRESH command must be
asserted at least once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh cycles is not allowed.
V
TT
50Ω
RReeffeerreennccee
13. The valid data window is derived by achieving other specifications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window
derates directly proportional with the clock duty cycle and a practical
data valid window can be derived. The clock is allowed a maximum
duty cycled variation of 45/55. Functionality is uncertain when
operating beyond a 45/55 ratio. The data valid window derating
curves are provided below for duty cycles ranging between 50/50
and 45/55.
Outtppuutt
Poiint
(VOUT
)
30pF
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to test
the device is 1V/ns in the range between VIL(AC) and VIH(AC).
14. Referenced to each output group: x4 = DQS with DQ0-DQ3.
15. READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfied prior to the internal precharge
command being issued.
5. The AC and DC input level specifications are defined in the SSTL_2
standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
16. JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to tDS and tDH for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
6. For slew rates less than 1V/ns and greater than or equal to 0.5V/ns.
If the slew rate is less than 0.5V/ns, timing must be derated: tIS has
an additional 50ps per each 100mV/ns reduction in slew rate from
the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the
slew rate exceeds 4.5V/ns, functionality is uncertain. For 266, slew
rates must be greater than or equal to 0.5V/ns.
18. tHP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.
19. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition.
t
LZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition.
7. Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is
recognized as LOW.
20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
8. tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tRFC has been satisfied.
9. The intent of the “Don’t Care” state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above VIHDC (MIN) then it must not transition LOW
(below VIHDC) prior to tDQSH (MIN).
22. Whenever the operating frequency is altered, not including jitter, the
DLL is required to be reset. This is followed by 200 clock cycles (before
READ commands).
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
March, 2007
Rev. 4
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W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
ORDERING INFORMATION FOR JD3
Part Number
Speed
CAS Latency
tRCD
2
tRP
2
Height*
W3EG2256M72ASSR262JD3xxG
W3EG2256M72ASSR263JD3xxG
W3EG2256M72ASSR265JD3xxG
W3EG2256M72ASSR202JD3xxG
133MHz/266Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
2
2
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
3
3
2.5
2
3
3
2
2
NOTES:
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
• For part numbering interpretation, please see "part numbering guide" on page 13
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
6.35
(0.250 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
30.48
(1.20 MAX)
17.78
(0.700)
1.27
(0.050 TYP.)
2.31
(0.091)
(2x)
10.0
(0.394)
3.99
(0.157)
(MIN)
6.35
(0.250)
49.53
(1.950)
1.27
0.10
(0.050)
( 0.004)
64.77
(2.550)
3.00
(0.118)
(4x)
6.36
(0.250)
1.78
(0.070)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
March, 2007
Rev. 4
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W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
ORDERING INFORMATION FOR AJD3
Part Number
Speed
CAS Latency
tRCD
2
tRP
2
Height*
W3EG2256M72ASSR262AJD3xxG
W3EG2256M72ASSR263AJD3xxG
W3EG2256M72ASSR265AJD3xxG
W3EG2256M72ASSR202AJD3xxG
133MHz/266Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
2
2
28.70 (1.13")
28.70 (1.13")
28.70 (1.13")
28.70 (1.13")
3
3
2.5
2
3
3
2
2
NOTES:
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
• For part numbering interpretation, please see "part numbering guide" on page 13
PACKAGE DIMENSIONS FOR AJD3
133.48
(5.255" MAX.)
131.34
(5.171")
6.35
(0.250 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
28.70
(1.13 MAX)
17.78
(0.700)
2.31
(0.091)
(2x)
1.27
(0.050 TYP.)
10.0
(0.394)
3.99
(0.157)
(MIN)
6.35
(0.250)
49.53
(1.950)
1.27
0.10
(0.050)
0.004)
64.77
(2.550)
3.00
(0.118)
(4x)
6.35
(0.250)
(
1.78
(0.070)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
March, 2007
Rev. 4
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W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
ORDERING INFORMATION FOR BJD3
Part Number
Speed
CAS Latency
tRCD
2
tRP
2
Height*
W3EG2256M72ASSR262BJD3xxG
W3EG2256M72ASSR265BJD3xxG
W3EG2256M72ASSR335BJD3xxG
133MHz/266Mb/s
133MHz/266Mb/s
166MHz/333Mb/s
2
28.70 (1.13")
28.70 (1.13")
28.70 (1.13")
2.5
2.5
3
3
3
3
NOTES:
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
• For part numbering interpretation, please see "part numbering guide" on page 13
PACKAGE DIMENSIONS FOR BJD3
133.48
(5.255" MAX.)
131.34
3.81
(5.171")
(0.150 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
28.70
(1.13 MAX)
17.78
(0.700)
1.27
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
10.0
(0.050 TYP.)
(0.394)
3.99
6.35
49.53
1.27
0.10
(0.157)
(MIN)
(0.250)
(1.950)
64.77
(0.050)
( 0.004)
(2.550)
6.36
1.78
(0.070)
(0.250)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
March, 2007
Rev. 4
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W3EG2256M72ASSR-JD3
-AJD3
-BJD3
White Electronic Designs
PART NUMBERING GUIDE
AJD3
BJD3
W 3 E G 2 256M 72 A S S R xxx JD3 x x G
WEDC
MEMORY (SDRAM)
DDR
GOLD
RANKS
DEPTH (Dual)
BUS WIDTH
COMPONENT WIDTH x4
Stack TSOP
2.5V
REGISTERED
SPEED (Mb/s)
PACKAGE (184 Pin)
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(S = Samsung)
G = RoHS COMPLIANT
March, 2007
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White Electronic Designs
Document Title
4GB – 2x256Mx72, DDR SDRAM Registered ECC, w/PLL
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Initial Release
5-2-03
Advanced
1.1 Package dimension change, status
1.2 Updated CAP and IDD specs
3-15-04
Preliminary
1.3 Removed "ED" from part number
1.4 Moved from Advanced to Preliminary
1.5 Added document title page
Rev 2
Rev 3
2.1 Changed data sheet part number (W3EG72512S-JD3) to
new part numbering system.
11-04
11-04
Preliminary
Preliminary
2.2 Added part numbering guide
3.1 Added Lead-Free and RoHS note
3.2 Added vendor code options
M = Micron
S = Samsung
Rev 4
Rev 5
4.1 Added BJD3 option which uses stacked die TSOP
4.2 Updated spec to include latest Samsung die release
4.3 Added 333MHz speed offering
3-07
3-07
Final
Final
5.1 Indicated vendor source used
5.2 Updated part numbering guide
March, 2007
Rev. 4
14
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