W3EG64M64ETSU403D4IMG [WEDC]
512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM; 512MB - 64Mx64 DDR SDRAM ，无缓冲， SO- DIMM
| 型号： | W3EG64M64ETSU403D4IMG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 512MB - 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM |
| 文件： | 总12页 (文件大小：178K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY*
512MB – 64Mx64 DDR SDRAM, UNBUFFERED, SO-DIMM
FEATURES
DESCRIPTION
ꢀ
ꢀ
ꢀ
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ꢀ
Fast data transfer rate: PC3200 & PC2700
The WV3EG64M64ETSU is a 64Mx64 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eight 64Mx8 DDR
SDRAMs TSOP-II packages mounted on a 200 pin FR4
substrate.
Clock speeds of 200MHz & 166MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency : DDR400 (3 clock),
DDR333 (2.5 clock)
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
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ꢀ
ꢀ
ꢀ
Programmable Burst Length (2, 4 or 8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh, 7.8µs refresh interval (8K
(64ms refresh)
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ꢀ
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Serial presence detect (SPD) with EEPROM
Serial presence detect with EEPROM
* This product is under development, is not qualified or characterized and is subject to
change without notice.
V
CC = VCCQ = +2.5V 0.2V (166MHz)
CC = VCCQ = +2.6V 0.1V (200MHz)
V
Gold edge contacts
JEDEC standard 200 pin, small-outline, SO-DIMM
package
•
PCB height option:
D4: 31.75 mm (1.25”) TYP
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR400@CL=3
200MHz
DDR333@CL2.5
166MHz
Clock Speed
CL-tRCD-tRP
3-3-3
2.5-3-3
March 2006
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
PIN CONFIGURATION
PIN NAMES
PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL PIN# SYMBOL
Symbol
A0-A12
BA0, BA1
DQ0-DQ63
Description
Address input
Bank Address
Input/Output: Data I/Os, Data bus
1
VREF
VREF
VSS
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VSS
VSS
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
A9
A8
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
DQ42
DQ46
DQ43
DQ47
VCC
2
3
DQ19
DQ23
DQ24
DQ28
VCC
VCC
DQ25
DQ29
DQS3
DM3
VSS
VSS
VSS
4
VSS
CK0, CK0#
5
DQ0
DQ4
DQ1
DQ5
VCC
A7
Clock Input
CK1, CK1#
6
A6
VCC
VCC
CKE0
CS0#
Clock Enable Input
Chip Select Input
7
A5
8
A4
CK1#
VSS
WE#, CAS#, RAS# Command Input
9
A3
DQS0-DQS7
DM0-DM7
VCC
Data Strobe
Data Write Mask
Supply: Power Supply
Power Supply for DQS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
A2
CK1
DQS0
DM0
DQ2
DQ6
VSS
A1
VSS
A0
VSS
VCC
DQ48
DQ52
DQ49
DQ53
VCC
VCCQ
VSS
VCC
Supply: Serial EEPROM Positive
VCCSPD
DQ26
DQ30
DQ27
DQ31
VCC
VCC
NC
A10
BA1
BA0
RAS#
WE#
CAS#
CS0#
NC
Power Supply
VSS
VREF
VSS
SCL
SA0-SA2
Supply: SSTL_2 reference voltage
Supply: Ground
Serial Clock
DQ3
DQ7
DQ8
DQ12
VCC
VCC
DQS6
DM6
DQ50
DQ54
VSS
Presence Detect Address Input
Input/Output: Serial Presence-
SDA
NC
Detect Data
VCC
NC
No Connect
DQ9
DQ13
DQS1
DM1
VSS
NC
NC
NC
NC
VSS
VSS
VSS
DQ51
DQ55
DQ56
DQ60
VCC
VSS
VSS
NC
DQ32
DQ36
DQ33
DQ37
VCC
VSS
NC
DQ10
DQ14
DQ11
DQ15
VCC
NC
NC
VCC
VCC
VCC
NC
DQ57
DQ61
DQS7
DM7
VSS
VCC
DQS4
DM4
DQ34
DQ38
VSS
VCC
CK0
VCC
CK0#
VSS
VSS
VSS
NC
NC
NC
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VCC
VSS
VSS
NC
DQ35
DQ39
DQ40
DQ44
VCC
VSS
DQ16
DQ20
DQ17
DQ21
VCC
NC
VCC
VCC
VCC
NC
VCC
SDA
SA0
SCL
SA1
VCCSPD
SA2
VCC
DQ41
DQ45
DQS5
DM5
VSS
VCC
CKE0
NC
NC
A12
A11
DQS2
DM2
DQ18
DQ22
NC
NC
VSS
March 2006
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DM
DQS4
DM4
DQS
S0#
S0#
S0#
S0#
S0#
S0#
S0#
S0#
DM
DQ33
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQS
DM
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS5
DM5
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS2
DM2
DQS6
DM6
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQS
DM
DQS
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS3
DM3
DQS7
DM7
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ64
DQS
DM
DQS
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CKE0
CKE0: DDR SDRAMs
Serial PD
BA0 - BA1
BA0 - BA1: DDR SDRAMs
A0 - A12: DDR SDRAMs
SCL
SP
A0 - A12
SDA
A0
A1
A2
RAS#
CAS#
WE#
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
WE#: DDR SDRAMs
SA0 SA1 SA2
120 Ohms
120 Ohms
CK0
DDR SDRAM x 4
DDR SDRAM x 4
CK0#
V
CCSPD
SPD
DDR SDRAMs
V
CC/VCCQ
CK1
CK1#
V
REF
DDR SDRAMs
DDR SDRAMs
V
SS
Note: 1. All resistor values are 22Ω unless otherwise specified.
March 2006
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
DC OPERATING CONDITIONS
TA = 0°C to 70°C
Parameter/Condition
Symbol
VCC
VCCQ
VCC
Min
2.5
2.5
Max
2.7
2.7
Units
V
V
Notes
Supply Voltage DDR400 (nominal VCC 2.6)
I/O Supply Voltage DDR400 (nominal VCC 2.6)
Supply Voltage DDR333
2.3
2.7
V
I/O Supply Voltage DDR333
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input voltage level, CK and CK#
Input differential voltage, CK and CK#
Input crossing point voltage, CK and CK#
VCCQ
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
2.3
2.7
V
V
V
V
V
V
V
V
0.49 × VCCQ
VREF - 0.04
VREF + 0.15
-0.3
0.51 × VCCQ
VREF + 0.04
VCC + 0.30
VREF - 0.15
VCCQ + 0.30
VCCQ + 0.60
VCCQ + 0.60
1
2
-0.3
-0.3
-0.3
3
Addr, CAS#,
RAS#, WE#
-16
16
µA
CS#, CKE
CK, CK#
DM
-16
-8
-2
16
8
2
µA
µA
µA
µA
Input leakage current
II
Output leakage current
IOZ
IOH
-5
5
Output high current (normal strength)
-16.8
-16.8
-9
—
—
—
—
mA
mA
mA
mA
VOUT = v + 0.84V
Output high current (normal strength)
IOL
VOH
VOL
VOUT = v - 0.84V
Output high current (half strength)
VOUT = VTT + 0.45V
Output high current (half strength)
9
VOUT = VTT - 0.45V
Notes:
1.
V
REF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed +/-2% of the DC
values.
2.
3.
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF
.
V
ID is the magnitude of the difference between the input level on CK and the input level of CK#.
4. Industrial grade modules are specified to a DRAM tCASE of 85°C and -40°C
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN, VOUT
VCC, VCCQ
VREF
TSTG
TA
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
0 ~ 70
Units
V
V
Voltage on any in relative to VSS
Voltage on VCC & VCCQ supply relative to VSS
Voltage on VREF supply relative to VSS
Storage temperature
Operating temperature
Power dissipation
V
°C
°C
W
PD
8
Short circuit output current
IOS
50
mA
Notes:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceed.
Functional operation should be restricted to recommended operating condition.
Exposing to higher than recommended voltage for extended periods of time could affect device reliability.
March 2006
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 100MHz
Parameter
Symbol
CIN1
CIN2
CIN3
CIN4
Min
20
20
20
12
8
Max
28
28
28
16
9
Units
pF
pF
pF
pF
Input capacitance (A0 ~ A12, BA0 ~ BA1, RAS#, CAS# WE#)
Input capacitance (CKE0)
Input capacitance (CS0#)
Input capacitance (CK0, CK0#, CK1, CK1#)
Input capacitance (DM0 ~ DM7)
CIN5
pF
Input capacitance (DQ0 ~ DQ63), (DQS0 ~ DQS7)
COUT1
8
9
pF
Notes:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceed.
Functional operation should be restricted to recommended operating condition.
Exposing to higher than recommended voltage for extended periods of time could affect device reliability.
AC OPERATING CONDITIONS
Parameter
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Differential Voltage, CK and CK# inputs
Input crossing point voltage, CK and CK# input
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF + 0.31
Max
Units
V
V
V
V
VREF - 0.31
VCCQ + 0.6
0.5*VCCQ + 0.2
0.7
0.5*VCCQ - 0.2
March 2006
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
ICC SPECIFICATIONS AND CONDITIONS
0°C ≤ TA ≤ +70°C DDR400: VCC = VCCQ = +2.6V 0.1V
Max
Max
Symbol
Parameter/Condition
Units
DDR400
@CL=3
DDR333
@CL=2.5
OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN);
DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
ICC0
960
840
mA
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN);
tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
ICC1
1,200
40
1,080
40
mA
mA
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = (LOW)
ICC2P
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS,
and DM
ICC2F
ICC3P
ICC3N
ICC4R
ICC4W
240
360
240
200
mA
mA
mA
mA
mA
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode;
tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS
(MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
480
360
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
1,240
1,400
1,120
1,200
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
ICC5
ICC6
AUTO REFRESH BURST CURRENT:
tREFC = tRFC (MIN)
1,760
40
1,640
40
mA
mA
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge,
tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during
Active READ, or WRITE commands
ICC7
3,080
2,880
mA
Notes:
CC parameters are based on SAMSUNG components. Other DRAM manufactures parameter may be different
I
March 2006
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
ICC SPECIFICATIONS AND CONDITIONS
0°C ≤ TA ≤ +70°C, DDR400: VCC = VCCQ = +2.6V 0.1V
Max
Max
Symbol
Parameter/Condition
Units
DDR400
@CL=3
DDR333
@CL=2.5
OPERATING CURRENT: One device bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN);
DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
ICC0
1,040
mA
TBD
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst = 4; tRC = tRC (MIN);
tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
ICC1
1,280
40
mA
mA
TBD
TBD
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = (LOW)
ICC2P
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle; tCK = tCK (MIN); CKE =
HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS,
and DM
ICC2F
ICC3P
ICC3N
ICC4R
ICC4W
360
280
mA
mA
mA
mA
mA
TBD
TBD
TBD
TBD
TBD
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode;
tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS
(MAX); tCK = tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
400
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA
1,320
1,400
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address
and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs
changing twice per clock cycle
ICC5
ICC6
AUTO REFRESH BURST CURRENT:
tREFC = tRFC (MIN)
2,320
40
mA
mA
TBD
TBD
SELF REFRESH CURRENT: CKE ≤ 0.2V
OPERATING CURRENT: Four device bank interleaving READs (Burst = 4) with auto precharge,
tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during
Active READ, or WRITE commands
ICC7
3,240
mA
TBD
Notes:
CC parameters are based on MICRON components. Other DRAM manufactures parameter may be different
I
March 2006
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C;
AC Characteristics
403
335
Parameter
Row Cycle Time
Refresh row cycle time
Row active
RAS# to CAS# delay
Row percharge time
Row active to row active delay
Write recovery time
Last data in to READ command
Symbol
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
Min
55
70
40
15
15
10
15
2
Max
Min
60
72
42
18
18
12
15
1
Max
Units
tCK
ps
ps
tCK
ns
ns
ns
ns
70K
70K
CL = 2.5
CL = 3
6
5
12
10
6
12
ns
ns
Clock cycle time
tCK
CK high-level width
CK low-level width
Access window of DQS from CK/CK#
Access window of DQs from CK/CK#
tCH
tCL
tDQSCK
tAC
0.45
0.45
-0.55
-0.65
-
0.55
0.55
+0.55
+0.65
0.4
0.45
0.45
-0.6
-0.7
-
0.55
0.55
+0.6
+0.7
0.4
tCK
tCK
ns
ns
ns
DQS-DQ skew, DQS to last DQ valid, per group, per
tDQSQ
access
Read preamble
Read postamble
CK to valid DQS-in
DQS-in setup time
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
0.9
0.4
0.72
0
0.25
0.2
0.2
1.1
0.6
1.28
0.9
0.4
0.75
0
0.25
0.2
0.2
1.1
0.6
1.25
tCK
tCK
tCK
ns
tCK
tCK
tCK
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge to CK rising-hold time
Notes:
tDSH
Industrial grade modules are specified to a DRAM tCASE of 85°C and -40°C
Continued on next page
March 2006
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C
AC Characteristics
403
335
Units
Parameter
DQS-in high level width
DQS-in low level width
Symbol
tDQSH
tDQSL
tISF
tIHF
tISs
tIHS
tHZ
tLZ
tMRD
tDS
Min
0.35
0.35
0.6
0.6
0.7
Max
Min
0.35
0.35
0.75
0.75
0.8
Max
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
µs
ns
ns
ns
ns
ns
Address and control input setup time (fast)
Address and control input hold time (fast)
Address and control input setup time (slow)
Address and control input hold time (slow)
Data-out high-impedance time from CK/CK#
Data-out low-impedance time from CK/CK#
Mode register set cycle
DQ and DM input setup time to DQS
DQ and DM input hold time to DQS
Control & address input pulse width
DQ & DM input pulse width
0.7
0.8
+0.65
+0.70
-0.65
10
0.4
0.4
2.2
1.75
75
200
-0.70
12
0.45
0.45
2.2
1.75
75
200
tDH
tIPW
tDIPW
tXSNR
tXSRD
tREFI
tQH
Exit self refresh to non-Read command
Exit self refresh to Read command
Refresh interval time
7.8
7.8
Output DQS valid window
tHP - tQHS
tHP - tQHS
Clock Half period
Data hold skew factor
DQS write postable
Active read with auto precharge command
tHP
tCL(MIN) or tCH(MAX)
tCL(MIN) or tCH(MAX)
tQHS
tWPST
tRAP
0.5
0.6
0.5
0.6
0.4
15
0.4
18
tWR/ CK
t
tWR/tCK
Auto precharge write recovery + precharge time
tDAL
tCK
tRP+/tCK
tRP+/tCK
Notes:
Industrial grade modules are specified to a DRAM tCASE of 85°C and -40°C
March 2006
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR D4
Part Number
Speed
CAS Latency
tRCD
3
tRP
3
Height*
WV3EG64M64ETSU403D4xxG
WV3EG64M64ETSU335D4xxG
200MHz/400Mbps
166MHz/333Mbps
3
31.75 (1.25") TYP
31.75 (1.25") TYP
2.5
3
3
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
200-PIN DDR2 SO-DIMM DIMENSIONS
FRONT VIEW
3.80 (0.150)
MAX
67.75 (2.667)
67.45 (2.656)
4.10 (0.161)
(2X)
3.90( 0.154)
31.90 (1.256)
31.60 (1.244)
1.80 (0.071)
(2X)
20.00 (0.787)
TYP
6.000 (.236)
2.55 (0.100)
1.10 (0.043)
0.90 (0.035)
2.15 (0.085)
1.00 (0.039)
TYP
0.45 (0.018)
TYP
0.60 (0.024)
TYP
PIN 199
PIN 1
2.504 (63.60)
TYP
BACK VIEW
0.165 (4.2)
TYP
PIN 200
PIN 2
1.866 (47.40)
TYP
0.449 (11.40)
TYP
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
March 2006
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
PART NUMBERING GUIDE
W 3 E G 64M 64 E T S U xxx D4 x x G
WEDC
MEMORY (SDRAM)
DDR
GOLD
DEPTH)
BUS WIDTH
x8
TSOP
(400M/bs = VCC/VCCQ = +2.6V 0.1V)
2.5V
UNBUFFERED
SPEED (Mbs)
PACKAGE 200 PIN
TEMPERATURE RANGE
(Blank = 0°C - 70°C ambient)
(I = -40°C to 85°C DRAM case temp)
COMPONENT VENDOR NAME
(M = MICRON)
(S = SAMSUNG)
G = RoHS COMPLIANT
March 2006
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG64M64ETSU-D4
White Electronic Designs
PRELIMINARY
Document Title
512MB - 64Mx64 DDR SDRAM, UNBUFFERED SO-DIMM
Revision History
Rev #
History
Release Date Status
Rev 0
Created
3-06
Preliminary
March 2006
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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