W3EG7235S202JD3 [WEDC]
256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL; 256MB - 2x16Mx72 DDR SDRAM ECC挂号，W / PLL
| 型号： | W3EG7235S202JD3 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| 文件： | 总12页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY*
256MB – 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL
FEATURES
DESCRIPTION
The WED3DG7235S is a 2x16Mx72 Double Data Rate
SDRAM memory module based on 128Mb DDR SDRAM
component. The module consists of eighteen 16Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184 pin
FR4 substrate.
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Double-data-rate architecture
Speeds of 100MHz and 133MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK# & CK)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Edge aligned data output, center aligned data
input
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Auto and self refresh
Serial presence detect
Dual Rank
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Power supply: 2.5V 0.20V
JEDEC standard 184 pin DIMM package
•
Package height option:
JD3 30.48 mm (1:20")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
DDR200 @CL=2
100MHz
Clock Speed
CL-tRCD-tRP
2-2-2
November 2004
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
PIN CONFIGURATION
PIN NAMES
A0-A12
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
CK0
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
Data Strobe Input/Output
Clock Input
PIN#
1
2
3
4
5
6
7
SYMBOL
PIN#
SYMBOL
DQS8
A0
CB2
VSS
CB3
BA1
DQ32
PIN#
93
94
95
96
97
98
99
SYMBOL
PIN#
SYMBOL
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VCC
DQ3
NC
RESET#
VSS
DQ8
DQ9
DQS1
VCCQ
*CK1
*CK1#
VSS
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
47
48
49
50
51
52
53
54
55
56
57
56
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VSS
DQ4
DQ5
VCCQ
DQM0
DQ6
DQ7
VSS
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VSS
DQM8
A10
CB6
VCCQ
CB7
CK0#
Clock input
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
DQM0-DQM8
VCC
VCCQ
VSS
VREF
VCCSPD
SDA
SCL
SA0-SA2
VCCID
NC
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data-In Mask
Power Supply
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
VSS
8
9
VCCQ
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
DQ36
DQ37
VCC
DQM4
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
CS1#
DQM5
VSS
DQ46
DQ47
NC
VCCQ
DQ52
DQ53
A13*
VCC
DQM6
DQ54
DQ55
VCCQ
NC
DQ60
DQ61
VSS
DQ33
DQS4
DQ34
VSS
NC
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
VCCQ
DQ12
DQ13
DQM1
VCC
DQ14
DQ15
CKE1
VCCQ
*BA2
DQ20
A12
VSS
DQ21
A11
DQM2
VCC
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VCCQ
DQM3
A3
DQ30
VSS
DQ31
CB4
CB5
VCCQ
CK0
CK0#
BA0
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
VCC
*CS2#
DQ48
DQ49
VSS
*CK2#
*CK2
VCCQ
DQS6
DQ50
DQ51
VSS
Serial clock
Address in EEPROM
VCC Indentification Flag
No Connect
RESET#
Reset Enable
* Not Used
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
VCC
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VCC
DQS16
DQ62
DQ63
VCCQ
SA0
SA1
SA2
NC
SDA
SCL
VCCSPD
November 2004
Rev. 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
RCS1#
RCS0#
DQS0
DQM0
DQS4
DQM4
DM
7
CS# DQS
CS# DQS
CS# DQS
CS# DQS
CS# DQS
DM
CS# DQS
CS# DQS
CS# DQS
CS# DQS
CS# DQS
DM
7
CS# DQS
CS# DQS
CS# DQS
CS# DQS
DM
CS# DQS
CS# DQS
CS# DQS
CS# DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
1
0
0
5
2
5
2
4
3
4
5
4
3
4
5
3
3
2
2
DQS1
DQM1
DQS5
DQM5
DM
7
DM
DM
7
DM
DQ8
DQ9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
1
1
0
0
5
2
5
2
4
3
4
5
4
3
4
5
3
3
2
2
DQS2
DQM2
DQS6
DQM6
DM
7
DM
DM
7
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
1
0
0
5
2
5
2
4
3
4
5
4
3
4
5
3
3
2
2
DQS3
DQM3
DQS7
DQM7
DM
7
DM
DM
7
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
1
0
0
5
2
5
2
4
3
4
5
4
3
4
5
3
3
2
2
DQS8
DQM8
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
REGISTER X 2
DM
7
DM
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
6
7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
120
6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CK0
CK0#
1
PLL
0
5
2
4
3
4
5
3
2
SERIAL PD
SCL
WP
SDA
A0 A1 A2
CS0#
CS1#
BA0-BA1
A0-A12
RAS#
CAS#
CKE0
CKE1
WE#
RCS0#
RCS1#
RBA0- RBA1
RA0 - RA12
RRAS#
RCAS#
RCKE0
RCKE1
RWE#
R
E
G
I
S
T
E
R
SA0 SA1 SA2
BA0-BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE: DDR SDRAMs
CKE: DDR SDRAMs
WE#: DDR SDRAMs
VCCSPD
SPD
VCCQ
DDR SDRAMS
DDR SDRAMS
DDR SDRAMS
DDR SDRAMS
VCC
PCK
PCK#
VREF
RESET#
VSS
NOTE: All resistor values are 22 ohms unless otherwise specified
November 2004
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
9
Units
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
V
°C
W
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
TA = 0°C to 70°C, VCC = 2.5V 0.2V
Parameter
Symbol
VCC
Min
2.3
Max
2.7
Unit
V
Supply Voltage
Supply Voltage
VCCQ
VREF
VTT
2.3
2.7
V
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
1.15
1.35
V
1.15
1.35
V
VIH
VREF+0.15
-0.3
VCCQ+0.3
VREF+0.15
—
V
VIL
V
VOH
VTT+0.76
—
V
VOL
VTT-0.76
V
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 2.5V
Parameter
Symbol
CIN1
Max
6.25
6.25
6.25
5.5
Unit
Input Capacitance (A0-A12)
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
CIN2
CIN3
Input Capacitance (CK0#,CK0)
Input Capacitance (CS0#)
CIN4
CIN5
6.25
13
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
CIN6
CIN7
6.25
13
COUT
COUT
13
November 2004
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
Includes PLL and Register Power
Rank2
Stand By
State
DDR266@CL = 2 DDR266@CL = 2.5 DDR200@CL = 2
Parameter
Rank 1
Conditions
One device bank; Active = Precharge; tRC = tRC(MIN);
CK = tCK(MIN); DQ,DM and DQS inputs changing
Max
Max
Max
Units
Operating Current
IDD0
2475
2340
2340
mA
IDD3N
t
once per clock cycle; Address and control inputs
changing once every two cycles.
Operating Current
IDD1
One device bank; Active-Read-Precharge; Burst = 2;
2565
2475
2475
mA
IDD3N
t
RC = tRC(MIN);tCK = tCK (MIN); Iout = 0mA; Address
and control inputs changing once per clock cycle.
All device banks idle; Power- down mode; tCK
tCK(MIN); CKE = (low)
Precharge Power-
IDD2P
IDD2F
=
54
54
54
mA
mA
IDD2P
IDD2F
Down Standby Current
dle Standby Current
CS# = High; All device banks idle; tCK = tCK(MIN);
CKE = high; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ,
DQS and DM.
1120
1030
1030
Active Power-Down
Standby Current
IDD3P
IDD3N
One device bank active; Power-down mode;
450
360
360
mA
mA
IDD3P
IDD3N
t
CK(MIN); CKE = (low)
Active Standby Current
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC = tRAS(MAX); tCK = tCK(MIN); DQ,
DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle.
1210
1120
1120
Operating Current
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK = tCK(MIN); IOUT = 0mA.
2655
2610
2520
2475
2520
2475
mA
mA
IDD3N
IDD4W
Burst = 2; Writes; Continous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK = tCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
IDD3N
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5
IDD6
tRC = tRC(MIN)
3500
329
3410
311
3375
346
mA
mA
mA
IDD3N
IDD6
CKE ≤ 0.2V
IDD7A
Four bank interleaving Reads (BL = 4) with auto
precharge with tRC = tRC (MIN); tCK = tCK(MIN);
Address and control inputs change only during Active
Read or Write commands.
4455
4320
4320
IDD3N
November 2004
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
Includes DDR SDRAM Components Only
Rank2
Stand By
State
DDR266@CL = 2 DDR266@CL = 2.5 DDR200@CL = 2
Parameter
Rank 1
Conditions
One device bank; Active = Precharge; tRC = tRC(MIN);
CK = tCK(MIN); DQ,DM and DQS inputs changing
Max
Max
Max
Units
Operating Current
IDD0
1890
1755
1755
mA
IDD3N
t
once per clock cycle; Address and control inputs
changing once every two cycles.
Operating Current
IDD1
One device bank; Active-Read-Precharge; Burst = 2;
1980
1890
1890
mA
IDD3N
t
RC = tRC(MIN);tCK = tCK (MIN); Iout = 0mA; Address
and control inputs changing once per clock cycle.
All device banks idle; Power- down mode; tCK
tCK(MIN); CKE = (low)
Precharge Power-
IDD2P
IDD2F
=
54
54
54
mA
mA
IDD2P
IDD2F
Down Standby Current
dle Standby Current
CS# = High; All device banks idle; tCK = tCK(MIN);
CKE = high; Address and other control inputs
changing once per clock cycle. VIN = VREF for DQ,
DQS and DM.
810
720
720
Active Power-Down
Standby Current
IDD3P
IDD3N
One device bank active; Power-down mode;
450
900
360
810
360
810
mA
mA
IDD3P
IDD3N
t
CK(MIN); CKE = (low)
Active Standby Current
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC = tRAS(MAX); tCK = tCK(MIN); DQ,
DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle.
Operating Current
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK = tCK(MIN); IOUT = 0mA.
2070
2025
1935
1890
1935
1890
mA
mA
IDD3N
IDD4W
Burst = 2; Writes; Continous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK = tCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
IDD3N
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5
IDD6
tRC = tRC(MIN)
2880
54
2790
36
2790
36
mA
mA
mA
IDD3N
IDD6
CKE ≤ 0.2V
IDD7A
Four bank interleaving Reads (BL = 4) with auto
precharge with tRC = tRC (MIN); tCK = tCK(MIN);
Address and control inputs change only during Active
Read or Write commands.
3870
3735
3735
IDD3N
November 2004
Rev. 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
4. Timing Patterns :
•
•
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
•
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
November 2004
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C; VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V
AC Characteristics
262/265
202
Parameter
Symbol
tAC
Min
-0.75
0.45
0.45
7.5
Max
+0.75
0.55
0.55
13
Min
-0.8
0.45
0.45
8
Max
+0.8
0.55
0.55
13
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
tCH
16
16
tCL
Clock cycle time
CL=2.5
CL=2
tCK (2.5)
tCK (2)
tDH
22
7.5/10
0.5
13
10
13
22
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
0.6
0.6
2
14,17
14,17
17
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
1.75
-0.75
0.35
0.35
+0.75
-0.8
0.35
0.35
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
0.5
0.6
13,14
0.75
0.2
1.25
0.75
0.2
1.25
0.2
0.2
tCH, tCL
tCH, tCL
18
8,19
8,20
6
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
Address and control input hold time (fast slew rate)
Address and control input set-up time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
tHZ
+0.75
+0.8
tLZ
-0.75
0.90
0.90
1
-0.8
1.1
1.1
1.1
1.1
2.2
16
tIHf
tISf
6
tIHs
6
tISs
1
6
tIPW
2.2
15
tMRD
tQH
tHP-tQHS
tHP-tQHS
13,14
15
tQHS
tRAS
tRAP
tRC
0.75
120,000
1
120,000
ACTIVE to PRECHARGE command
40
15
60
75
40
20
70
80
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
tRFC
21
November 2004
Rev. 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
0°C ≤ TA ≤ +70°C; VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V
AC Characteristics
262/265
202
Parameter
Symbol
tRCD
Min
15
Max
Min
20
Max
Units
ns
Notes
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
tRP
15
20
ns
tRPRE
tRPST
tRRD
0.9
0.4
12
1.1
0.6
0.9
0.4
15
1.1
0.6
tCK
tCK
ns
19
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
0.25
0
tCK
ns
DQS write preamble setup time
DQS write postamble
10,11
9
0.4
15
0.6
0.4
15
0.6
tCK
ns
Write recovery time
Internal WRITE to READ command delay
Data valid output window
tWTR
1
1
tCK
ns
NA
tQH-tDQSQ
tQH-tDQSQ
13
12
12
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VCC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tREFC
tREFI
140.6
15.6
140.6
15.6
μs
μs
tVTD
0
0
ns
tXSNR
tXSRD
75
80
ns
200
200
tCK
November 2004
Rev. 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
Notes
11. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
1.
2.
All voltages referenced to VSS
Tests for AC timing, IDD, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specifications and device operations are guaranteed for
the full voltage range specified.
high during this time, depending on tDQSS
.
12. The refresh period is 64ms. This equates to an average refresh
rate of 15.625µs. However, an AUTO REFRESH command must
be asserted at least once every 140.6µs; burst refreshing or
posting by the DRAM controller greater than eight refresh cycles is
not allowed.
3.
Outputs are measured with equivalent load:
V
TTT
50Ω
RReeffeerreennccee
Outtppuut
13. The valid data window is derived by achieving other specifications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid
window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
Poiint
30pF
(VOUT
)
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
14. Referenced to each output group: x8 = DQS with DQ0-DQ7.
15. READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfied prior to the internal precharge
command being issued.
5.
6.
The AC and DC input level specifications are defined in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
16. JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to tDS and tDH for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
For slew rates less than 1V/ns and greater than or equal to 0.5V/
ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS
has an additional 50ps per each 100mV/ns reduction in slew rate
from the 500mV/ns. tIH has 0ps added, that is, it remains constant.
If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403
and 335, slew rates must be greater than or equal to 0.5V/ns.
18.
t
HP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.
19.
t
HZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX)
7.
8.
Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is
recognized as LOW.
condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX)
condition.
20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tRFC has been satisfied.
9.
The intent of the “Don’t Care” state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above VIHDC (MIN) then it must not transition
LOW (below VIHDC) prior to tDQSH (MIN).
22. Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
November 2004
Rev. 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
ORDER INFORMATION FOR JD3
Part Number
Speed
CAS Latency
tRCD
tRP
Height*
133MHz/266Mbps
2
2
2
W3EG7235S262JD3
W3EG7235S265JD3
W3EG7235S202JD3
NOTES:
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
133MHz/266Mbps
100MHz/200Mbps
2.5
2
3
2
3
2
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
4.06
(0.160 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
3.99
(0.157)
(MIN)
30.48
(1.20 MAX)
17.78
(0.700)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27
10.01
(0.050 TYP.)
(0.394)
6.35
(0.250)
49.53
(1.950)
64.77
1.27 0.10
(0.050 0.004)
(2.550)
6.35
1.78
(0.070)
(0.250)
ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
November 2004
Rev. 2
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7235S-JD3
White Electronic Designs
PRELIMINARY
Document Title
256MB - 32Mx72 DDR SDRAM REGISTERED ECC
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Rev 2
Initial Release
5-22-02
2-13-04
11-04
Advanced
Preliminary
Preliminary
1.1 Removed "ED" from part marking
2.1 Added AC specs
November 2004
Rev. 2
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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