W3EG7236S262D3 [WEDC]
256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL; 256MB - 32Mx72 DDR SDRAM注册瓦特/ PLL型号: | W3EG7236S262D3 |
厂家: | WHITE ELECTRONIC DESIGNS CORPORATION |
描述: | 256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL |
文件: | 总12页 (文件大小:173K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
W3EG7236S-D3
White Electronic Designs
PRELIMINARY*
256MB – 32Mx72 DDR SDRAM REGISTERED, w/PLL
FEATURES
DESCRIPTION
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Speeds of 100MHz and 133 MHz
The W3EG7236S is a 32Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR
SDRAM component. The module consists of nine
32Mx8 DDR SDRAMs in 66 pin TSOP package
mounted on a 184 Pin FR4 substrate.
Double-data-rate architecture
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
Serial presence detect
* This product is under development, is not qualified or characterized and is subject to
change without notice.
184 pin DIMM package
Power Supply: 2.5V 0.20V
OPERATING FREQUENCIES
DDR266 @CL=2
133MHz
DDR266 @CL=2.5
133MHz
DDR200 @CL=2
100MHz
Clock Speed
CL-tRCD-tRP
2-3-3
2.5-3-3
2-2-2
November 2004
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
PIN CONFIGURATIONS
PIN NAMES
PIN
1
2
3
4
5
6
7
8
SYMBOL
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VCC
DQ3
NC
RESET#
VSS
DQ8
DQ9
DQS1
VCCQ
*CK1
*CK1#
VSS
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
PIN
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
SYMBOL
DQS8
A0
CB2
VSS
PIN
93
94
95
96
97
98
99
SYMBOL
VSS
PIN
139
140
141
VCC
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
SYMBOL
VSS
DQM8
A10
CB6
VCCQ
CB7
A0 – A12
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
CK0
CK0#
CKE0
CS0#
RAS#
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
Data Strobe Input/Output
Clock Input
DQ4
DQ5
VCCQ
DQM0
DQ6
DQ7
VSS
CB3
BA1
Clock Input
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
VSS
Clock Enable Input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
DQ36
DQ37
VCC
DQM4
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
*CS1#
DQM5
VSS
DQ46
DQ47
*CS3#
VCCQ
DQ52
DQ53
NC
9
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
CAS#
WE#
*A13
VCCQ
DQ12
DQ13
DQM1
VCC
DQ14
DQ15
CKE1
VCCQ
*BA2
DQ20
A12
VSS
DQ21
A11
DQM2
VCC
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VCCQ
DQM3
A3
DQ30
VSS
DQ31
CB4
CB5
VCCQ
CK0
DQM0-DQM8 Data-In Mask
VCC
VCCQ
VSS
VREF
VCCSPD
BA0
Power Supply (2.5V)
Power Supply for DQS (2.5V)
Ground
Power Supply for Reference
Serial EEPROM Power Supply
(2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
VCC Identification Flag
No Connect
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
VCC
*CK2#
DQ48
DQ49
VSS
*CK2#
*CK2
VCCQ
DQS6
DQ50
DQ51
VSS
SDA
SCL
SA0-SA2
VCCID
NC
RESET#
VCCID
Reset Enable
VCC Identification Flag
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
* Note Used
VCC
DQM6
DQ54
DQ55
VCCQ
NC
DQ60
DQ61
VSS
DQM7
DQ62
DQ63
VCCQ
SA0
DQ25
DQS3
A4
VCCIQ
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
VCC
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VCC
NC
SDA
SCL
SA1
SA2
VCC SPD
CK0#
November 2004
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
RCS0#
DQS0
DQM0
DQS4
DQM4
DM RCS0# DQS
DQ0
DM RCS0# DQS
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ1
DQ1
DQ2
DQ2
DQ3
DQ3
DQ4
DQ4
DQ5
DQ5
DQ6
DQ6
DQ7
DQ7
DQS1
DQM1
DQS5
DQM5
DM RCS0# DQS
DQ0
DM RCS0# DQS
DQ0
DQ8
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ9
DQ1
DQ1
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ2
DQ2
DQ3
DQ3
DQ4
DQ4
DQ5
DQ5
DQ6
DQ6
DQ7
DQ7
DQS2
DQM2
DQS6
DQM6
DM RCS0# DQS
DQ0
DM RCS0# DQS
DQ0
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ1
DQ1
DQ2
DQ2
DQ3
DQ3
DQ4
DQ4
DQ5
DQ5
DQ6
DQ6
DQ7
DQ7
DQS3
DQM3
DQS7
DQM7
DM RCS0# DQS
DQ0
DM RCS0# DQS
DQ0
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ1
DQ1
DQ2
DQ2
DQ3
DQ3
DQ4
DQ4
DQ5
DQ5
DQ6
DQ6
DQ7
DQ7
DQS8
DQM8
DDR SDRAM
DM RCS0# DQS
DQ0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR SDRAM
REGISTER X 2
DQ1
120
DQ2
CK0
CK0#
DQ3
PLL
DQ4
DQ5
DQ6
DQ7
SERIAL PD
R
E
G
I
SCL
WP
SDA
CS0#
BA0, BA1
A0-A11/12
RAS#
RCS0#
A0 A1 A2
RBA0, RBA1
RA0-RA11/12
RRAS#
RCAS#
RCKE0
SA0 SA1 SA2
S
T
E
R
S
CAS#
CKE0
VDDSPD
VDDQ
SPD
WE#
RWE#
DDR SDRAMS
VDD
VREF
VSS
DDR SDRAMS
DDR SDRAMS
DDR SDRAMS
CK
CK#
RESET#
NOTE: All resistor values are 22 ohms unless otherwise specified.
November 2004
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
V
V
°C
W
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
-0.5 to 3.6
-1.0 to 3.6
-55 to +150
9
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V 0.2V
Parameter
Symbol
VCC
Min
2.3
Max
2.7
Unit
V
Supply Voltage
Supply Voltage
VCCQ
VREF
VTT
2.3
2.7
V
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
1.15
1.35
V
1.15
1.35
V
VIH
VREF + 0.15
-0.3
VCCQ + 0.3
VREF -0.15
—
V
VIL
V
VOH
VTT + 0.76
—
V
VOL
VTT-0.76
V
CAPACITANCE
TA = 25°C. f = 1MHz, VCC = 2.5V
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0#,CK0)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT
Max
6.5
6.5
6.5
5.5
6.5
8
6.5
8
8
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
November 2004
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
Includes DDR SDRAM component only
DDR266@CL=2
Max
DDR266@CL=2.5
DDR200@CL=2
Parameter
Symbol Conditions
IDD0
Units
Max
Max
Operating Current
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
810
720
675
mA
Operating Current
IDD1
One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
1080
27
990
27
900
27
mA
rnA
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
225
315
180
270
162
225
mA
mA
Active Power-Down
Standby Current
IDD3P
IDD3N
One device bank active; Power-Down
mode; tCK (MIN); CKE=(low)
Active Standby
Current
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
495
1530
1530
405
1260
1260
360
1080
1035
mA
mA
rnA
Operating Current
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
IDD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
Auto Refresh
Current
IDD5
tRC = tRC (MIN)
1620
27
1485
27
1350
27
mA
mA
Self Refresh Current
Operating Current
IDD6
CKE ≤ 0.2V
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
2925
2520
2115
mA
November 2004
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
Includes PLL and register power
DDR266@CL=2
Max
DDR266@CL=2.5
DDR200@CL=2
Parameter
Symbol Conditions
IDD0
Units
Max
Max
Operating Current
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
1120
1030
985
mA
Operating Current
IDD1
One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
1390
27
1300
27
1210
27
mA
rnA
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
535
315
490
270
472
225
mA
mA
Active Power-Down
Standby Current
IDD3P
IDD3N
One device bank active; Power-Down
mode; tCK (MIN); CKE=(low)
Active Standby
Current
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
805
1840
1840
715
1570
1570
670
1390
1345
mA
mA
rnA
Operating Current
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
IDD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
Auto Refresh
Current
IDD5
tRC = tRC (MIN)
1930
337
1795
337
1660
337
mA
mA
Self Refresh Current
Operating Current
IDD6
CKE ≤ 0.2V
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
3536
2831
2426
mA
November 2004
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
4. Timing Patterns :
•
•
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
•
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
November 2004
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C; VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V
AC Characteristics
262/265
202
Parameter
Symbol
tAC
Min
-0.75
0.45
0.45
7.5
Max
+0.75
0.55
0.55
13
Min
-0.8
0.45
0.45
8
Max
+0.8
0.55
0.55
13
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
tCH
16
16
tCL
Clock cycle time
CL=2.5
CL=2
tCK (2.5)
tCK (2)
tDH
22
7.5/10
0.5
13
10
13
22
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
0.6
0.6
2
14,17
14,17
17
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
1.75
-0.75
0.35
0.35
+0.75
-0.8
0.35
0.35
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
0.5
0.6
13,14
0.75
0.2
1.25
0.75
0.2
1.25
0.2
0.2
tCH, tCL
tCH, tCL
18
8,19
8,20
6
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
Address and control input hold time (fast slew rate)
Address and control input set-up time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
tHZ
+0.75
+0.8
tLZ
-0.75
0.90
0.90
1
-0.8
1.1
1.1
1.1
1.1
2.2
16
tIHf
tISf
6
tIHs
6
tISs
1
6
tIPW
2.2
15
tMRD
tQH
tHP-tQHS
tHP-tQHS
13,14
15
tQHS
tRAS
tRAP
tRC
0.75
120,000
1
120,000
ACTIVE to PRECHARGE command
40
20
65
75
40
20
70
80
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
tRFC
21
November 2004
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
0°C ≤ TA ≤ +70°C; VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V
AC Characteristics
262/265
202
Parameter
Symbol
tRCD
Min
20
Max
Min
20
Max
Units
ns
Notes
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
tRP
20
20
ns
tRPRE
tRPST
tRRD
0.9
0.4
15
1.1
0.6
0.9
0.4
15
1.1
0.6
tCK
tCK
ns
19
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
0.25
0
tCK
ns
DQS write preamble setup time
DQS write postamble
10,11
9
0.4
15
0.6
0.4
15
0.6
tCK
ns
Write recovery time
Internal WRITE to READ command delay
Data valid output window
tWTR
1
1
tCK
ns
NA
tQH-tDQSQ
tQH-tDQSQ
13
12
12
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VCC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tREFC
tREFI
70.3
7.8
70.3
7.8
μs
μs
tVTD
0
0
ns
tXSNR
tXSRD
75
80
ns
200
200
tCK
November 2004
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
Notes
1.
2.
All voltages referenced to VSS
11. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
Tests for AC timing, IDD, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specifications and device operations are guaranteed for
the full voltage range specified.
high during this time, depending on tDQSS
.
12. The refresh period is 64ms. This equates to an average refresh
rate of 15.625µs. However, an AUTO REFRESH command must
be asserted at least once every 140.6µs; burst refreshing or
posting by the DRAM controller greater than eight refresh cycles is
not allowed.
3.
Outputs are measured with equivalent load:
VTT
50ΩΩ
13. The valid data window is derived by achieving other specifications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid
window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
RReeffeerreennccee
Outputt
Point
30ppFF
(VOUT
)
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
14. Referenced to each output group: x4 = DQS with DQ0-DQ4.
15. READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfied prior to the internal precharge
command being issued.
5.
6.
The AC and DC input level specifications are defined in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
16. JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to tDS and tDH for each
100mV/ns reduction in slew rate. If slew rates exceeds 4V/ns,
functionality is uncertain.
Command/Address input slew rate = 0.5V/ns. For -75 with slew
rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the
slew rate is less than 0.5V/ns, timing must be derated: tIS has an
additional 50ps per each 100mV/ns reduction in slew rate from the
500mV/ns. tIH has 0ps added, that is, it remains constant. If the
slew rate exceeds 4.5V/ns, functionality is uncertain.
18.
t
HP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.
19. This maximum value is derived from the referenced test load. In
practice, the values obtained in a typical terminated design may
reflect up to 310ps less for tHZ (MAX) and last DVW. tHZ (MAX) will
prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN)
will prevail over tDQSCK (MIN) + PRE (MAX) condition.
7.
8.
Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is
recognized as LOW.
tHZ and tLZ transitions occur in the same access time windows as
20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tREF later.
9.
The maximum limit for this parameter is not a device limit. The
device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
22. Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
November 2004
Rev. 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
ORDER INFORMATION FOR D3
Part Number
Speed
CAS Latency
tRCD
2
3
tRP
2
3
Height*
W3EG7236S262D3
W3EG7236S265D3
W3EG7236S202D3
133MHz/266Mbps
133MHz/266Mbps
100MHz/200Mbps
2
2.5
2
26.67 (1.05")
26.67 (1.05")
26.67 (1.05")
2
2
PACKAGE DIMENSIONS FOR D3
133.48
(5.255)
MAX
3.99
(0.157)
(4X)
4.06
(0.160)
MAX
3.99
(0.157)
MAX
26.67
(1.050)
MAX
17.78
(0.700)
1.27 (0.050) TYP
10.01
6.35
49.53
(0.394)
3.00
(0.118)
(4X)
(0.250)
(1.950)
1.27 0.10
(0.050 0.004)
64.77
(2.550)
6.35
1.78
(0.070)
(0.250)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
November 2004
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7236S-D3
White Electronic Designs
PRELIMINARY
Document Title
256MB – 32Mx72 DDR SDRAM REGISTERED, w/PLL
Revision History
Rev #
History
Release Date Status
Rev A
Rev B
Rev 0
Created
1-23-02
5-21-02
6-04
Advanced
Advanced
Preliminary
Corrected mechanical drawing
0.1 Updated CAP and IDD specs
0.2 Changed status from Advanced to Preliminary
0.3 Removed "ED" from part number
Rev 1
1.1 Added AC Specs
11-04
Preliminary
November 2004
Rev. 1
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号:
©2020 ICPDF网 联系我们和版权申明