W3EG7263S-JD3 [WEDC]
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL; 512MB- 64Mx72 DDR SDRAM挂号W / PLL
| 型号： | W3EG7263S-JD3 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL |
| 文件： | 总13页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY*
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL
FEATURES
DESCRIPTION
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Double-data-rate architecture
The W3EG7263S is a 64Mx72 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
component. The module consists of eighteen 64Mx4 DDR
SDRAMs in 66 pin TSOP package mounted on a 184 Pin
FR4 substrate.
Clock Speeds: 100MHz, 133MHz and 166MHz
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lenths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
Serial presence detect
Power supply: VCC: 2.5V 0.2V
This product is under development, is not qualified or characterized and is subject to
change without notice.
JEDEC standard 184 pin DIMM package
•
Package height options:
JD3: 30.48mm (1.20") and
AJD3: 28.70mm (1.13")
OPERATING FREQUENCIES
DDR333 @CL=2.5
DDR266 @CL=2
133MHz
DDR266 @CL=2
133MHz
DDR266 @CL=2.5
133MHz
DDR200 @CL=2
100MHz
Clock Speed
CL-tRCD-tRP
166MHz
2.5-3-3
2-2-2
2-3-3
2.5-3-3
2-2-2
April 2004
Rev. # 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
PIN CONFIGURATION
PIN NAMES
A0-A12
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
BA0-BA1
DQ0-DQ63
CB0-CB7
1
VREF
DQ0
VSS
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
DQS8
A0
93
94
VSS
DQ4
DQ5
VCCQ
DQS9
DQ6
DQ7
VSS
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VSS
DQS17
A10
2
3
CB2
95
DQS0-DQS17 Data Strobe Input/Output
CK0
4
DQ1
DQS0
DQ2
VCC
DQ3
NC
RESET#
VSS
DQ8
DQ9
DQS1
VCCQ
NC
VSS
96
CB6
Clock Input
Clock Input
5
CB3
BA1
97
VCCQ
CK0#
CKE0
CS0#
RAS#
CAS#
WE#
VCC
6
98
CB7
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Power Supply (2.5V)
Power Supply for DQS (2.5V)
Ground
Power Supply for Reference
Serial EEPROM Power Supply
(2.3V to 3.6V)
Serial data I/O
Serial clock
7
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
99
VSS
8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
DQ36
DQ37
VCC
DQS13
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
NC
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
NC
NC
VCCQ
DQ12
DQ13
DQS10
VCC
VCCQ
BA0
VSS
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
VREF
VCCSPD
NC
VSS
DQ14
DQ15
NC
VCCQ
NC
DQ20
A12
VSS
SDA
SCL
SA0-SA2
VCCID
NC
RESET#
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
Address in EEPROM
VCC Indentification Flag
No Connect
DQS5
DQ42
DQ43
VCC
DQS14
VSS
Reset Enable
DQ46
DQ47
NC
NC
DQ21
A11
DQ48
DQ49
VSS
VCCQ
DQS11
VCC
DQ22
A8
DQ52
DQ53
NC
NC
NC
VCC
VCCQ
DQS6
DQ50
DQ51
VSS
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
DQ23
VSS
DQS15
DQ54
DQ55
VCCQ
A6
DQ28
DQ29
VCCQ
DQS12
A3
DQ25
DQS3
A4
NC
DQ60
DQ61
VSS
VCC
DQ26
DQ27
A2
DQ30
VSS
DQS16
DQ62
DQ63
VCCQ
DQ31
CB4
CB5
VCCQ
CK0
CK0#
VSS
A1
CB0
CB1
VCC
SA0
NC
SDA
SCL
SA1
SA2
VCCSPD
April 2004
Rev. # 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
DQS9
-AJD3
PRELIMINARY
VSS
RS0A#
DQS0
DQS
I/O3
DM
CS#
DQS
DM
CS#
DQ0
DQ1
DQ2
I/O3
DQ4
DQ5
DQ6
DQ7
I/O2
I/O1
I/O0
I/O2
I/O1
I/O0
D0
D9
DQ3
DQS1
DQS10
DQS11
DQS12
DQS13
DQS14
DQS
CS#
DM
DQS
I/O3
I/O2
I/O1
I/O0
DM
CS#
D1
I/O3
I/O2
I/O1
DQ8
DQ9
DQ10
DQ12
DQ13
DQ14
DQ15
D10
I/O0
DQ11
DQS2
CS#
D11
CS#
D2
DQS
I/O3
I/O2
I/O1
I/O0
DM
DM
DQS
I/O3
I/O2
I/O1
I/O0
DM
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS4
DQS5
DQS6
CS#
DQS
I/O3
I/O2
I/O1
I/O0
CS#
D3
DQS
I/O3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O2
D12
I/O1
I/O0
CS#
D4
DQS
I/O3
I/O2
I/O1
DM
DQS
CS#
DM
DM
CK0
SDRAM
PLL
DQ32
DQ33
DQ34
DQ36
DQ37
DQ38
DQ39
I/O3
I/O2
D13
I/O1
I/O0
I/O0
DQ35
CK0#
REGISTER
DQS
I/O3
I/O2
I/O1
I/O0
CS#
DQS
I/O3
I/O2
I/O1
I/O0
DM
DM
CS#
D5
DQ44
DQ45
DQ46
DQ40
DQ41
DQ42
DQ43
D14
DQ47
DQS15
DQS16
DQS17
Serial PD
DQS
CS#
D6
DQS
I/O3
I/O2
I/O1
CS#
DM
DM
I/O3
I/O2
I/O1
I/O0
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
SCL
WP
D15
SDA
I/O0
A0
A1
A2
DQS7
DQS8
SA0 SA1
SA2
DQS
I/O3
I/O2
I/O1
I/O0
CS#
D7
DM
DM
DQS
I/O3
I/O2
CS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
D16
DQ62
DQ63
I/O1
I/O0
VCCSPD
SPD
VCC/VCCQ
D0 - D17
D0 - D17
DQS
I/O3
I/O2
I/O1
I/O0
CS#
D8
DQS
CS#
DM
DQ56
DQ57
DQ58
DQ59
I/O3
CB4
CB5
CB6
I/O2
D17
VREF
VSS
D0 - D17
D0 - D17
I/O1
I/O0
CB7
CS0#
RS0A#
RS0B#
R
E
G
I
S
T
E
R
Notes:
RBA0- RBA1
RA0- RA12
RRAS#
BA0-BA1: SDRAMs DQ0-D17
A0-A12: SDRAMs DQ0-D17
RAS#: SDRAMs DQ0-D17
CAS#: SDRAMs DQ0-D17
CKE: SDRAMs DQ0-D8
CKE: SDRAMs DQ9-D17
WE#: SDRAMs DQ0-D17
BA0-BA1
.
A0-A12
RAS#
CAS#
CKE0
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.
3. DQ, DQSresistors: 22 Ohms
RCAS
RCKE0A
RCKE0B
RWE#
WE#
PCK
PCK#
RESET#
April 2004
Rev. # 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
-0.5 - 3.6
-1.0 - 3.6
-55 - +150
27
Units
V
V
°C
W
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
Power Dissipation
PD
Short Circuit Current
I0S
50
mA
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C £ TA £ 70°C, VCC = 2.5V 0.2V
Parameter
Supply Voltage
Symbol
VCC
Min
2.3
Max
2.7
Unit
V
Supply Voltage
VCCQ
VREF
VTT
VIH
VIL
2.3
1.15
1.15
2.7
1.35
1.35
V
V
V
V
V
V
V
Reference Voltage
Termination Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
VREF + 0.15
-0.3
VTT + 0.76
—
VCCQ + 0.3
VREF - 0.15
—
VOH
VOL
VTT - 0.76
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 2.5V
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#, CAS#, WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0,CK0#)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM8)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)(DQS)
Data input/output capacitance (CB0-CB7)
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
COUT
COUT
Min
Max
6.5
6.5
6.5
5.5
6.5
8
6.5
8
8
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
—
—
—
—
—
—
—
—
—
April 2004
Rev. # 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C £ TA £ +70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V.
Includes DDR SDRAM components and PLL and Register
Rank 2
Standby
State
Rank 1
DDR333@CL=2.5 DDR266:@CL=2, 2.5 DDR200@CL=2 S
Parameter
Symbol Conditions
Max
Max
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
TBD
1715
1715
mA
IDD3N
t
RC = tRC (MIN); tCK = tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
Operating Current
IDD1
One device bank; Active-Read-
TBD
2255
2255
mA
IDD3N
Precharge Burst = 2; tRC = tRC (MIN);
t
CK = tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
Precharge Power-
IDD2P
IDD2F
All device banks idle; Power-down
mode; tCK = tCK (MIN); CKE = (low)
TBD
TBD
54
54
rnA
mA
IDD2P
IDD2F
Down Standby Current
Idle Standby Current
CS# = High; All device banks idle;
671
671
t
CK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
Active Power-Down
Standby Current
IDD3P
IDD3N
One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
TBD
TBD
540
540
mA
mA
IDD3P
IDD3N
Active Standby Current
CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS
(MAX); tCK = tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
1121
1121
Operating Current
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK (MIN); lOUT = 0mA.
TBD
TBD
2795
2795
2795
2795
mA
rnA
IDD3N
IDD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK = tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
IDD3N
Auto Refresh Current
Self Refresh Current
Operating Current
IDD5
IDD6
tRC = tRC (MIN)
TBD
TBD
TBD
3281
365
3281
365
mA
mA
mA
IDD3N
IDD6
CKE £ 0.2V
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
5315
5315
IDD3N
t
CK=tCK(MIN); Address and control
inputs change only during Active Read
or Write commands.
April 2004
Rev. # 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT: ONE BANK
IDD7A: OPERATING CURRENT: FOUR BANKS
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lOUT = 0mA
4. Timing patterns
3. Four banks are being interleaved with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
not changing.
lout = 0mA
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL =
4, tRCD = 2*tCK, tRAg = 5*tCK
4. Timing patterns
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL =
4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL
= 2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with
autoprecharge
Read: A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing; 50% of data
changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5,
BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL
= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR333 (166MHz, CL = 2.5) : tCK = 6ns, BL = 4,
tRCD = 10*tCK, tRAg = 7*tCK
Read: A0 N N R0 N P0 N N N A0 N — repeat the
same timing with random address changing; 50% of
data changing at every burst
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2,
BL = 4, tRRD = 2*tCK, tRCD = 3*tCK
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR333 (166MHz, CL = 2.5) : tCK = 6ns, BL = 4,
tRRD = 3*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
Legend: A = Activate, R = Read, W = Write, P =
Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
April 2004
Rev. # 2
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ TA ≤ +70°C; VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V
AC Characteristics
335
262/263/265
202
Parameter
Symbol
tAC
Min
-0.7
0.45
0.45
6
Max
+0.7
0.55
0.55
13
Min
Max
+0.75
0.55
0.55
13
Min
-0.8
0.45
0.45
8
Max
+0.8
0.55
0.55
13
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Access window of DQs from CK, CK#
CK high-level width
CK low-level width
-0.75
0.45
0.45
7.5
tCH
16
16
tCL
Clock cycle time
CL=2.5
CL=2
t
CK (2.5)
tCK (2)
tDH
22
7.5
13
7.5/10
0.5
13
10
13
22
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK, CK#
DQS input high pulse width
0.45
0.45
1.75
-0.60
0.35
0.35
0.6
0.6
2
14,17
14,17
17
tDS
0.5
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
tDSH
tHP
1.75
-0.75
0.35
0.35
+0.60
+0.75
-0.8
0.35
0.35
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
0.35
1.25
0.5
0.6
13,14
0.75
0.2
0.75
0.2
1.25
0.75
0.2
1.25
0.2
0.2
0.2
tCH, tCL
+0.70
tCH, tCL
+0.75
tCH, tCL
18
8,19
8,20
6
Data-out high-impedance window from CK, CK#
Data-out low-impedance window from CK, CK#
Address and control input hold time (fast slew rate)
Address and control input set-up time (fast slew rate)
Address and control input hold time (slow slew rate)
Address and control input setup time (slow slew rate)
Address and control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data hold skew factor
tHZ
+0.8
tLZ
-0.70
0.75
0.75
0.80
0.80
2.2
-0.75
0.90
0.90
1
-0.8
1.1
1.1
1.1
1.1
2.2
16
tIHf
tISf
6
tIHs
6
tISs
1
6
tIPW
2.2
15
tMRD
tQH
12
tHP-tQHS
0.50
120,000
tHP-tQHS
tHP-tQHS
13,14
15
tQHS
tRAS
tRAP
tRC
0.75
1
ACTIVE to PRECHARGE command
42
18
60
72
40
20
65
75
120,000
40
20
70
80
120,000
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
tRFC
21
April 2004
Rev. # 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
Notes 1-5, 7; notes appear following parameter tables; 0°C ≤ TA ≤ +70°C; VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V
AC Characteristics
335
262/263/265
202
Parameter
Symbol
tRCD
Min
18
Max
Min
Max
Min
20
Max
Units
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
μs
μs
ns
ns
tCK
Notes
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
20
20
0.9
0.4
15
0.25
0
tRP
18
20
tRPRE
tRPST
tRRD
0.9
0.4
12
1.1
0.6
1.1
0.6
0.9
0.4
15
1.1
0.6
19
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tWPRE
tWPRES
tWPST
tWR
0.25
0
0.25
0
DQS write preamble setup time
DQS write postamble
10,11
9
0.4
15
0.6
0.4
15
1
0.6
0.4
15
0.6
Write recovery time
Internal WRITE to READ command delay
Data valid output window
tWTR
1
1
NA
tQH-tDQSQ
tQH-tDQSQ
tQH-tDQSQ
13
12
12
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VCC
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
tREFC
tREFI
70.3
7.8
70.3
7.8
70.3
7.8
tVTD
0
0
0
tXSNR
tXSRD
75
75
80
200
200
200
April 2004
Rev. # 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
Notes
12. The refresh period is 64ms. This equates to an average refresh
rate of 15.625µs (256Mb component) or 7.8125µs (512 Mb
component). However, an AUTO REFRESH command must be
asserted at least once every 140.6µs (256 Mb component) or
70.3µs (512Mb component); burst refreshing or posting by the
DRAM controller greater than eight refresh cycles is not allowed.
1.
2.
All voltages referenced to VSS
Tests for AC timing, IDD, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specifications and device operations are guaranteed for
the full voltage range specified.
3.
Outputs are measured with equivalent load:
13. The valid data window is derived by achieving other specifications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window
derates directly proportional with the clock duty cycle and a
practical data valid window can be derived. The clock is allowed
a maximum duty cycled variation of 45/55. Functionality is
uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
VTT
50Ω
RReeffeerreennccee
Outputt
Point
30ppFF
(VOUT
)
14. Referenced to each output group: x4 = DQS with DQ0-DQ4.
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in
the test environment, but input timing is still referenced to VREF (or
to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
15. READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfied prior to the internal precharge
command being issued.
16. JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17. DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to tDS and tDH for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
5.
6.
The AC and DC input level specifications are defined in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
18.
t
HP min is the lesser of tCL min and tCH min actually applied to the
Command/Address input slew rate = 0.5V/ns. For -75 with slew
rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the
slew rate is less than 0.5V/ns, timing must be derated: tIS has an
additional 50ps per each 100mV/ns reduction in slew rate from the
500mV/ns. tIH has 0ps added, that is, it remains constant. If the
slew rate exceeds 4.5V/ns, functionality is uncertain.
device CK and CK# inputs, collectively during bank active.
19. This maximum value is derived from the referenced test load. In
practice, the values obtained in a typical terminated design may
reflect up to 310ps less for tHZ (MAX) and last DVW. tHZ (MAX) will
prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + PRE (MAX) condition.
7.
8.
Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE £ 0.3 x VCCQ is
recognized as LOW.
20. For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
tHZ and tLZ transitions occur in the same access time windows as
21. CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tREF later.
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
9.
The maximum limit for this parameter is not a device limit. The
device will operate with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
22. Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
10. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
11. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on tDQSS
.
April 2004
Rev. # 2
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
ORDERING INFORMATION FOR JD3
Part Number
Speed
CAS Latency
tRCD
3
tRP
3
Height*
W3EG7263S335JD3
W3EG7263S262JD3
W3EG7263S263JD3
W3EG7263S265JD3
W3EG7263S202JD3
166MHz/333Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
2.5
2
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
30.48 (1.20")
2
2
2
3
3
2.5
2
3
3
2
2
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
4.06
(0.160 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
3.99
(0.157)
(MIN)
30.48
(1.20 MAX)
17.78
(0.700)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27
10.01
(0.050 TYP.)
(0.394)
6.35
49.53
(0.250)
(1.950)
64.77
1.27 0.10
(2.550)
(0.050 0.004)
6.35
1.78
(0.070)
(0.250)
* All Dimensions are in millimeters and (inches).
April 2004
Rev. # 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
ORDERING INFORMATION FOR AJD3
Part Number
Speed
CAS Latency
tRCD
3
tRP
3
Height*
W3EG7263S335AJD3
W3EG7263S262AJD3
W3EG7263S263AJD3
W3EG7263S265AJD3
W3EG7263S202AJD3
166MHz/333Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
2.5
2
28.70 (1.13")
28.70 (1.13")
28.70 (1.13")
28.70 (1.13")
28.70 (1.13")
2
2
2
3
3
2.5
2
3
3
2
2
PACKAGE DIMENSIONS FOR AJD3
133.48
(5.255" MAX.)
131.34
(5.171")
4.06
(0.160 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
3.99
(0.157)
(MIN)
28.70
(1.13 MAX)
17.78
(0.700)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27
10.01
(0.050 TYP.)
(0.394)
6.35
49.53
(0.250)
(1.950)
64.77
1.27 0.10
(2.550)
(0.050 0.004)
6.35
1.78
(0.070)
(0.250)
* All Dimensions are in millimeters and (inches).
April 2004
Rev. # 2
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency
tRCD
3
tRP
3
Height*
W3EG7263S335D3
W3EG7263S262D3
W3EG7263S263D3
W3EG7263S265D3
W3EG7263S202D3
166MHz/333Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
133MHz/266Mb/s
100MHz/200Mb/s
2.5
2
28.58 (1.125")
28.58 (1.125")
28.58 (1.125")
28.58 (1.125")
28.58 (1.125")
2
2
2
3
3
2.5
2
3
3
2
2
PACKAGE DIMENSIONS FOR D3
NOT RECOMMENDED FOR NEW DESIGNS
133.48
(5.255" MAX.)
131.34
(5.171")
4.06
(0.160 MAX)
128.95
(5.077")
3.99
(0.157 (2x))
3.99
28.58
(0.157)
(MIN)
(1.125 MAX)
17.78
(0.700)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27
10.01
(0.050 TYP.)
(0.394)
6.35
49.53
(0.250)
(1.950)
64.77
1.27 0.10
(0.050 0.004)
(2.550)
6.35
1.78
(0.250)
(0.070)
* All Dimensions are in millimeters and (inches).
April 2004
Rev. # 2
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG7263S-D3
-JD3
White Electronic Designs
-AJD3
PRELIMINARY
Document Title
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLL
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Created Datasheet
3-5-02
Advanced
Advanced
Added 333MHz Speed
4-16-03
Rev 2
2.1 Added JD3 and AJD3 Package Height Options
2.2 Added "Not Recommended for New Designs" to D3
2.3 Updated Document Title Page
4-04
Preliminary
2.4 Removed "ED" from Part Marking
April 2004
Rev. # 2
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
W3EG7263S202AJD3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S202D3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S202JD3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S262AJD3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S262D3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S262JD3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S263AJD3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S263D3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S263JD3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S265AJD3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S265D3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
W3EG7263S265JD3
512MB- 64Mx72 DDR SDRAM REGISTERED w/PLLWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
©2020 ICPDF网 联系我们和版权申明