W3EG7266S265AD4 [WEDC]

512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL; 512MB - 64Mx72 DDR SDRAM非缓冲ECC W / PLL
W3EG7266S265AD4
型号: W3EG7266S265AD4
厂家: WHITE ELECTRONIC DESIGNS CORPORATION    WHITE ELECTRONIC DESIGNS CORPORATION
描述:

512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
512MB - 64Mx72 DDR SDRAM非缓冲ECC W / PLL

存储 内存集成电路 动态存储器 双倍数据速率
文件: 总13页 (文件大小:191K)
中文:  中文翻译
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W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY*  
512MB – 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL  
FEATURES  
DESCRIPTION  
Double-data-rate architecture  
The W3EG7266S is a 64Mx72 Double Data Rate  
SDRAM memory module based on 512Mb DDR SDRAM  
components. The module consists of nine 64Mx8 DDR  
SDRAMs in 66 pin TSOP packages mounted on a 200  
pin FR4 substrate.  
DDR200, DDR266, DDR300 and DDR400  
• JEDEC design specifications  
Bi-directional data strobes (DQS)  
Differential clock inputs (CK & CK#)  
Programmable Read Latency 2,2.5 (clock)  
Programmable Burst Length (2,4,8)  
Programmable Burst type (sequential & interleave)  
Edge aligned data output, center aligned data input  
Auto and self refresh  
Synchronous design allows precise cycle control with the  
use of system clock. Data I/O transactions are possible  
on both edges and Burst Lengths allow the same device to  
be useful for a variety of high bandwidth, high performance  
memory system applications.  
* This data sheet describes a product that is not fully qualified or characterized and is  
subject to change without notice.  
Serial presence detect  
Power supply:  
• VCC = VCCQ = +2.5V 0.2V (100, 133 and  
166MHz)  
• VCC = VCCQ = +2.6V 0.1V (200MHz)  
JEDEC standard 200 pin SO-DIMM package  
• Package height options:  
AD4: 35.05 mm (1.38”)  
BD4: 31.75 mm (1.25”)  
NOTE: Consult factory for availability of:  
• Lead-Free Products  
• Vendor source control options  
• Industrial temperature options  
OPERATING FREQUENCIES  
DDR400@CL=3  
DDR333@CL=2.5  
166MHz  
DDR266@CL=2  
133MHz  
DDR266@CL=2.5  
133MHz  
DDR200@CL=2  
100MHz  
Clock Speed  
CL-tRCD-tRP  
200MHz  
3-3-3  
2.5-3-3  
2-2-2  
2.5-3-3  
2-2-2  
October 2004  
Rev. 7  
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
PIN CONFIGURATION  
PIN NAMES  
A0 – A12  
BA0-BA1  
DQ0-DQ63  
CB0-CB7  
DQS0-DQS8  
CK0  
Address input (Multiplexed)  
Bank Select Address  
Data Input/Output  
Check bits  
Pin  
1
2
3
4
5
6
7
8
Symbol  
VREF  
VREF  
VSS  
Pin  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
81  
82  
83  
84  
85  
86  
87  
88  
89  
90  
91  
92  
93  
94  
95  
96  
97  
98  
99  
100  
Symbol  
VSS  
VSS  
DQ19  
DQ23  
DQ24  
DQ28  
VCC  
Pin  
101  
102  
103  
104  
105  
106  
107  
108  
109  
110  
111  
112  
113  
114  
115  
116  
117  
118  
119  
120  
121  
122  
123  
124  
125  
126  
127  
128  
129  
130  
131  
132  
133  
134  
135  
136  
137  
138  
139  
140  
141  
142  
143  
144  
145  
146  
147  
148  
149  
150  
Symbol  
A9  
AB  
VSS  
VSS  
A7  
A6  
A5  
A4  
A3  
A2  
AL  
AO  
VCC  
VCC  
A10/AP  
BA1  
RAO  
RAS#  
WE#  
CAS#  
CSO  
NC  
NC  
NC  
VSS  
VSS  
DQ32  
DQ36  
DQ33  
DQ37  
VCC  
Pin  
151  
152  
153  
154  
155  
156  
157  
158  
159  
160  
161  
162  
163  
164  
165  
166  
167  
168  
169  
170  
171  
172  
173  
174  
175  
176  
177  
178  
179  
180  
181  
182  
183  
184  
185  
186  
187  
188  
189  
190  
191  
192  
193  
194  
195  
196  
197  
198  
199  
200  
Symbol  
DQ42  
DQ46  
DQ43  
DQ47  
VCC  
VCC  
VCC  
NC  
VSS  
NC  
VSS  
VSS  
DQ48  
DQ52  
DQ49  
DQ53  
VCC  
Data Strobe Input/Output  
Clock Input  
VSS  
DQO  
DQ4  
DQ1  
DQ5  
VCC  
CK0#  
Clock input  
CKE0  
Clock Enable input  
Chip select Input  
Row Address Strobe  
Column Address Strobe  
Write Enable  
CS0#  
VCC  
RAS#  
9
DQ25  
DQ29  
DQS3  
DQM3  
VSS  
CAS#  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
VCC  
WE#  
DQSO  
DQMO  
DQ2  
DQ6  
VSS  
DQM0-DQM8 Data-In Mask  
VCC  
Power Supply  
VSS  
Ground  
VSS  
VREF  
VCCSPD  
SDA  
Power Supply for Reference  
Serial EEPROM Power Supply  
Serial data I/O  
DQ26  
DQ30  
DQ27  
DQ31  
VCC  
VSS  
DQ3  
DQ7  
DQ8  
DQ12  
VCC  
SCL  
Serial clock  
VCC  
SA0-SA2  
VCCID  
NC  
Address in EEPROM  
VCC Identification Flag  
No Connect  
DQS6  
DQM6  
DQ50  
DQ54  
VSS  
VCC  
CBO  
CB4  
CB1  
CB5  
VSS  
VCC  
DQ9  
DQ13  
DQS1  
DQM1  
VSS  
VSS  
DQ51  
DQ55  
DQ56  
DQ60  
VCC  
VSS  
DQS8  
DQM8  
CB2  
CB6  
VCC  
VSS  
DQ10  
DQ14  
DQ11  
DQ15  
VCC  
VCC  
CKO  
VCC  
VCC  
DQ57  
DQ61  
DQS7  
DQM7  
VSS  
VCC  
VCC  
CB3  
CB7  
NC  
NC  
VSS  
VSS  
NC  
VSS  
NC  
VCC  
VCC  
VCC  
NC  
CKEO  
NC  
NC  
A12  
A L L  
DQS4  
DQM4  
DQ34  
DQ38  
VSS  
VSS  
CKO#  
VSS  
VSS  
DQ58  
DQ62  
DQ59  
DQ63  
VCC  
VSS  
DQ35  
DQ39  
DQ40  
DQ44  
VCC  
VSS  
DQ16  
DQ20  
DQ17  
DQ21  
VCC  
VCC  
SDA  
SAO  
SCL  
SA1  
VCCSPD  
SA2  
VCC  
DQ41  
DQ45  
DQS5  
DQM5  
VSS  
VCC  
DQS2  
DQM2  
DQ18  
DQ22  
VCCID  
NC  
VSS  
October 2004  
Rev. 7  
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
FUNCTIONAL BLOCK DIAGRAM  
S0#  
DQS0  
DM0  
DQS4  
DM4  
DM CS# DQS  
DM CS# DQS  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ32  
DQ33  
DQ34  
DQ35  
DQ36  
DQ37  
DQ38  
DQ39  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQS1  
DM1  
DQS5  
DM5  
DM CS# DQS  
DM CS# DQS  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ8  
DQ40  
DQ41  
DQ42  
DQ43  
DQ44  
DQ45  
DQ46  
DQ47  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ9  
DQ10  
DQ11  
DQ12  
DQ13  
DQ14  
DQ15  
DQS2  
DM2  
DQS6  
DM6  
DM CS# DQS  
DM CS# DQS  
DQ16  
DQ17  
DQ18  
DQ19  
DQ20  
DQ21  
DQ22  
DQ23  
DQ48  
DQ49  
DQ50  
DQ51  
DQ52  
DQ53  
DQ54  
DQ55  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
120  
CK0  
CK0#  
DDR SDRAM  
DQS3  
DM3  
DQS7  
DM7  
120  
120  
CK1  
DM CS# DQ  
DM CS# DQ  
DDR SDRAM  
DDR SDRAM  
CK1#  
DQ24  
DQ25  
DQ26  
DQ27  
DQ28  
DQ29  
DQ30  
DQ31  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ56  
DQ57  
DQ58  
DQ59  
DQ60  
DQ61  
DQ62  
DQ63  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
CK2  
CK2#  
DQS8  
DM8  
SERIAL PD  
SCL  
WP  
SDA  
DM CS# DQS  
A0 A1 A2  
CB0  
CB1  
CB2  
CB3  
CB4  
CB5  
CB6  
CB7  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
DQ  
VCC  
SA0 SA1 SA2  
120  
CK0A  
FREQ_SEL  
CK0  
DDR  
SDRAM  
PLL  
CK0A#  
CK0#  
BA0, BA1  
A0-A12  
RAS#  
BA0, BA1: DDR SDRAMs  
A0-A12: DDR SDRAMs  
RAS#: DDR SDRAMs  
CAS#: DDR SDRAMs  
CKE0: DDR SDRAMs  
WE#: DDR SDRAMs  
V
CCSPD  
CC  
REF  
SS  
SPD/EEPROM  
V
DDR SDRAMS  
DDR SDRAMS  
DDR SDRAMS  
CAS#  
CKE0  
WE#  
V
V
NOTE: All resistor values are 22 ohms unless otherwise specified  
October 2004  
Rev. 7  
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Symbol  
Value  
– 0.5 ~ 3.6  
–1.0 ~ 3.6  
– 55 ~ +150  
9
Units  
V
Voltage on any pin relative to VSS  
Voltage on VCC supply relative to VSS  
Storage Temperature  
VIN, VOUT  
VCC, VCCQ  
TSTG  
V
°C  
W
Power Dissipation  
PD  
Short Circuit Current  
IOS  
50  
mA  
Note:  
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.  
Functional operation should be restricted to recommended operating condition.  
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.  
DC CHARACTERISTICS  
0°C TA 70°C, VCC = 2.5V 0.2V  
Parameter  
Symbol  
VCC  
Min  
Max  
2.7  
Unit  
V
Supply Voltage  
2.3  
2.3  
Supply Voltage  
VCCQ  
VREF  
VTT  
2.7  
V
Reference Voltage  
Termination Voltage  
Input High Voltage  
Input Low Voltage  
Output High Voltage  
Output Low Voltage  
1.15  
1.35  
V
1.15  
1.35  
V
VIH  
VREF + 0.15  
– 0.3  
VCCQ + 0.3  
VREF – 0.15  
V
VIL  
V
VOH  
VTT + 0.76  
V
VOL  
VTT – 0.76  
V
CAPACITANCE  
TA = 25°C, f = 1MHz, VCC = 2.5V 0.2V  
Parameter  
Symbol  
Max  
29  
29  
29  
5.5  
29  
8
Unit  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
pF  
Input Capacitance (A0-A12)  
CIN1  
CIN2  
CIN3  
CIN4  
CIN5  
CIN6  
CIN7  
COUT  
COUT  
Input Capacitance (RAS#,CAS#,WE#)  
Input Capacitance (CKE0,CKE1)  
Input Capacitance (CK0,CK0#)  
Input Capacitance (CS0#,CS1#)  
Input Capacitance (DQM0-DQM8)  
Input Capacitance (BA0-BA1)  
29  
8
Data input/output Capacitance (DQ0-DQ63)(DQS)  
Data input/output Capacitance (CB0-CB7)  
8
October 2004  
Rev. 7  
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
IDD SPECIFICATIONS AND TEST CONDITIONS  
0°C TA 70°C, VCC = VCCQ = 2.5V 0.2V (100, 133, 166MHz), VCC = VCCQ = +2.6V 0.1V (200MHz)  
DDR400@  
CL=3  
DDR333@  
CL=2.5  
DDR266@  
CL=2, 2.5  
DDR200@  
CL=2  
Parameter  
Symbol Conditions  
IDD0  
Max  
Max  
Max  
Max  
Units  
Operating Current  
One device bank; Active - Precharge;  
1670  
1445  
1445  
1445  
mA  
(MIN); DQ,DM and DQS inputs  
changing once per clock cycle;  
Address and control inputs changing  
once every two cycles. TRC=TRC(MIN);  
TCK=TCK  
Operating Current  
IDD1  
One device bank; Active-  
1940  
1715  
1715  
1715  
mA  
Read-Precharge; Burst = 2;  
TRC=TRC(MIN);TCK=TCK (MIN); Iout  
= 0mA; Address and control inputs  
changing once per clock cycle.  
Precharge Power-  
Down Standby  
Current  
IDD2P All device banks idle; Power-down  
mode; TCK=TCK(MIN); CKE=(low)  
45  
45  
45  
45  
mA  
mA  
Idle Standby Current  
IDD2F CS# = High; All device banks idle;  
TCK=TCK(MIN); CKE = high; Address  
and other control inputs changing once  
per clock cycle. VIN = VREF for DQ,  
DQS and DM.  
770  
680  
680  
680  
Active Power-Down  
Standby Current  
IDD3P One device bank active; Power-down  
mode; TCK(MIN); CKE=(low)  
405  
815  
315  
725  
315  
725  
315  
725  
mA  
mA  
Active Standby  
Current  
IDD3N CS# = High; CKE = High; One  
device bank; Active-Precharge;  
TRC=TRAS(MAX); TCK=TCK(MIN); DQ,  
DM and DQS inputs changing twice  
per clock cycle; Address and other  
control inputs changing once per clock  
cycle.  
Operating Current  
Operating Current  
IDD4R Burst = 2; Reads; Continous burst;  
One device bank active;Address  
andcontrol inputs changing once  
per clock cycle; TCK=TCK(MIN); IOUT  
= 0mA.  
1985  
2030  
1760  
1850  
1760  
1670  
1760  
1670  
mA  
mA  
IDD4W Burst = 2; Writes; Continous burst;  
One device bank active; Address and  
control inputs changing once per clock  
cycle; TCK=TCK(MIN); DQ,DM and  
DQS inputs changing twice per clock  
cycle.  
Auto Refresh Current  
Self Refresh Current  
Operating Current  
IDD5  
IDD6  
TRC=TRC(MIN)  
CKE ≤ 0.2V  
3360  
320  
2885  
320  
2885  
320  
2885  
320  
mA  
mA  
mA  
IDD7A Four bank interleaving Reads (BL=4)  
with auto precharge with TRC=TRC  
(MIN); TCK=TCK(MIN); Address and  
control inputs change only during  
Active Read or Write commands  
4325  
3875  
3875  
3875  
October 2004  
Rev. 7  
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A  
IDD1 : OPERATING CURRENT : ONE BANK  
IDD7A : OPERATING CURRENT : FOUR BANKS  
1. Typical Case : VCC=2.5V, T=25°C  
2. Worst Case : VCC=2.7V, T=10°C  
1. Typical Case : VCC=2.5V, T=25°C  
2. Worst Case : VCC=2.7V, T=10°C  
3. Only one bank is accessed with tRC (min), Burst  
Mode, Address and Control inputs on NOP edge  
are changing once per clock cycle. IOUT = 0mA  
3. Four banks are being interleaved with tRC (min),  
Burst Mode, Address and Control inputs on NOP  
edge are not changing. Iout=0mA  
4. Timing Patterns :  
4. Timing Patterns :  
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,  
BL=4, tRCD=2*tCK, tRAS=5*tCK  
Read : A0 N R0 N N P0 N A0 N - repeat the  
same timing with random address changing;  
50% of data changing at every burst  
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,  
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with  
Autoprecharge  
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0  
- repeat the same timing with random address  
changing; 100% of data changing at every  
burst  
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,  
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK  
Read : A0 N N R0 N P0 N N N A0 N - repeat  
the same timing with random address  
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,  
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK  
Read with Autoprecharge  
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N  
A1 R0 - repeat the same timing with random  
address changing; 100% of data changing at  
every burst  
changing; 50% of data changing at every burst  
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,  
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK  
Read : A0 N N R0 N P0 N N N A0 N - repeat  
the same timing with random address  
changing; 50% of data changing at every burst  
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,  
BL=4, tRRD=2*tCK, tRCD=2*tCK  
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N  
A1 R0 - repeat the same timing with random  
address changing; 100% of data changing at  
every burst  
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,  
tRCD=10*tCK, tRAS=7*tCK  
Read : A0 N N R0 N P0 N N N A0 N - repeat  
the same timing with random address  
changing; 50% of data changing at every burst  
DDR333 (166MHz, CL=2.5) : tCK=6ns,  
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with  
Autoprecharge  
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N  
A1 R0 - repeat the same timing with random  
address changing; 100% of data changing at  
every burst  
DDR400 (200MHz, CL=3) : tCK=5ns, BL=4,  
tRCD=15*tCK, tRAS=7*tCK  
Read : A0 N N R0 N P0 N N N A0 N - repeat  
the same timing with random address  
changing; 50% of data changing at every burst  
DDR400 (200MHz, CL=3) : tCK=5ns,  
BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with  
Autoprecharge  
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N  
A1 R0 - repeat the same timing with random  
address changing; 100% of data changing at  
every burst  
Legend : A = Activate, R = Read, W = Write, P = Precharge,  
N = NOP  
A (0-3) = Activate Bank 0-3  
R (0-3) = Read Bank 0-3  
October 2004  
Rev. 7  
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED  
AC OPERATING CONDITIONS  
DDR400: VCC = VCCQ = +2.6V 0.1V  
AC CHARACTERISTICS  
403  
335  
262  
265  
202  
PARAMETER  
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES  
Access window of DQs from CK/CK#  
CK high-level width  
CK low-level width  
tAC  
tCH  
tCL  
-0.7 +0.7 -0.7 +0.7 -0.75 +0.75 -0.75 0.75 -0.8  
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55  
0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55  
0.8  
ns  
tCK  
tCK  
25  
25  
Clock cycle time  
CL = 3  
CL = 2.5  
CL = 2  
tCK (3)  
tCK (2.5)  
tCK (2)  
tDH  
5
6
7.5  
0.4  
0.4  
1.75  
7.5  
13  
13  
6
7.5  
13  
13  
7.5  
7.5  
13  
7.5  
13  
8
10  
13  
13  
ns 38, 43  
ns 38, 43  
ns 37, 42  
ns 22, 26  
ns 22, 26  
13 7.5/10 13  
DQ and DM input hold time relative to DQS  
DQ and DM input setup time relative to DQS  
DQ and DM input pulse width (for each input)  
Access window of DQS from CK/CK#  
DQS input high pulse width  
0.45  
0.45  
1.75  
0.5  
0.5  
1.75  
0.6  
0.6  
2
tDS  
tDIPW  
tDQSCK  
tDQSH  
tDQSL  
tDQSQ  
ns  
ns  
tCK  
tCK  
ns  
26  
-0.6 +0.6 -0.60 +0.60 -0.75 +0.75 +0.75 -0.8 +0.8  
0.35  
0.35  
0.35  
0.35  
0.35  
0.35  
0.35  
0.35  
0.5  
DQS input low pulse width  
DQS-DQ skew, DQS to last DQ valid, per group, per  
0.40  
0.45  
0.5  
0.6  
22  
access  
Write command to first DQS latching transition  
DQS falling edge to CK rising - setup time  
DQS falling edge from CK rising - hold time  
Half clock period  
tDQSS  
tDSS  
tDSH  
tHP  
0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25  
tCK  
tCK  
tCK  
ns  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
0.2  
tCH,tCL  
tCH,tCL  
tCH,tCL  
tCH,tCL  
tCH,tCL  
29  
Data-out high-impedance window from CK/CK#  
Data-out low-impedance window from CK/CK#  
Address and control input hold time (1 V/ns)  
Address and control input setup time (1 V/ns)  
Address and control input hold time (0.5 V/ns)  
Address and control input setup time (0.5 V/ns)  
Address and Control input pulse width (for each input)  
LOAD MODE REGISTER command cycle time  
tHZ  
tLZ  
tIHF  
tISF  
tIHS  
tISS  
tIPW  
tMRD  
tQH  
+0.70  
+0.70  
+0.75  
+0.75  
+0.8  
ns 16, 35  
ns 16, 35  
-0.70  
0.6  
0.6  
0.6  
0.6  
2.20  
2
-0.70  
0.75  
0.75  
0.80  
0.80  
2.2  
-0.75  
0.90  
0.90  
1
1
2.2  
15  
-0.75  
-0.8  
ns  
0.90 1.1  
12  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
12  
12  
12  
12  
0.90  
1
1
2.2  
15  
1.1  
1.1  
1.1  
2.2  
16  
12  
DQ-DQS hold, DQS to first DQ to go non-valid, per  
tHP  
tHP  
tHP  
tHP  
tHP  
22  
30  
access  
- tQHS  
- tQHS  
- tQHS  
- tQHS  
- tQHS  
Data hold skew factor  
ACTIVE to PRECHARGE command  
ACTIVE to READ with Auto precharge command  
tQHS  
tRAS  
tRAP  
tRC  
0.50  
0.60  
0.75  
0.75  
1
ns  
40 70,000 42 70,000 40 120,000 40 120,000 40 120,000 ns  
15  
55  
15  
60  
15  
60  
20  
65  
20  
70  
ns  
ns  
ACTIVE to ACTIVE/AUTO REFRESH command  
period  
AUTO REFRESH command period  
ACTIVE to READ or WRITE delay  
PRECHARGE command period  
DQS read preamble  
DQS read postamble  
ACTIVE bank a to ACTIVE bank b command  
DQS write preamble  
tRFC  
tRCD  
tRP  
tRPRE  
tRPST  
tRRD  
tWPRE  
tWPRES  
70  
15  
15  
0.9  
0.4  
10  
0.25  
0
72  
15  
15  
0.9  
0.4  
12  
0.25  
0
75  
15  
15  
0.9  
0.4  
15  
0.25  
0
72  
20  
20  
0.9  
0.4  
15  
0.25  
0
75  
20  
20  
0.9  
0.4  
15  
0.25  
0
ns  
ns  
ns  
tCK  
tCK  
ns  
tCK  
41  
1.1  
0.6  
1.1  
0.6  
1.1  
0.6  
1.1  
0.6  
1.1  
0.6  
36  
36  
DQS write preamble setup time  
ns 17, 19  
October 2004  
Rev. 7  
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED  
AC OPERATING CONDITIONS (Continued)  
DDR400: VCC = VCCQ = +2.6V 0.1V  
AC CHARACTERISTICS  
403  
355  
262  
265  
202  
PARAMETER  
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES  
DQS write postamble  
Write recovery time  
tWPST  
tWR  
0.4  
15  
0.6  
0.4  
15  
0.6  
0.4  
15  
0.6  
0.4  
15  
0.6  
0.4  
15  
0.6  
tCK  
ns  
17  
Internal WRITE to READ command delay  
tWTR  
2
1
1
1
1
tCK  
Data valid output window  
REFRESH to REFRESH command interval  
Average periodic refresh interval  
Terminating voltage delay to VCC  
Exit SELF REFRESH to non-READ command  
Exit SELF REFRESH to READ command  
na  
tQH - tDQSQ  
tQH - tDQSQ  
tQH - tDQSQ  
ns  
µs  
µs  
ns  
ns  
tCK  
22  
21  
21  
tQH - tDQSQ  
tQH - tDQSQ  
tREFC  
tREFI  
tVTD  
tXSNR  
tXSRD  
70.3  
7.8  
70.3  
7.8  
70.3  
7.8  
70.3  
7.8  
70.3  
7.8  
0
75  
200  
0
75  
200  
0
75  
200  
0
75  
200  
0
80  
200  
October 2004  
Rev. 7  
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
Notes  
1. All voltages referenced to VSS  
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be  
conducted at nominal reference/supply voltage levels, but the related specifications  
and device operation are guaranteed for the full voltage range specified.  
3. Outputs measured with equivalent load:  
.
17. The intent of the Don’t Care state after completion of the postamble is the DQS-  
driven signal should either be high, low, or high-Z and that any signal transition  
within the input switching region must follow valid input requirements. That is, if  
DQS transitions high [above VIHDC (MIN)] then it must not transition low (below  
VIHDC) prior to tDQSH (MIN).  
18. This is not a device limit. The device will operate with a negative value, but system  
performance could be degraded due to bus turnaround.  
V
TT  
19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE  
command. The case shown (DQS going from High-Z to logic LOW) applies when  
no WRITEs were previously in progress on the bus. If a previous WRITE was in  
50Ω  
RReeffeerreennccee  
Output  
Point  
30pF  
progress, DQS could be HIGH during this time, depending on tDQSS  
.
(VOUT  
)
20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets  
the minimum absolute value for the respective parameter. tRAS (MAX) for IDD  
measurements is the largest multiple of tCK that meets the maximum absolute value  
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test  
environment, but input timing is still referenced to VREF (or to the crossing point for  
CK/CK#), and parameter specifications are guaranteed for the specified AC input  
levels under normal use conditions. The mini-mum slew rate for the input signals  
used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).  
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard  
(i.e., the receiver will effectively switch as a result of the signal crossing the AC  
input level, and will remain in that state as long as the signal does not ring back  
above [below] the DC input LOW [HIGH] level).  
for tRAS  
.
21. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs.  
However, an AUTO REFRESH command must be as-serted at least once every  
70.3µs; burst refreshing or posting by the DRAM controller greater than eight  
refresh cycles is not allowed.  
22. The data valid window is derived by achieving other specifications: tHP (tCK/2), tDQSQ  
and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with  
the clock duty cycle and a practical data valid window can be derived. The clock  
is allowed a maximum duty cycle variation of 45/55, beyond which functionality is  
uncertain.  
23. Each byte lane has a corresponding DQS.  
24. This limit is actually a nominal value and does not result in a fail value. CKE is  
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during  
standby).  
25. To maintain a valid level, the transitioning edge of the input must:  
a. Sustain a constant slew rate from the current AC level through to the target AC  
level, VIL(AC) or VIH(AC).  
,
6.  
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations  
in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may  
not exceed 2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed 25mV  
for DC error and an additional 25mV for AC noise. This measurement is to be  
taken at the nearest VREF bypass capacitor.  
7.  
8.  
V
TT is not applied directly to the device. VTT is a system supply for signal  
termination resistors, is expected to be set equal to VREF and must track variations  
in the DC level of VREF  
DD is dependent on output loading and cycle rates. Specified values are obtained  
with mini-mum cycle time at CL = 2 for 262 and 202, CL = 2.5 for 265, 335 and  
CL = 3 for 403 with the outputs open.  
.
I
b. Reach at least the target AC level.  
c. After the AC target level is reached, continue to maintain at least the target DC  
level, VIL(DC) or VIH(DC).  
9. Enables on-chip refresh and address counters.  
10. DD specifications are tested after the device is properly initialized, and is averaged  
at the defined cycle rate.  
11. This parameter is sampled. VCC = +2.5V 0.2V, VCCQ = +2.5V 0.2V, VREF = VSS, f  
= 100 MHz, TA = 25°C, VOUT (DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM input is  
grouped with I/O pins, reflecting the fact that they are matched in loading.  
12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing  
must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew  
rate from 500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns,  
functionality is uncertain. For 335, slew rates must be 0.5 V/ns.  
26. JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns  
differentially).  
I
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.  
If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps  
must be added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate  
exceeds 4 V/ns, functionality is uncertain. For 403, slew rates must be ≥ 0.5 V/ns.  
28.  
VCC must not vary more than 4 percent if CKE is not active while any bank is active.  
29. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary  
by the same amount.  
30.  
t
HP min is the lesser of tCL minimum and tCH minimum actually applied to the device  
CK and CK/ inputs, collectively during bank active.  
31. READs and WRITEs with auto precharge are not allowed to be issued until  
RAS(MIN) can be satisfied prior to the internal precharge command being issued.  
13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at  
which CK and CK# cross; the input reference level for signals other than CK/CK# is  
VREF  
.
t
14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period  
before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW.  
15. The output timing reference level, as measured at the timing reference point  
32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and  
not more than +400mV or 2.9V maximum, whichever is less. Any negative glitch  
must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V  
mini-mum, whichever is more positive.  
indicated in Note 3, is VTT  
.
16. tHZ and tLZ transitions occur in the same access time windows as data valid  
transitions. These parameters are not referenced to a specific voltage level, but  
specify when the device output is no longer driving (HZ) or begins driving (LZ).  
October 2004  
Rev. 7  
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
33. The voltage levels used are derived from a mini-mum VCC level and the referenced  
test load. In practice, the voltage levels obtained from a properly terminated bus will  
provide significantly different voltage values.  
40. Random addressing changing and 50 percent of data changing at every transfer.  
41. Random addressing changing and 100 percent of data changing at every transfer.  
42. CKE must be active (high) during the entire time a refresh command is executed.  
That is, from the time the AUTO REFRESH command is registered, CKE must be  
active at each rising clock edge, until tREF later.  
34.  
VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width < 3ns and the pulse width  
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a  
pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.  
43.  
I
I
DD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level.  
DD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to  
35.  
36.  
V
CC and VCCQ must track each other.  
HZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will  
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.  
RPST end point and tRPRE begin point are not referenced to a specific voltage level  
t
remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”  
44. Whenever the operating frequency is altered, not including jitter, the DLL is required  
to be reset. This is followed by 200 clock cycles (before READ commands).  
45. Leakage number reflects the worst case leakage possible through the module pin,  
not what each memory device contributes.  
37.  
t
but specify when the device output is no longer driving (tRPST), or begins driving  
(tRPRE).  
38. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.  
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ  
are 0V, provided a minimum of 42 0 of series resistance is used between the VTT  
supply and the input pin.  
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or  
LOW.  
47. The 403 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) =  
120,000ns at any slower frequency.  
39. The current part operates below the slowest JEDEC operating frequency of 83  
MHz. As such, future die may not reflect this option.  
October 2004  
Rev. 7  
10  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
ORDERING INFORMATION FOR BD4  
Part Number  
Speed  
Height*  
Commercial Operating Range  
0°C to 70°C  
W3EG7266S403BD4  
W3EG7266S335BD4  
W3EG7266S262BD4  
W3EG7266S265BD4  
W3EG7266S202BD4  
200MHz/400Mbps, CL=3  
166MHz/333Mbps, CL=2.5  
133MHz/266Mbps, CL=2  
133MHz/266Mbps, CL=2.5  
100MHz/200Mbps, CL=2  
31.75 (1.25")  
31.75 (1.25")  
31.75 (1.25")  
31.75 (1.25")  
31.75 (1.25")  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
INDUSTRIAL  
Part Number  
Speed  
Height*  
Industrial Operating Range  
-40°C to 85°C  
W3EG7266S403BD4I  
W3EG7266S335BD4I  
W3EG7266S262BD4I  
W3EG7266S265BD4I  
W3EG7266S202BD4I  
NOTES:  
200MHz/400Mbps, CL=3  
166MHz/333Mbps, CL=2.5  
133MHz/266Mbps, CL=2  
133MHz/266Mbps, CL=2.5  
100MHz/200Mbps, CL=2  
31.75 (1.25")  
31.75 (1.25")  
31.75 (1.25")  
31.75 (1.25")  
31.75 (1.25")  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
• Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)  
• Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.  
• Consult factory for availability of industrial temperature (-40°C to 85°C) option  
PACKAGE DIMENSIONS FOR BD4  
3.81  
(0.150) MAX.  
67.56  
(2.666) MAX  
3.98 0.1  
(0.157 0.004)  
31.75  
(1.25)  
20  
(0.787)  
2.31  
(0.091) REF.  
3.98  
(0.157) MIN.  
4.19  
(0.165)  
47.40  
(1.866)  
1.0 0.1  
(0.039 0.004)  
1.80  
(0.071)  
11.40  
(0.449)  
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)  
October 2004  
Rev. 7  
11  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
ORDERING INFORMATION FOR AD4  
Part Number  
Speed  
Height*  
Commercial Operating Range  
0°C to 70°C  
W3EG7266S403AD4  
W3EG7266S335AD4  
W3EG7266S262AD4  
W3EG7266S265AD4  
W3EG7266S202AD4  
200MHz/400Mbps, CL=3  
166MHz/333Mbps, CL=2.5  
133MHz/266Mbps, CL=2  
133MHz/266Mbps, CL=2.5  
100MHz/200Mbps, CL=2  
35.05 (1.38") MAX  
35.05 (1.38") MAX  
35.05 (1.38") MAX  
35.05 (1.38") MAX  
35.05 (1.38") MAX  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
0°C to 70°C  
INDUSTRIAL  
Part Number  
Speed  
Height*  
Industrial Operating Range  
-40°C to 85°C  
W3EG7266S403AD4I  
W3EG7266S335AD4I  
W3EG7266S262AD4I  
W3EG7266S265AD4I  
W3EG7266S202AD4I  
NOTES:  
200MHz/400Mbps, CL=3  
166MHz/333Mbps, CL=2.5  
133MHz/266Mbps, CL=2  
133MHz/266Mbps, CL=2.5  
100MHz/200Mbps, CL=2  
35.05 (1.38") MAX  
35.05 (1.38") MAX  
35.05 (1.38") MAX  
35.05 (1.38") MAX  
35.05 (1.38") MAX  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
• Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant)  
• Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.  
• Consult factory for availability of industrial temperature (-40°C to 85°C) option  
PACKAGE DIMENSIONS FOR AD4  
67.56  
(2.664 MAX.  
3.81  
(0 .1504 MAX.  
2.0  
(0.0794  
3.98 0.1  
(0.157 0.00ꢀ4  
35.05  
(1.384 MAX.  
20  
(0.7874  
P1  
2.31  
(0.0914 REF.  
3.98  
(0.1574 MIN.  
ꢀ.19  
(0.1654  
ꢀ7.ꢀ0  
(1.8664  
1.80  
(0.0714  
1.0 0.1  
(0.039 0.00ꢀ4  
11.ꢀ0  
(0.ꢀꢀ94  
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)  
October 2004  
Rev. 7  
12  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  
W3EG7266S-AD4  
-BD4  
White Electronic Designs  
PRELIMINARY  
Document Title  
512MB – 64Mx72, DDR, SDRAM Unbuffered ECC, w/PLL  
Revision History  
Rev #  
History  
Release Date Status  
Rev 0  
Initial Release  
1-31-02  
Advanced  
Rev 1  
1.1 Page 1 add “PLL”  
10-10-02  
Advanced  
1.2 Page 5 add new table  
Rev 2  
Rev 3  
Rev 4  
1.1 Add 333MHz  
3-5-03  
2-27-04  
5-04  
Advanced  
Preliminary  
Preliminary  
1.1 Added “BD4” package option/correction  
1.1 BD4 module dimensions corrected  
1.2 AD4 module dimensions corrected  
1.3 Removed “ED” from part number  
Rev 5  
Rev 6  
Rev 7  
1.0 Added Industrial Temp Spec  
1.0 Added 400MHz  
7-04  
9-04  
10-4  
Preliminary  
Preliminary  
Preliminary  
1.0 Added 400 MHz IDD Specs  
October 2004  
Rev. 7  
13  
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com  

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MICROSEMI

W3EG7266S265AD4I

512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
WEDC

W3EG7266S265AD4IF

DDR DRAM Module, 64MX72, 0.75ns, CMOS, LEAD FREE, SO-DIMM-200
WEDC

W3EG7266S265AD4IG

暂无描述
WEDC

W3EG7266S265BD4

512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
WEDC

W3EG7266S265BD4F

DDR DRAM Module, 64MX72, 0.75ns, CMOS, LEAD FREE, SO-DIMM-200
WEDC

W3EG7266S265BD4G

DDR DRAM Module, 64MX72, 0.75ns, CMOS, ROHS COMPLIANT, SO-DIMM-200
WEDC

W3EG7266S265BD4I

512MB - 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL
WEDC

W3EG7266S265BD4IF

DDR DRAM Module, 64MX72, 0.75ns, CMOS, LEAD FREE, SO-DIMM-200
WEDC