W3H64M72E-533ESI [WEDC]
64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package; 64M X 72 DDR2 SDRAM 208 PBGA多芯片封装
| 型号： | W3H64M72E-533ESI |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| 文件： | 总30页 (文件大小：942K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
FEATURES
ꢀ
Data rate = 667*, 533, 400
Package:
ꢀ
ꢀ
ꢀ
ꢀ
Programmable CAS latency: 3, 4 or 5
Posted CAS additive latency: 0, 1, 2, 3 or 4
Write latency = Read latency - 1* tCK
ꢀ
• 208 Plastic Ball Grid Array (PBGA), 17 x 23mm
• 1.0mm pitch
Commercial, Industrial and Military ꢀemperature
Ranges
ꢀ
ꢀ
ꢀ
DDR2 Data Rate = 667*, 533, 400
Core Supply Voltage = 1.8V 0.1V
ꢀ
ꢀ
Organized as 64M x 72
Weight: W3H64M72E-XSBX - 2.5 grams typical
I/O Supply Voltage = 1.8V 0.1V - (SSꢀTL18
compatible)
BENEFITS
ꢀ
ꢀ
ꢀ
ꢀ
Differential data strobe (DQS, DQS#) per byte
Internal, pipelined, double data rate architecture
4-bit prefetch architecture
ꢀ
ꢀ
ꢀ
ꢀ
63% SPACE SAVINGS vs. FPBGA
Reduced part count
55% I/O reduction vs FPBGA
DTT for alignment of DQ and DQS transitions with
clock signal
Reduced trace lengths for lower parasitic
capacitance
ꢀ
Eight internal banks for concurrent operation
(Per DDR2 SDRAM Die)
ꢀ
ꢀ
Suitable for hi-reliability applications
Upgradable to 128M x 72 density (contact factory
for information)
ꢀ
ꢀ
ꢀ
ꢀ
Programmable Burst lengths: 4 or 8
Auto Refresh and Self Refresh Modes
On Die ꢀermination (ODꢀ)
* ꢀhis product is under development, is not qualified or characterized and is subject
to change or cancellation without notice.
Adjustable data – output drive strength
FIGURE 1 – DENSITY COMPARISONS
Actual Size
S
A
V
I
N
G
S
CSP Approach (mm)
W3H64M72E-XSBX
11.0
11.0
11.0
11.0
11.0
23
White Electronic Designs
W3H64M72E-XSBX
90
FBGA
90
FBGA
90
FBGA
90
FBGA
90
FBGA
19.0
17
Area
5 x 209mm2 = 1,045mm2
5 x 92 balls = 460 balls
391mm2
63%
55%
I/O
208 Balls
Count
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
CS#
WE#
RAS#
CAS#
CKE
CS# WE# RAS# CAS# CKE
ODꢀ
A0-12
BA0-2
ODꢀ
A0-12
BA0-2
DQ0
DQ0
CK0
CK0#
CK
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
¥
CK#
TDM0
TDM
U0
UDM0
UDM
TDQS0
TDQS0#
UDQS0
UDQS0#
TDQS
TDQS#
UDQS
UDQS#
¥
DQ15
DQ15
CS# WE# RAS# CAS# CKE
ODꢀ
A0-12
BA0-2
CK
DQ0
¥
¥
¥
DQ16
¥
¥
¥
CK1
CK1#
CK#
TDM1
TDM
U1
¥
¥
¥
¥
¥
¥
UDM1
UDM
TDQS1
TDQS1#
UDQS1
UDQS1#
TDQS
TDQS#
UDQS
UDQS#
DQ15
DQ31
CS# WE# RAS# CAS# CKE
ODꢀ
A0-12
DQ0
¥
¥
¥
¥
¥
DQ32
¥
¥
¥
¥
¥
BA0-2
CK2
CK2#
CK
CK#
U2
TDM2
TDM
UDM2
UDM
TDQS2
TDQS2#
UDQS2
UDQS2#
TDQS
TDQS#
UDQS
UDQS#
¥
¥
DQ15
DQ47
CS# WE# RAS# CAS# CKE
ODꢀ
A0-12
DQ0
¥
¥
¥
¥
¥
DQ48
¥
¥
¥
¥
¥
BA0-2
CK3
CK3#
CK
CK#
TDM3
TDM
U3
UDM3
UDM
TDQS3
TDQS3#
UDQS3
UDQS3#
TDQS
TDQS#
UDQS
UDQS#
¥
¥
DQ15
DQ63
CS# WE# RAS# CAS# CKE
ODꢀ
A0-12
DQ0
¥
¥
¥
¥
¥
DQ64
¥
¥
¥
¥
¥
BA0-2
CK4
CK4#
CK
CK#
TDM4
TDM
U4
VCC
UDM
TDQS4
TDQS4#
UDQS4
UDQS4#
TDQS
TDQS#
UDQS
UDQS#
¥
¥
DQ15
DQ71
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
2
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W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
FIGURE 3 - PIN CONFIGURATION
TOP VIEW
1
2
3
4
5
6
7
8
9 10 11
VCC
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VCC
VSS
A
B
C
D
E
F
VCC
VSS
NC
NC
NC
NC
NC
NC
NC
VSS
VCC
VSS
DQ35
DQ52
LDM3
DQ38
UMD3
VCC
NC
NC
NC
NC
NC
NC
DQ34
DQ53
CK3
DQ37
CK3#
CK2#
VSS
DQ51
DQ36
LDM2
DQ54
DQ44
A6
NC
NC
NC
NC
DQ50
CK2
DQ32
DQ33
DQ49
DQ60
DQ41
A10
NC
BA2
DQ59
DNU
DNU
VSS
VCC
VSS
VREF
VSS
VCC
VSS
ODT
DQ39 LDQS2 LDQS3 DQ48
DQ43
DQ55
DQ63
DQ58
DQ56
DQ42 LDQS2# LDQS3#
DQ57 UMD2
DQ40
DQ61
DQ45
G
H
J
DQ46
A9
DQ62
VCC
UDQS2# DQ47 UDQS2 UDQS3 UDQS3#
VCC
VSS
A3
A12
A1
DNU*
BA1
VCC
VSS
VSS
A0
A11
VCC
VSS
VCC
K
T
VCC
A2
A4
A8
VCC
VCC
BA0
A5
A7
VCC
UDQS1# UDQS1
UDQS0
DQ8
DQ10
DQ15
DQ24
DQ26
UDQS0#
DQ31
DQ23
DQ7
DQ18
RAS#
CS#
DQ30
UDM0
DQ27
DQ14
DQ25
DQ11
DQ9
DQ28
DQ17
DQ1
DQ12
DQ22
LDM0
DQ4
DQ19
DQ68
VSS
UMD1
DQ6
LDM1
DQ20
DQ3
M
N
P
R
ꢀ
DQ13
DQ29
LDQS1# LDQS0#
DQ0
CK0
VSS
DQ16 LDQS1 LDQS0
LDQS4# UDQS4 UDQS4#
CK0#
CK1#
VSS
DQ5
CK1
CK4#
VSS
DQ21
DQ2
CK4
VCC
LDQS4
CAS#
DQ66
VSS
DQ71
DQ64
DQ69
Vcc
CKE
DQ70
LDM4
VCC
WE#
DQ65
DQ67
VSS
VSS
U
V
W
VCC
VSS
VCC
VCC
VCC
VCC
VSS
* Pin J10 is reserved for signal A13 on 128Mx72 and higher densities.
Note: UDQS4 and UDQS4# require a 10KΩ pull up resistor.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
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ADVANCED*
TABLE 1 – BALL DESCRIPTIONS
Symbol
Type
Description
On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When
enabled, ODT is only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and
UDQS#. The ODT input will be ignored if disabled via the LOAD MODE command.
ODT
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing
of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the
crossings of CK and CK#.
CK, CK#
Input
Input
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the
DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration
and operating mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks
idle), or ACTIVE power-down (row active in any bank). CKE is synchronous for power-down entry, Power-down
exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding
CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh.
CKE is an SSTL_18 input but will detect a LVCMO SLOW level once VCC is applied during first power-up. After
VREF has become stable during the power on and initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper SELF-REFRESH operation, VREF must be maintained.
CKE
CS#
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands
are masked when CS# is registered HIGH.
Input
Input
RAS#, CAS#,
WE#
Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered.
Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled
HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM
loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for
upper byte DQ8–DQ15, of each of U0-U4
LDM, UDM
BA0–BA2
Input
Input
Bank address inputs: BA0–BA2 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is
being applied. BA0–BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the
LOAD MODE command.
Continued on next page
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
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W3H64M72E-XSBX
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ADVANCED*
TABLE – 1 BALL DESCRIPTIONS (continued)
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA2–BA0) or all banks (A10 HIGH) The address inputs also provide the op-code during a LOAD
MODE command.
A0-A12
Input
DQ0-71
I/O
I/O
Data input/output: Bidirectional data bus
Data strobe for upper byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. UDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
UDQS, UDQS#
Data strobe for lower byte: Output with read data, input with write data for source synchronous operation. Edge-
aligned with read data, center-aligned with write data. LDQS# is only used when differential data strobe mode is
enabled via the LOAD MODE command.
LDQS, LDQS#
I/O
VCC
VCCQ
VREF
VSS
Supply
Supply
Supply
Supply
-
Power Supply: 1.8V 0.1V
DQ Power supply: 1.8V 0.1V. Isolated on the device for improved noise immunity
SSTL_18 reference voltage.
Ground
NC
No connect: These balls should be left unconnected.
Future use; address bits A14 and A15 are reserved for future densities.
DNU
-
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
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ADVANCED*
DESCRIPTION
ꢀhe 4Gb DDR2 SDRAM is a high-speed CMOS, dynamic
random-access memory containing 4,294,967,296 bits.
Each of the five chips in the MCP are internally configured
as 8-bank DRAM. ꢀhe block diagram of the device is
shown in Figure 2. Ball assignments and are shown in
Figure 3.
An auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of the
burst access.
As with standard DDR SDRAMs, the pipelined, multibank
architecture of DDR2 SDRAMs allows for concurrent
operation, thereby providing high, effective bandwidth by
hiding row precharge and activation time.
ꢀhe 4Gb DDR2 SDRAM uses a double-data-rate
architecture to achieve high-speed operation. ꢀhe
double data rate architecture is essentially a 4n-prefetch
architecture, with an interface designed to transfer two data
words per clock cycle at the I/O balls.Asingle read or write
access for the 4Gb DDR2 SDRAM effectively consists of
a single 4n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and four corresponding n-bit-wide,
one-half-clock-cycle data transfers at the I/O balls.
Aself refresh mode is provided, along with a power-saving
power-down mode.
All inputs are compatible with the JEDEC standard for
SSꢀTL18. All full drive-strength outputs are SSꢀTL18-
compatible.
GENERAL NOTES
•
ꢀhe functionality and the timing specifications
discussed in this data sheet are for the DTT-
enabled mode of operation.
A bidirectional data strobe (DQS, DQS#) is transmitted
externally, along with data, for use in data capture at the
receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during
WRIꢀEs. DQS is edge-aligned with data for READs and
center-aligned with data for WRIꢀEs. ꢀhere are strobes,
one for the lower byte (TDQS, TDQS#) and one for the
upper byte (UDQS, UDQS#).
•
ꢀhroughout the data sheet, the various figures and
text refer to DQs as “DQ.” ꢀhe DQ term is to be
interpreted as any and all DQ collectively, unless
specifically stated otherwise. Additionally, each chip
is divided into 2 bytes, the lower byte and upper
byte. For the lower byte (DQ0–DQ7), DM refers to
TDM and DQS refers to TDQS. For the upper byte
(DQ8–DQ15), DM refers to UDM and DQS refers to
UDQS. Note that the there is no upper byte for U4
and therefore no UDM4.
ꢀhe 4Gb DDR2 SDRAM operates from a differential clock
(CK and CK#); the crossing of CK going HIGH and CK#
going TOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.
•
•
Complete functionality is described throughout
the document and any page or diagram may have
been simplified to convey a topic and may not be
inclusive of all requirements.
Read and write accesses to the DDR2 SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACꢀIVE command, which is then followed by a READ or
WRIꢀE command. ꢀhe address bits registered coincident
with the ACꢀIVE command are used to select the bank
and row to be accessed. ꢀhe address bits registered
coincident with the READ or WRIꢀE command are used
to select the bank and the starting column location for the
burst access.
Any specific requirement takes precedence over a
general statement.
INITIALIZATION
DDR2 SDRAMs must be powered up and initialized
in a predefined manner. Operational procedures other
than those specified may result in undefined operation.
ꢀhe following sequence is required for power up and
initialization and is shown in Figure 4 on page 8.
ꢀhe DDR2 SDRAM provides for programmable read
or write burst lengths of four or eight locations. DDR2
SDRAM supports interrupting a burst read of eight with
another read, or a burst write of eight with another write.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
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ADVANCED*
FIGURE 4 – POWER-UP AND INITIALIZATION
Notes appear on page 9
VCC
V
CC
Q
1
tVꢀD1
V
ꢀꢀ
V
REF
ꢀk0
ꢀl0
ꢀm0
ꢀg0
ꢀh0
ꢀi0
ꢀj0
ꢀe0
ꢀf0
ꢀc0
ꢀd0
ꢀb0
ꢀ0
ꢀa0
t
CK
CK#
CK
t
t
CT
CT
See
note
3
SSꢀTL18
TVCMOS
TOW TEVET8
8
CKE TOW TEVET
ODꢀ
COMMAND
REF
TM
TM
VATID3
2
TM
TM
TM
PRE
PRE
TM
TM
REF
NOP
DM7
9
ADDRESS
CODE
CODE
CODE
A10 = 1
CODE
CODE
CODE
CODE
A10 = 1
VATID
High-Z
High-Z
7
DQS
DQ7
High-Z
Rꢀꢀ
t
t
t
t
t
t
t
t
t
MRD
ꢀ = 200µs (MIN)
Power-up:
CC and stable
clock (CK, CK#)
t
MRD
t
ꢀ = 400ns
(MIN)
RPA
MRD
MRD
MRD
MRD
EMR with
DTT ENABTE5
RPA
RFC
RFC
MRD
Seenote4
V
EMR(2)
EMR(3)
MR w/o
EMR with
DTT RESEꢀ OCD Default
EMR with
10
11
OCD Exit
Normal
Operation
3
200 cycles of CK
MR with
DTT RESEꢀ
Indicates a break in
time scale
DON’ꢀ CARE
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
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ADVANCED*
NOTES:
ENABLE command provide LOW to BA1, BA2 and A0; provide HIGH to BA0. Bits
E7, E8 and E9 can be set to "0" or "1;" Micron recommends setting them to "0".
10. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is
required to lock the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide
LOW to BA2 = BA1 = BA0 = 0.) CKE must be HIGH the entire time. .
11. Issue PRECHARGE ALL command.
1. Applying power; if CKE is maintained below 0.2 x VCCQ, outputs remain disabled.
To guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must
be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs
must be less than VCCQ during voltage ramp time to avoid DDR2 SDRAM device
latch-up). At least one of the following two sets of conditions (A or B) must be
met to obtain a stable supply state (stable supply defined as VCC, VCCQ,VREF, and
12. Issue two or more REFRESH commands.
V
TT are between their minimum and maximum values as stated in DC Operating
13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e.,
to program operating parameters without resetting the DLL). To access the mode
registers, BA0 = 0, BA1 = 0, BA2 = 0.
14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits
E7, E8, and E9 to “1,” and then setting all other desired parameters. To access the
extended mode register, BA2 = 0, BA1 = 0, BA0 = 1.
Conditions table):
A. (single power source) The VCC voltage ramp from 300mV to VCC (MIN) must
take no longer than 200ms; during the VCC voltage ramp, |VCC - VCCQ| ≤ 0.3V.
Once supply voltage ramping is complete (when VCCQ crosses VCC (MIN), DC
Operating Conditions table specifications apply.
•
•
•
V
V
V
CC, VCCQ are driven from a single power converter output
TT is limited to 0.95V MAX
15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7,
E8, and E9 to “0,” and then setting all other desired parameters. To access the
extended mode registers, BA2 = 0, BA1 = 0, BA0 = 1.
16. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock
cycles after the DLL RESET at Tf0.
REF tracks VCCQ/2; VREF must be within 0.3V with respect to VCCQ/2 during
supply ramp time.
CCQ ≥ VREF at all times
•
V
B. (multiple power sources) VCC ≥ VCCQ must be maintained during supply voltage
ramping, for both AC and DC levels, until supply voltage ramping completes
(VCCQ crosses VCC [MIN]). Once supply voltage ramping is complete, DC
Operating Conditions table specifications apply.
• Apply VCC before or at the same time as VCCQ; VCC voltage ramp time must
be ≤ 200ms from when VCC ramps from 300mV to VCC (MIN)
• Apply VCCQ before or at the same time as VTT; the VCCQ voltage ramp time
from when VCC (MIN) is achieved to when VCCQ (MIN) is achieved must be ≤
500ms; while VCC is ramping, current can be supplied from VCC through the
device to VCCQ
•
VREF must track VCCQ/2, VREF must be within 0.3V with respect to VCCQ/2
during supply ramp time; VCCQ ≥ VREF must be met at all times
• Apply VTT; The VTT voltage ramp time from when VCCQ (MIN) is achieved to
when VTT (MIN) is achieved must be no greater than 500ms
2. CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during
device power-up prior to VREF. being stable. After state T0, Cke is required to have
SSTL_18 input levels. Once CKE transitions to a high level, it must stay HIGH for
the duration on the initialization sequence.
3. PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode
Register, EMR = extended mode register, EMR2 = extended mode register 2,
EMR3 = extended mode register 3, REF = REFRESH command, ACT = ACTIVE
command, A10 = PRECHARGE ALL, CODE = desired value for mode registers
(blank addresses are required to be decoded), VALID - any valid command/
address, RA = row address, bank address.
4. DM represents UDM & LDM, DQS represents, UDQS, UDQS#, LDQS, LDQS#,
RDQS, RDQS#, DQ represents DQ0-71.
5. For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or
DESELECT commands, then take CKE HIGH.
6. Wait a minimum of 400ns, then issue a PRECHARGE ALL command.
7. Issue a LOAD MODE command to the EMR(2). (To issue an EMR(3) command,
provide LOW to BA2 and BA0, and provide HIGH to BA1.) Set register E7 to "0" or
"1;" all others must be "0".
8. Issue LOAD MODE command to the EMR(3). (to issue and EMR(3) command,
provide HIGH to BA0 = 1, BA1 = 1, and BA2 = 0.) Set all registers to "0".
9. Issue a LOAD MODE command to the EMR to enable DLL. To issue a CLL
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
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ADVANCED*
FIGURE 5 – MODE REGISTER (MR) DEFINITION
MODE REGISTER (MR)
ꢀhe mode register is used to define the specific mode of
operation of the DDR2 SDRAM. ꢀhis definition includes
the selection of a burst length, burst type, CT, operating
mode, DTTRESEꢀ, write recovery, and power-down mode,
as shown in Figure 5. Contents of the mode register can be
altered by re-executing the TOAD MODE (TM) command.
If the user chooses to modify only a subset of the MR
variables, all variables (M0–M14) must be programmed
when the command is issued.
BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
01 PD
MR
WR
DTT ꢀM CAS# Tatency Bꢀ Burst Tength
Mode
Normal
ꢀest
M7
0
M2 M1 M0
Burst Tength
Reserved
Reserved
4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
PD mode
M12
0
Fast Exit
(Normal)
Slow Exit
ꢀhe mode register is programmed via the TM command
(bits BA2–BA0 = 0, 0, 0) and other bits (M12–M0) will
retain the stored information until it is programmed again
or the device loses power (except for bit M8, which is
self-clearing). Reprogramming the mode register will
not alter the contents of the memory array, provided it is
performed correctly.
DTT Reset
No
M8
0
8
1
Reserved
Reserved
Reserved
Reserved
1
Yes
(Tow Power)
WRIꢀE RECOVERY
M11 M10 M9
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
Burst ꢀype
Sequential
Interleaved
M3
0
3
ꢀhe TM command can only be issued (or reissued) when all
banks are in the precharged state (idle state) and no bursts
are in progress. ꢀhe controller must wait the specified
4
1
5
6
CAS Tatency (CT)
M6 M5 M4
Reserved
Reserved
t
time MRD before initiating any subsequent operations
Reserved
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
such as an ACꢀIVE command. Violating either of these
requirements will result in unspecified operation.
Reserved
Reserved
Mode Register Definition
Mode Register (MR)
M15 M14
3
0
1
0
1
0
0
1
1
4
Extended Mode Register (EMR)
Extended Mode Register (EMR2)
Extended Mode Register (EMR3)
BURST LENGTH
5
6
Burst length is defined by bits M0–M3, as shown in Figure
5. Read and write accesses to the DDR2 SDRAM are
burst-oriented, with the burst length being programmable
to either four or eight. ꢀhe burst length dete rmines
the maximum number of column locations that can be
accessed for a given READ or WRIꢀE command.
Reserved
Note: 1. Not used on this part
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved. ꢀhe burst type is selected
via bit M3, as shown in Figure 5. ꢀhe ordering of accesses
within a burst is determined by the burst length, the burst
type, and the starting column address, as shown in ꢀable
2. DDR2 SDRAM supports 4-bit burst mode and 8-bit burst
mode only. For 8-bit burst mode, full interleave address
ordering is supported; however, sequential address
ordering is nibble-based.
When a READ or WRIꢀE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. ꢀhe block is uniquely selected by
A2–Ai when BT = 4 and by A3–Ai when BT = 8 (where
Ai is the most significant column address bit for a given
configuration). ꢀhe remaining (least significant) address
bit(s) is (are) used to select the starting location within the
block. ꢀhe programmed burst length applies to both READ
and WRIꢀE bursts.
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DLL RESET
TABLE 2 – BURST DEFINITION
DTT RESEꢀ is defined by bit M8, as shown in Figure 5.
Programming bit M8 to “1” will activate the DTT RESEꢀ
function. Bit M8 is self-clearing, meaning it returns back
to a value of “0” after the DTT RESEꢀ function has been
issued.
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Burst
Starting Column
Address
Length
A1
0
A0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
Anytime the DTTRESEꢀ function is used, 200 clock cycles
must occur before a READ command can be issued to
allow time for the internal clock to be synchronized with
the external clock. Failing to wait for synchronization
4
0
1
1
0
1
1
t
t
A2
0
A1
0
A0
0
to occur may result in a violation of the AC or DQSCK
parameters.
0-1-2-3-4-5-6-7
1-2-3-0-5-6-7-4
2-3-0-1-6-7-4-5
3-0-1-2-7-4-5-6
4-5-6-7-0-1-2-3
5-6-7-4-1-2-3-0
6-7-4-5-2-3-0-1
7-4-5-6-3-0-1-2
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0
0
1
WRITE RECOVERY
0
1
0
Write recovery (WR) time is defined by bits M9–M11, as
shown in Figure 5. ꢀhe WR register is used by the DDR2
SDRAM during WRIꢀE with auto precharge operation.
During WRIꢀE with auto precharge operation, the DDR2
SDRAM delays the internal auto precharge operation by
WR clocks (programmed in bits M9–M11) from the last
data burst.
8
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
WR values of 2, 3, 4, 5, or 6 clocks may be used for
programming bits M9–M11. ꢀhe user is required to
program the value of WR, which is calculated by dividing
tWR (in ns) by tCK (in ns) and rounding up a non integer
value to the next integer; WR [cycles] = tWR [ns] / tCK [ns].
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects the
starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select the
starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2 select the
starting column within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
POWER-DOWN MODE
Active power-down (PD) mode is defined by bit M12,
as shown in Figure 5. PD mode allows the user to
determine the active power-down mode, which determines
performance versus power savings. PD mode bit M12 does
not apply to precharge PD mode.
OPERATING MODE
ꢀhe normal operating mode is selected by issuing a
command with bit M7 set to “0,” and all other bits set to
the desired values, as shown in Figure 5. When bit M7 is
“1,” no other bits of the mode register are programmed.
Programming bit M7 to “1” places the DDR2 SDRAM into a
test mode that is only used by the manufacturer and should
not be used. No operation or functionality is guaranteed
if M7 bit is ‘1.’
When bit M12 = 0, standard active PD mode or “fast-exit”
active PD mode is enabled. ꢀhe tXARD parameter is used
for fast-exit active PD exit timing. ꢀhe DTT is expected to
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode or “slow-
exit” active PD mode is enabled. ꢀhe tXARD parameter is
used for slow-exit active PD exit timing. ꢀhe DTT can be
enabled, but “frozen” during active PD mode since the exit-
to-READ command timing is relaxed. ꢀhe power difference
expected between PD normal and PD low-power mode is
defined in the ICC table.
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CAS LATENCY (CL)
ꢀhe CAS latency (CT) is defined by bits M4–M6, as shown
in Figure 5. CT is the delay, in clock cycles, between the
registration of a READ command and the availability of
the first bit of output data. ꢀhe CT can be set to 3, 4, 5,
or 6 clocks, depending on the speed grade option being
used.
DDR2 SDRAM also supports a feature called posted
CAS additive latency (AT). ꢀhis feature allows the READ
command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AT clocks.
Examples of CT = 3 and CT = 4 are shown in Figure 6;
both assume AT = 0. If a READ command is registered
at clock edge n, and the CT is m clocks, the data will be
available nominally coincident with clock edge n+m (this
assumes AL = 0).
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
FIGURE 6 – CAS LATENCY (CL)
ꢀ0
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQS, DQS#
D
OUꢀ
D
OUꢀ
D
OUꢀ
DOUꢀ
n + 3
DQ
n
n + 1
n + 2
CT = 3 (AT = 0)
ꢀ0
ꢀ1
ꢀ2
ꢀ3
ꢀ4
ꢀ5
ꢀ6
CK#
CK
READ
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
DQS, DQS#
D
OUꢀ
D
OUꢀ
D
OUꢀ
DOUꢀ
n + 3
DQ
n
n + 1
n + 2
CT = 4 (AT = 0)
Burst length = 4
Posted CAS# additive latency (AT) = 0
t
t t
AC, DQSCK, and DQSQ
ꢀRANSIꢀIONING DAꢀA
DON’ꢀ CARE
Shown with nominal
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EXTENDED MODE REGISTER (EMR)
ꢀhe extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DTT enable/disable, output drive strength,
on die termination (ODꢀ) (Rꢀꢀ), postedAT, off-chip driver
impedance calibration (OCD), DQS# enable/disable,
RDQS/RDQS# enable/disable, and output disable/enable.
ꢀhese functions are controlled via the bits shown in
Figure 7. ꢀhe EMR is programmed via the TOAD MODE
(TM) command and will retain the stored information
until it is programmed again or the device loses power.
Reprogramming the EMR will not alter the contents of the
memory array, provided it is performed correctly.
ꢀhe EMR must be loaded when all banks are idle and
no bursts are in progress, and the controller must wait
the specified time tMRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecified operation.
FIGURE 7 – EXTENDED MODE REGISTER DEFINITION
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3
A2 A1 A0
Address Bus
Extended Mode
Register (Ex)
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
02 out
OCD Program
Posted CAS#
ODS DLL
MRS
RTT
RTT
RDQS DQS#
Outputs
Enabled
Disabled
E0
0
DLL Ena ble
Enable (Normal)
E12
0
Rtt (nominal)
RTT disabled
75Ω
E6 E2
1
1
0
0
1
1
0
1
0
1
Disable (Test/Debug)
Output Drive Strength
RDQ S Ena ble
150 Ω
E11
0
E1
0
No
50Ω
Full strength (18 Ω target)
1
Yes
1
Reduced strength (40 Ω target)
E10
0
DQ S# Ena ble
Posted CA S# A dditive Laten cy (AL)
E5 E4 E3
Enable
Disable
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
2
3
E9 E8 E7
OCD Operation
1
0
0
0
1
1
0
0
1
0
1
0
1
0
0
1
OCD not supported
Reserved
4
Reserved
Reserved
Reserved
Reserved
Reserved
1
OCD default state
Mo de Regi ster Set
Mode register set (MRS)
E16 E15 E14
0
1
0
1
0
0
0
0
0
0
1
1
Extended mode register (EMRS)
Extended mode register (EMRS2)
Extended mode register (EMRS3)
Note: 1. During initialization, all three bits must be set to "1" for OCD default state,
then must be set to "0" before initialization is finished, as detailed in the
initialization procedure.
2.. E13 (A13) is not used on this device.
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DLL ENABLE/DISABLE
OUTPUT ENABLE/DISABLE
ꢀhe DTT may be enabled or disabled by programming bit
E0 during the TM command, as shown in Figure 7. ꢀhe
DTT must be enabled for normal operation. DTT enable is
required during power-up initialization and upon returning
to normal operation after having disabled the DTT for the
purpose of debugging or evaluation. Enabling the DTT
should always be followed by resetting the DTT using an
TM command.
ꢀhe OUꢀPUꢀ ENABTE function is defined by bit E12, as
shown in Figure 7. When enabled (E12 = 0), all outputs
(DQs, DQS, DQS#, RDQS, RDQS#) function normally.
When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs,
DQS, DQS#, RDQS, RDQS#) are disabled, thus removing
output buffer current. ꢀhe output disable feature is intended
to be used during ICC characterization of read current.
ON-DIE TERMINATION (ODT)
ꢀhe DTT is automatically disabled when entering SETF
REFRESH operation and is automatically re-enabled and
reset upon exit of SETF REFRESH operation.
ODꢀ effective resistance, Rꢀꢀ (EFF), is defined by bits
E2 and E6 of the EMR, as shown in Figure 7. ꢀhe ODꢀ
feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller
to independently turn on/off ODꢀ for any or all devices.
Rꢀꢀ effective resistance values of 50Ω ,75Ω, and 150Ω
are selectable and apply to each DQ, DQS/DQS#, RDQS/
RDQS#, UDQS/UDQS#, TDQS/TDQS#, DM, and UDM/
TDM signals. Bits (E6, E2) determine what ODꢀ resistance
is enabled by turning on/off “sw1,” “sw2,” or “sw3.” ꢀhe
ODꢀ effective resistance value is elected by enabling
switch “sw1,” which enables all R1 values that are 150Ω
each, enabling an effective resistance of 75Ω (Rꢀꢀ2(EFF)
= R2/2). Similarly, if “sw2” is enabled, all R2 values that
are 300Ω each, enable an effective ODꢀ resistance of
150Ω (Rꢀꢀ2(EFF) = R2/2). Switch “sw3” enables R1 values
of 100Ω enabling effective resistance of 50Ω Reserved
states should not be used, as unknown operation or
incompatibility with future versions may result.
Any time the DTTis enabled (and subsequently reset), 200
clock cycles must occur before a READ command can be
issued, to allow time for the internal clock to synchronize
with the external clock. Failing to wait for synchronization
t
t
to occur may result in a violation of the AC or DQSCK
parameters.
OUTPUT DRIVE STRENGTH
ꢀhe output drive strength is defined by bit E1, as shown
in Figure 7. ꢀhe normal drive strength for all outputs are
specified to be SSꢀTL18. Programming bit E1 = 0 selects
normal (full strength) drive strength for all outputs. Selecting
a reduced drive strength option (E1 = 1) will reduce all
outputs to approximately 60 percent of the SSꢀTL18 drive
strength. ꢀhis option is intended for the support of lighter
load and/or point-to-point environments.
ꢀhe ODꢀ control ball is used to determine when Rꢀꢀ(EFF)
is turned on and off, assuming ODꢀ has been enabled via
bits E2 and E6 of the EMR. ꢀhe ODꢀ feature and ODꢀ
input ball are only used during active, active power-down
(both fast-exit and slow-exit modes), and precharge power-
down modes of operation. ODꢀ must be turned off prior to
entering self refresh. During power-up and initialization of
the DDR2 SDRAM, ODꢀ should be disabled until issuing
the EMR command to enable the ODꢀ feature, at which
point the ODꢀ ball will determine the Rꢀꢀ(EFF) value.
Any time the EMR enables the ODꢀ function, ODꢀ may
not be driven HIGH until eight clocks after the EMR has
been enabled. See “ODꢀ ꢀiming” section for ODꢀ timing
diagrams.
DQS# ENABLE/DISABLE
ꢀhe DQS# ball is enabled by bit E10. When E10 = 0,
DQS# is the complement of the differential data strobe pair
DQS/DQS#. When disabled (E10 = 1), DQS is used in a
single ended mode and the DQS# ball is disabled. When
disabled, DQS# should be left floating. ꢀhis function is also
used to enable/disable RDQS#. If RDQS is enabled (E11
= 1) and DQS# is enabled (E10 = 0), then both DQS# and
RDQS# will be enabled.
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POSTED CAS ADDITIVE LATENCY (AL)
Posted CAS additive latency (AT) is supported to make
the command and data bus efficient for sustainable
bandwidths in DDR2 SDRAM. Bits E3–E5 define the value
of AT, as shown in Figure 7. Bits E3–E5 allow the user
to program the DDR2 SDRAM with an inverse AT of 0, 1,
2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions
may result.
In this operation, the DDR2 SDRAM allows a READ or
t
WRIꢀE command to be issued prior to RCD (MIN) with
the requirement thatAT ≤ tRCD (MIN).Atypical application
using this feature would setAT = tRCD (MIN) - 1x tCK. ꢀhe
READ or WRIꢀE command is held for the time of the AT
before it is issued internally to the DDR2 SDRAM device.
RT is controlled by the sum of AT and CT; RT = AT+CT.
Write latency (WT) is equal to RT minus one clock; WT =
AT + CT - 1 x tCK.
FIGURE 8 – EXTENDED MODE REGISTER 2 (EMR2) DEFINITION
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0
Address Bus
Exten ded Mo de
Register (Ex)
16
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
01
01 01
01
01 01 01 01 01 01 01 01
01 01
EMR2
Mode Register Definition
M1 6 M15 M14
High Temperature Self Refresh rate enable
E7
0
Mode register (MR)
0
1
0
1
0
0
0
0
0
0
1
1
Commercial temperature default
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Industrial temperature option;
use if T C exceeds 85° C
1
Note: 1. E13 (A13)-E0(A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
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FIGURE 9 – EXTENDED MODE REGISTER 3 (EMR3) DEFINITION
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0
Address Bus
Exten ded Mo de
Register (Ex)
16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
01
01 01 01 01 01 01 01 01 01 01 01
01 01
EMR3
Mode Register Definition
M1 6 M15 M14
Mode register (MR)
0
1
0
1
0
0
0
0
0
0
1
1
Extended mode register (EMR)
Extended mode register (EMR2)
Extended mode register (EMR3)
Note: 1. E13 (A13)-E0 (A0) are reserved for future use and must be programmed to
"0." A13 is not used in this device.
EXTENDED MODE REGISTER 2
not alter the contents of the memory array, provided it is
performed correctly.
ꢀhe extended mode register 2 (EMR2) controls functions
beyond those controlled by the mode register. Currently
all bits in EMR2 are reserved, as shown in Figure 8. ꢀhe
EMR2 is programmed via the TM command and will
retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will
not alter the contents of the memory array, provided it is
performed correctly.
EMR3 must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
t
specified time MRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecified operation.
Bit E7 (A7) must be programmed as"1" to provide a faster
refresh rate on devices if the ꢀCASE exceeds 85°C
COMMAND TRUTH TABLES
ꢀhe following tables provide a quick reference of DDR2
SDRAM available commands, including CKE power-down
modes, and bank-to-bank commands.
EMR2 must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
t
specified time MRD before initiating any subsequent
operation. Violating either of these requirements could
result in unspecified operation.
EXTENDED MODE REGISTER 3
ꢀhe extended mode register 3 (EMR3) controls functions
beyond those controlled by the mode register. Currently,
all bits in EMR3 are reserved, as shown in Figure 9.
ꢀhe EMR3 is programmed via the TM command and will
retain the stored information until it is programmed again
or the device loses power. Reprogramming the EMR will
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TABLE 3 – TRUTH TABLE - DDR2 COMMANDS
Notes 1, 5, and 6 apply to all
CKE
BA2
BA1
BA0
A12
A11
Function
CS#
RAS#
CAS#
WE#
A10
A9-A0
Notes
Previous
Cycle
Current
Cycle
H
H
H
H
H
L
L
L
L
L
L
L
L
BA
X
OP Code
2
LOAD MODE
REFRESH
H
X
X
X
X
X
X
L
H
L
L
X
H
L
L
X
H
H
H
X
H
L
X
SELF-REFRESH Entry
L
H
X
X
X
X
7
2
SELF-REFRESH Exit
H
H
H
H
H
H
L
X
X
X
X
L
H
X
X
Single bank precharge
All banks PRECHARGE
Bank activate
L
L
L
L
H
H
L
L
BA
Row Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
Column
Address
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
L
L
L
L
BA
BA
BA
BA
L
H
L
2, 3
2, 3
2, 3
2, 3
WRITE
WRITE with auto precharge
READ
H
L
L
H
H
L
H
H
H
READ with auto precharge
H
H
X
X
H
X
X
X
X
X
X
X
X
NO OPERATION
H
H
L
H
L
X
X
H
X
H
X
X
H
X
H
X
X
H
X
H
Device DESELECT
H
L
X
X
X
X
X
X
X
4
4
POWER-DOWN entry
L
H
X
POWER-DOWN exit
Note: 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a LM command selects which mode register is programmed.
3. 3. Burst reads or writes at BL = 4 cannot be terminated or interrupted.
4. The power-down mode does not perform any REFRESH operations. The duration of power-down is therefore limited by the refresh requirements outlined in the AC
parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh. See “On-Die Termination (ODT)” for details.
6. “X” means “H or L” (but a defined logic level).
7. Self refresh exit is asynchronous.
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DESELECT
ꢀhe DESETECꢀ function (CS# HIGH) prevents new
commands from being executed by the DDR2 SDRAM.
ꢀhe DDR2 SDRAM is effectively deselected. Operations
already in progress are not affected.
entered. ꢀhe same procedure is used to convert other
specification limits from time units to clock cycles. For
t
example, a RCD (MIN) specification of 20ns with a 266
MHz clock (tCK = 3.75ns) results in 5.3 clocks, rounded
up to 6.
NO OPERATION (NOP)
A subsequent ACꢀIVE command to a different row in the
same bank can only be issued after the previous active
row has been closed (precharged). ꢀhe minimum time
interval between successive ACꢀIVE commands to the
same bank is defined by tRC
ꢀhe NO OPERAꢀION (NOP) command is used to instruct
the selected DDR2 SDRAM to perform a NOP (CS# is
TOW; RAS#, CAS#, and WE are HIGH). ꢀhis prevents
unwanted commands from being registered during idle
or wait states. Operations already in progress are not
affected.
A subsequent ACꢀIVE command to another bank can be
issued while the first bank is being accessed, which results
in a reduction of total row-access overhead. ꢀhe minimum
time interval between successive ACꢀIVE commands to
different banks is defined by tRRD
LOAD MODE (LM)
ꢀhe mode registers are loaded via inputs BA2–BA0, and
A12–A0. BA2–BA0 determine which mode register will
be programmed. See “Mode Register (MR)”. ꢀhe TM
command can only be issued when all banks are idle, and
a subsequent execute able command cannot be issued
until tMRD is met.
FIGURE 10 – ACTIVE COMMAND
BANK/ROW ACTIVATION
ACTIVE COMMAND
CK#
CK
ꢀhe ACꢀIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. ꢀhe
value on the BA2–BA0 inputs selects the bank, and the
address provided on inputs A12–A0 selects the row.
ꢀhis row remains active (or open) for accesses until
a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening
a different row in the same bank.
CKE
CS#
RAS#
CAS#
WE#
ACTIVE OPERATION
Before any READ or WRIꢀE commands can be issued to
a bank within the DDR2 SDRAM, a row in that bank must
be opened (activated), even when additive latency is used.
ꢀhis is accomplished via the ACꢀIVE command, which
selects both the bank and the row to be activated.
Row
ADDRESS
BANK ADDRESS
Bank
After a row is opened with an ACꢀIVE command, a READ
or WRIꢀE command may be issued to that row, subject to
the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACꢀIVE
command on which a READ or WRIꢀE command can be
DON’ꢀ CARE
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READ COMMAND
ꢀhe READ command is used to initiate a burst read access
to an active row. ꢀhe value on the BA2–BA0 inputs selects
the bank, and the address provided on inputsA0–i (where
i = A9) selects the starting column location. ꢀhe value on
input A10 determines whether or not auto precharge is
used. If auto precharge is selected, the row being accessed
will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
FIGURE 11 – READ COMMAND
READ OPERATION
CK#
CK
READ bursts are initiated with a READ command. ꢀhe
starting column and bank addresses are provided with the
READ command and auto precharge is either enabled or
disabled for that burst access. If auto precharge is enabled,
the row being accessed is automatically precharged at the
completion of the burst. If auto precharge is disabled, the
row will be left open after the completion of the burst.
CKE
CS#
RAS#
CAS#
During READ bursts, the valid data-out element from the
starting column address will be available READ latency
(RT) clocks later. RT is defined as the sum of AT and CT;
RT = AT + CT. ꢀhe value for AT and CT are programmable
via the MR and EMR commands, respectively. Each
subsequent data-out element will be valid nominally at
the next positive or negative clock edge (i.e., at the next
crossing of CK and CK#).
WE#
ADDRESS
Col
ENABTE
A10
DQS/DQS# is driven by the DDR2 SDRAM along with
output data. ꢀhe initial TOW state on DQS and HIGH state
on DQS# is known as the read preamble (tRPRE). ꢀhe
TOW state on DQS and HIGH state on DQS# coincident
with the last data-out element is known as the read
postamble (tRPSꢀ).
AUꢀO PRECHARGE
BANK ADDRESS
DISABTE
Bank
DON’ꢀ CARE
Upon completion of a burst, assuming no other commands
have been initiated, the DQ will go High-Z.
Data from any READ burst may be concatenated with
data from a subsequent READ command to provide a
continuous flow of data. ꢀhe first data element from the
new burst follows the last element of a completed burst.
ꢀhe new READ command should be issued x cycles after
the first READ command, where x equals BT / 2 cycles.
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WRITE COMMAND
DQS edge is WT tDQSS. Subsequent DQS positive rising
edges are timed, relative to the associated clock edge, as
tDQSS. tDQSS is specified with a relatively wide range
(25 percent of one clock cycle).All of the WRIꢀE diagrams
show the nominal case, and where the two extreme cases
ꢀhe WRIꢀE command is used to initiate a burst write
access to an active row. ꢀhe value on the BA2–BA0 inputs
selects the bank, and the address provided on inputsA0–9
selects the starting column location. ꢀhe value on input
A10 determines whether or not auto precharge is used.
If auto precharge is selected, the row being accessed
will be precharged at the end of the WRIꢀE burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses.
t
(tDQSS [MIN] and DQSS [MAX]) might not be intuitive,
they have also been included. Upon completion of a burst,
assuming no other commands have been initiated, the
DQ will remain High-Z and any additional input data will
be ignored.
Input data appearing on the DQ is written to the memory
array subject to the DM input logic level appearing
coincident with the data. If a given DM signal is registered
TOW, the corresponding data will be written to memory; if
the DM signal is registered HIGH, the corresponding data
inputs will be ignored, and a WRIꢀE will not be executed
to that byte/column location.
Data for any WRIꢀE burst may be concatenated with a
subsequent WRIꢀE command to provide continuous flow
of input data. ꢀhe first data element from the new burst is
applied after the last element of a completed burst. ꢀhe
new WRIꢀE command should be issued x cycles after the
first WRIꢀE command, where x equals BT/2.
DDR2 SDRAM supports concurrent auto precharge
options, as shown in ꢀable 4.
WRITE OPERATION
WRIꢀE bursts are initiated with a WRIꢀE command, as
shown in Figure 12. DDR2 SDRAM uses WT equal to RT
minus one clock cycle [WT = RT - 1CK = AT + (CT - 1CK)].
ꢀhe starting column and bank addresses are provided
with the WRIꢀE command, and auto precharge is either
enabled or disabled for that access. If auto precharge is
enabled, the row being accessed is precharged at the
completion of the burst.
DDR2 SDRAM does not allow interrupting or truncating
any WRIꢀE burst using BT = 4 operation. Once the BT
= 4 WRIꢀE command is registered, it must be allowed
to complete the entire WRIꢀE burst cycle. However,
a WRIꢀE (with auto precharge disabled) using BT = 8
operation might be interrupted and truncated ONTY by
another WRIꢀE burst as long as the interruption occurs
on a 4-bit boundary, due to the 4n prefetch architecture of
DDR2 SDRAM. WRIꢀE burst BT = 8 operations may not
to be interrupted or truncated with any command except
another WRIꢀE command.
During WRIꢀE bursts, the first valid data-in element will
be registered on the first rising edge of DQS following the
WRIꢀE command, and subsequent data elements will be
registered on successive edges of DQS. ꢀhe TOW state
on DQS between the WRIꢀE command and the first rising
edge is known as the write preamble; the TOW state on
DQS following the last data-in element is known as the
write postamble.
Data for any WRIꢀE burst may be followed by a
subsequent READ command. ꢀhe number of clock cycles
required to meet tWꢀR is either 2 or tWꢀR/tCK, whichever
is greater. Data for any WRIꢀE burst may be followed by a
subsequent PRECHARGE command. tWꢀ starts at the end
of the data burst, regardless of the data mask condition.
ꢀhe time between the WRIꢀE command and the first rising
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FIGURE 12 – WRITE COMMAND
CK#
CK
CKE
CS#
HIGH
RAS#
CAS#
WE#
ADDRESS
A10
CA
EN AP
DIS AP
BANK ADDRESS
BA
DON’ꢀ CARE
Note: CA = column address; BA = bank address; EN AP = enable auto precharge; and
DIS AP = disable auto precharge.
TABLE 4 – WRITE USING CONCURRENT AUTO PRECHARGE
Minimum Delay (With Concurrent
From Command (Bank n)
To Command (Bank m)
Units
Auto Precharge)
READ OR READ w/AP
WRITE or WRITE w/AP
PRECHARGE or ACTIVE
(CL-1) + (BL/2) + tWTR
tCK
tCK
tCK
(BL/2)
1
WRITE with Auto Precharge
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PRECHARGE COMMAND
ꢀhe PRECHARGE command, illustrated in Figure 13, is
used to deactivate the open row in a particular bank or
the open row in all banks. ꢀhe bank(s) will be available
for a subsequent row activation a specified time (tRP)
after the PRECHARGE command is issued, except in
the case of concurrent auto precharge, where a READ or
WRIꢀE command to a different bank is allowed as long
as it does not interrupt the data transfer in the current
bank and does not violate any other timing parameters.
Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRIꢀE
commands being issued to that bank. A PRECHARGE
command is allowed if there is no open row in that bank
(idle state) or if the previously open row is already in the
process of precharging. However, the precharge period
will be determined by the last PRECHARGE command
issued to the bank.
FIGURE 13 – PRECHARGE COMMAND
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
PRECHARGE OPERATION
ADDRESS
Input A10 determines whether one or all banks are to be
precharged, and in the case where only one bank is to be
precharged, inputs BA2–BA0 select the bank. Otherwise
BA2–BA0 are treated as “Don’t Care.”
ATT BANKS
A10
ONE BANK
BA0 - BA2
BA
When all banks are to be precharged, inputs BA2–BA0
are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRIꢀE commands being issued to that
bank. tRPA timing applies when the PRECHARGE (ATT)
command is issued, regardless of the number of banks
already open or closed. If a single-bank PRECHARGE
command is issued, tRP timing applies. tRPA(MIN) applies
to all 8-bank DDR2 devices.
DON’ꢀ CARE
Note: BA = bank address (if A10 is LOW; otherwise "Don't Care").
cycles must then occur before a READ command can be
issued). ꢀhe differential clock should remain stable and
meet CKE specifications at least 1 x CK after entering
self refresh mode. All command and address input signals
except CKE are “Don’t Care” during self refresh.
t
t
SELF REFRESH COMMAND
ꢀhe procedure for exiting self refresh requires a sequence
of commands. First, the differential clock must be stable
and meet tCK specifications at least 1 x tCK prior to CKE
going back HIGH. Once CKE is HIGH (tCTE(MIN) has
been satisfied with four clock registrations), the DDR2
SDRAM must have NOP or DESETECꢀ commands issued
for tXSNR because time is required for the completion of
any internal refresh in progress. A simple algorithm for
meeting both refresh and DTT requirements is to apply
NOP or DESETECꢀ commands for 200 clock cycles before
applying any other command.
ꢀhe SETF REFRESH command can be used to retain
data in the DDR2 SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR2 SDRAM retains data without external clocking. All
power supply inputs (including VREF) must be maintained
at valid levels upon entry/exit and during SETF REFRESH
operation.
ꢀhe SETF REFRESH command is initiated like a
REFRESH command except CKE is TOW. ꢀhe DTT is
automatically disabled upon entering self refresh and is
automatically enabled upon exiting self refresh (200 clock
Note: Self refresh not available at military temperature..
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DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
VCCQ
VREF
VTT
Min
1 .7
1 .7
Typical
1 .8
1 .8
0.50 x VCCQ
VREF
Max
1 .9
1 .9
Unit
V
V
V
V
Notes
Supply voltage
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage
Notes:
1
4
2
3
0.49 x VCCQ
VREF-0.04
0.51 x VCCQ
VREF + 0.04
1.
2.
V
CC VCCQ must track each other. VCCQ must be less than or equal to VCC
.
V
REF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
3.
4.
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
V
CCQ tracks with VCC track with VCC
.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VCCQ
VIN, VOUT
TSTG
Parameter
MIN
-1.0
-0.5
-0.5
-55
MAX
2.3
2.3
2.3
125
U nit
V
V
V
°C
Voltage on VCC pin relative to VSS
Voltage on VCCQ pin relative to VSS
Voltage on any pin relative to VSS
Storage temperature
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
CK, CK#
DM
-25
25
µA
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
IL
-10
-5
10
5
µA
µA
Output leakage current;
IOZ
DQ, DQS, DQS#
-5
5
µA
µA
0V<VOUT<VCCQ; DQs and ODT are disable
IVREF
VREF leakage current; VREF = Valid VREF level
-10
10
INPUT/OUTPUT CAPACITANCE
TA = 25°C, f = 1MHz, VCC = VCCQ = 1.8V
Parameter
Symbol
Max
TBD
TBD
TBD
TBD
Unit
Input capacitance (A0 - A12, BA0 - BA2 ,CS#, RAS#,CAS#,WE#, CKE, ODT)
Input capacitance CK, CK#
CIN1
CIN2
CIN3
COUT
pF
pF
pF
pF
Input capacitance DM, DQS, DQS#
Input capacitance DQ0 - 71
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INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
VREF + 0.1 25
-0.300
Max
Unit
V
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VCCQ + 0.300
VREF - 0.125
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
VREF + 0.250
VREF + 0.200
—
Max
—
Unit
V
AC Input High (Logic 1) Voltage DDR2-400 & DDR2-533
AC Input High (Logic 1) Voltage DDR2-667
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0) Voltage DDR2-667
—
V
VREF - 0.250
VREF - 0.200
V
—
V
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DDR2 ICC SPECIFICATIONS AND CONDITIONS
VCC = 1.8V 0.1V; -55°C ≤ TA ≤ 125°C
Symbol Proposed Conditions
Operating one bank active-precharge current;
533 CL4 400 CL3
Units
ICC0
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
675
550
mA
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD = tRCD(ICC);
CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDAD6W
ICC1
650
600
mA
Precharge power-down current;
ICC2P
ICC2Q
ICC2N
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING
35
35
mA
mA
mA
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are STABLE;
Data bus inputs are FLOATING
325
350
225
250
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
200
50
150
50
mA
mA
ICC3P
Active standby current;
ICC3N
All banks open; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
375
300
900
mA
mA
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS = tRASMAX(ICC), tRP
= tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING; Data
bus inputs are SWITCHING
ICC4W
1,000
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
ICC4R
1,300
1,250
mA
tRASMAX(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
Burst auto refresh current;
ICC5
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,350
35
1,250
35
mA
mA
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
ICC6
Normal
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC), tRC
=
ICC7
t
RC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address
1,750
1,650
mA
bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R; Refer to the following page for
detailed timing conditions
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AC TIMING PARAMETERS
-55°C ≤ TA < +125°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
533Mbs CL4
Symbol
400Mbs CL3
Unit
Parameter
Min
3,750
Max
8,000
8,000
0.52
Min
5,000
Max
8,000
8,000
0.52
CL=4
CL=3
tCK(4)
tCK(3)
tCH
ps
ps
tCK
tCK
ps
Clock cycle time
5,000
5,000
CK high-level width
CK low-level width
Half clock period
0.48
0.48
tCL
0.48
0.52
0.48
0.52
tHP
MIN (tCH, tCL)
tCKAVG
MIN (tCH, tCL)
tCKAVG
tCKAVG
tCKAVG
Absolute tCK
tCKabs
tCHabs
(MIN)+ tJITPER (MAX)+ tJITPER (MIN)+ tJITPER (MAX)+ tJITPER
ps
(MIN)
(MAX)
(MIN)
(MAX)
tCKAVG
tCKAVG
(MIN)* tCHAVG
(MIN)+ tJITDTY
(MIN)
tCKAVG
tCKAVG
(MAX)*
(MIN)* tCHAVG (MAX)* tCHAVG
(MIN)+ tJITDTY (MAX)+ tJITDTY
Absolute CK high-level width
tCHAVG
ps
(MAX)+ tJITDTY
(MAX)
(MIN)
(MAX)
tCKAVG
(MIN)*
tCLAVG
tCKAVG
(MAX)*
tCLAVG
tCKAVG
(MIN)*
tCLAVG
tCKAVG
(MAX)*
tCLAVG
Absolute CK low-level width
tCLabs
ps
(MIN)+ tJITDTY (MAX)+ tJITDTY (MIN)+ tJITDTY (MAX)+ tJITDTY
(MIN)
-125
-125
(MAX)
125
(MIN)
-125
-125
(MAX)
125
Clock jitter - period
tJITPER
tJITDUTY
tJITCC
tERR2per
tERR3per
tERR4per
tERR5per
tERR6-10per
tERR11-50per
ps
ps
ps
ps
ps
ps
ps
ps
ps
Clock jitter - half period
125
125
Clock jitter - cycle to cycle
250
250
Cumulative jitter error, 2 cycles
Cumulative jitter error, 3 cycles
Cumulative jitter error, 4 cycles
Cumulative jitter error, 5 cycles
Cumulative jitter error, 6-10 cycles
Cumulative jitter error, 11-50 cycles
-175
-225
-250
-250
-350
-450
175
225
250
250
350
450
-175
-225
-250
-250
-350
-450
175
225
250
250
350
450
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AC TIMING PARAMETERS (continued)
-55°C ≤ TA < +125°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
533Mbs CL4
Symbol
400Mbs CL3
Unit
Parameter
DQ hold skew factor
Min
-
Max
400
Min
-
Max
450
tQHS
tAC
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
tCK
tCK
ps
tCK
tCK
ps
tCK
tCK
ps
DQ output access time from CK/CK#
Data-out high impedance window from CK/CK#
DQS Low-Z window from CK/CK#
DQ Low-Z window from CK/CK#
-500
+500
-600
+600
tHZ
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tAC(MAX)
tLZ1
tAC(MN)
2*tAC(MN)
350
tAC(MN)
2*tAC(MN)
400
tLZ2
tDSa
tDHa
350
400
DQ and DM input setup time relative to DQS
tDSb
100
150
tDHb
225
275
DQ and DM input pulse width (for each input)
Data hold skew factor
tDIPW
tQHS
tQH
0.35
0.35
400
450
DQ-DQS hold, DQS to first DQ to go nonvalid, per access
Data valid output window (DVW)
tHP - tQHS
tQH - tDQSQ
0.35
tHP - tQHS
tQH - tDQSQ
0.35
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tDSH
tDQSQ
tRPRE
tRPST
tWPRES
DQS input high pulse width
DQS input low pulse width
0.35
0.35
DQS output access time fromCK/CK#
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
DQS-DQ skew, DOS to last DQ valid, per group, per access
DQS read preamble
-450
+450
-500
+500
0.2
0.2
0.2
0.2
300
1.1
0.6
350
1.1
0.6
0.9
0.4
0
0.9
0.4
0
DQS read postamble
DQS write preamble setup time
DQS write preamble
tWPRE
0.25
0.25
tCK
DQS write postamble
tWPST
tDQSS
0.4
0.6
0.25
0.4
0.6
0.25
tCK
tCK
tCK
Positive DQS latching edge to associated clock edge
Write command to first DQS latching transition
-0.25
-0.25
WL-TDQSS
WL+TDQSS
WL-TDQSS
WL+TDQSS
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
26
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
AC TIMING PARAMETERS (continued)
-55°C ≤ TA < +125°C; VCCQ = + 1.8V 0.1V, VCC = +1.8V 0.1V
533Mbs CL4
Symbol
400Mbs CL3
Unit
Parameter
Address and control input pulse width for each input
Min
0.6
Max
Min
Max
tIPW
tISa
0.6
tCK
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
ns
ns
µs
µs
ns
tCK
ps
tCK
ps
tCK
ps
500
250
500
375
2
600
350
600
475
Address and control input setup time
Address and control input hold time
tISb
tIHa
tIHb
CAS# to CAS# command delay
ACTIVE to ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b command
ACTIVE to READ or WRITE delay
Four Bank Activate period
ACTIVE to PRECHARGE command
Internal READ to precharge command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal WRITE to READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK, CK# uncertainty
REFRESH to Active or Refresh to Refresh command interval
Average periodic refresh interval (commercial)
Average periodic refresh interval (industrial)
Exit self refresh to non-READ command
Exit self refresh to READ
tCCD
tRC
2
55
55
10
15
tRRD
tRCD
tFAW
tRAS
tRTP
tWR
10
15
50
40
7.5
15
tWR + tRP
7.5
15
50
40
70,000
70,000
7.5
15
tWR + tRP
10
15
tDAL
tWTR
tRP
tRPA
tMRD
tDELAY
tRFC
tREFI
tREFIIT
tXSNR
tXSRD
tlSXR
tAOND
tACN
tAOFD
tRP + tCK
2
tIS +tIH + tCK
127.5
tRP + tCK
2
tIS +tIH + tCK
127.5
70,000
7.8
3.9
70,000
7.8
3.9
tRPC(MIN) + 10
tRFC(MIN) + 10
200
tIS
2
tAC(MIN)
2.5
tAC(MIN)
200
tIS
Exit self refresh timing reference
ODT tum-on delay
ODT turn-on
ODT turn-off delay
ODT tum-off
2
2
2
tAC(MAX) + 1000
2.5
tAC(MAX) + 600
tAC(MIN)
2.5
tAC(MAX) + 1000
2.5
t
tAC(MIN)
tAC(MAX) + 600
AOF
tAC(MIN)
+
2 x tCK
tAC(MAX) + 1000
2 x tCK
tAC(MAX) + 1000
+
tAC(MIN)
+
2 x tCK
tAC(MAX) + 1000
2 x tCK
tAC(MAX) + 1000
+
ODT tum-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
ps
ps
2000
2000
tAC(MIN)
2000
+
+
tAC(MIN)
2000
+
+
tAOFPD
ODT to power-down entry latency
ODT power-down exit latency
ODT enable from MRS command
Exit active power-down to READ command, MR[bit12=0]
Exit active power-down to READ command, MR[bit12=1]
Exit precharge power-down to any non-READ command
CKE minimum high/low time
tANPD
tAXPD
tMOD
tXARD
tXARDS
tXP
3
8
12
2
6-AL
2
3
3
8
12
2
6-AL
2
3
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCKE
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
27
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
PACKAGE DIMENSION: 208 PLASTIC BALL GRID ARRAY (PBGA)
BOTTOM VIEW
208 x Ø 0.51 (0.020) NOM
11 10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
T
M
N
P
R
ꢀ
U
V
W
1.0 (0.039)NOM
0.44
(0.017)
NOM
10.0 (0.394) NOM
17.15 (0.675) MAX
3.20 (0.126) MAX
All linear dimensions are millimeters and parenthetically in inches
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
28
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
ORDERING INFORMATION
W 3H 64M 72 E - XXX SB X
WHITE ELECTRONIC DESIGNS CORP.
DDR2 SDRAM
CONFIGURATION, 64M x 72
1.8V Power Supply
DATA RATE (Mbs)
400 = 400Mbs
533 = 533Mbs
667 = 667Mbs
Blank = No data rate specified for ES product(1)
PACKAGE:
ES = Non Qualified Product(1)
SB = 208 Plastic Ball Grid Array (PBGA)
DEVICE GRADE:
M = Military
-55°C to +125°C
-40°C to +85°C
I
= Industrial
C = Commercial 0°C to +70°C
Blank = No temperature specified for ES product(1)
Note 1: W3H64M72E-ESSB is the only available product until completion of qualification.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
29
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3H64M72E-XSBX
White Electronic Designs
ADVANCED*
Document Title
64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
Revision History
Rev #
History
Release Date Status
Rev 0
Rev 1
Initial Release
December 2005
March 2006
Advanced
Advanced
Changes (All pages)
1.1 Add additional technical data
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 1
30
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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