W3HG128M72AEF534F1SBG [WEDC]
DDR DRAM Module, 256MX4, CMOS, ROHS COMPLIANT, FBDIMM-240;
| 型号： | W3HG128M72AEF534F1SBG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | DDR DRAM Module, 256MX4, CMOS, ROHS COMPLIANT, FBDIMM-240 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总17页 (文件大小：256K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3HG128M72AEF-Fx
White Electronic Designs
ADVANCED*
1GB – 128Mx72 DDR2 SDRAM FBDIMM, ECC
FEATURES
VCC = VCCQ = +1.8V for DDR2 SDRAM
240-pin DDR2 fully buffered, dual in-line memory
module (FBDIMM) with ECC to detect and report
channel errors to the host memory controller.
VREF = 0.9V SDRAM C/A termination
VCC = 1.5V for advanced memory buffer (AMB)
Fast DDR2 DRAM data transfer rates: PC2-6400*,
PC2-5300, and PC2-4300
Serial Presence Detect (SPD) with EEPROM
Gold edge contacts
Dual rank
3.2 Gb/s and 4.0 Gb link transfer rates
High speed differential point-to-point link between
host memory controller and the AMB using serial,
dual-simplex bit lanes
RoHS
• 10-pair southbound (data path to FBDIMM)
• 14-pair northbound (data path to FBDIMM)
DESCRIPTION
The W3HG128M72AEF is a 128Mx72 fully buffered 240-
pin Double Data Rate 2 SDRAM memory module based
on 512Mb DDR2 SDRAM components. The module
consists of eighteen 128Mx4, in FBGA package and a
AMB mounted on a 240 pin FR4 substrate.
Fault tolerant; can work around a bad bit lane in
each direction
High density scaling with up to 8 dual-rank modules
(288 DDR2 SDRAM devices) per channel
SMBus interface to AMB for configuration register
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
access.
In-band and out-bank command access
Deterministic protocol
NOTE: Consult factory for availability of:
• Vendor source control options
• Enables memory controller to optimize DRAM
access for maximum performance
• Delivers precise control and repeatable memory
behavior
Automatic DDR2 SDRAM bus and channel
calibration
Transmitter de-emphasis to reduce ISI
MBIST and IBIST test functions
Transparent mode for DDR2 SDRAM test support
PERFORMANCE PARAMETERS
Speed Grade
Module Bandwidth
PC2-5300
Peak Channel Throughput
8.0 GB/s
Link Transfer Rate
4.0 GT/s
Latency (CL-tRCD-tRP)
665
534
5-5-5
4-4-4
PC2-4200
6.4 GB/s
3.2 GT/s
* Consult factory for availability
Note: JEDEC has not yet adopted a final FBDIMM standard
September 2007
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AEF-Fx
White Electronic Designs
ADVANCED
PIN ASSIGNMENT – 240 PIN FBDIMM
PIN NAMES
PIN
1
SYMBOL
PIN
SYMBOL
PN9#
VSS
PIN
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
SYMBOL
VDD
VDD
VDD
VSS
PIN
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
SYMBOL
SN9#
VSS
Symbol
SCK
SCK#
Descriptions
VDD
61
System Clock Input, positive line
System Clock Input, negative line
Primary Northbound Data, positive lines
Primary Northbound Data, negative lines
Primary Southbound Data, positive lines
Primary Southbound Data, negative lines
Secondary Northbound Data, positive lines
Secondary Northbound Data, negative lines
Secondary Southbound Data, positive lines
Secondary Southbound Data, negative lines
Serial Presence Detect (SPD) Clock Input
SPD Data Input/Output
2
VDD
62
3
VDD
63
PN10
PN10#
VSS
SN10
SN10#
VSS
PN0-PN13
PN0#-PN13#
PS0-PS9
PS0#-PS9#
SN0-SN13
SN0#-SN13#
SS0-SS9
SS0#-SS9#
SCL
4
VSS
64
5
VDD
65
VDD
VDD
VDD
VSS
6
VDD
66
PN11
PN11#
VSS
SN11
SN11#
VSS
7
VDD
67
8
VSS
68
9
VCC
69
VSS
VCC
VCC
VSS
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VCC
70
PS0
PS0#
VSS
SS0
SS0#
VSS
VSS
71
VCC
72
VCC
VCC
VSS
VCC
73
PS1
PS1#
VSS
SS1
SS1#
VSS
SDA
VSS
74
SPD Address Inputs, also used to select the
FBDIMM number in the AMB
SA0-SA2
VTT
75
VTT
VID1
RESET#
VSS
RFU2
RFU2
VSS
76
PS2
PS2#
VSS
VID0
SS2
SS2#
VSS
Voltage ID: These pins must be
unconnected for DDR2-based FBDIMMs.
VID0 is VDD value: OPEN=1.8V,
GND=1.5V;VID1 is VCC value: OPEN=1.5V,
GND=1.2V
AMB reset signal
Reserved for Future Use
AMB Core Power and AMB Channel
Interface Power (1.5V)
DRAM Power and AMB DRAM I/O Power
(1.8V)
77
137 DNU/M_Test 197
78
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
VSS
RFU2
RFU2
VSS
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
VID0-VID1
79
PS3
PS3#
VSS
SS3
SS3#
VSS
80
81
RESET#
RFU
PN0
PN0#
VSS
82
PS4
PS4#
VSS
SN0
SN0#
VSS
SS4
83
SS4#
VSS
84
VCC
VDD
VTT
PN1
PN1#
VSS
85
VSS
SN1
SN1#
VSS
VSS
86
RFU1
RFU1
VSS
RFU1
RFU1
VSS
87
DRAM Address/Command/Clock
Termination Power (VDD/2
SPD Power
Ground
PN2
PN2#
VSS
88
SN2
SN2#
VSS
89
VSS
VSS
)
90
PS9
PS9#
VSS
SS9
SS9#
VSS
VCCSPD
PN3
PN3#
VSS
91
SN3
SN3#
VSS
VSS
DNU/M_TEST
92
Do Not Use
93
PS5
PS5#
VSS
SS5
SS5#
VSS
Note:
PN4
PN4#
VSS
94
SN4
SN4#
VSS
1. These pin positions are reserved for forwarded clocks to be used in
future module implemenations
2. These pin positions are reserved for future architechture flexibility.
3. The following signals are CRC bits and thus appear out of the
normal sequence: PN12/PN12#, SN12/SN12#, PN13/PN13#,
PS9/PS9#, SS9/SS9#.
95
96
PS6
PS6#
VSS
SS6
SS6#
VSS
PN5
PN5#
VSS
97
SN5
SN5#
VSS
98
99
PS7
PS7#
VSS
SS7
SS7#
VSS
PN13
PN13#
VSS
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
SN13
SN13#
VSS
4. RFU = Reserved Future Use.
PS8
PS8#
VSS
RFU2
RFU2
VSS
SS8
SS8#
VSS
RFU2
RFU2
VSS
VSS
VSS
RFU
RFU
VSS
RFU1
RFU1
VSS
VSS
VSS
PN12
PN12#
VSS
VDD
SN12
SN12#
VSS
SCK
SCK#
VSS
VDD
VSS
PN6
PN6#
VSS
VDD
SN6
SN6#
VSS
VDD
VDD
VDD
VDD
VDD
PN7
PN7#
VSS
VSS
SN7
SN7#
VSS
VSS
VDD
VDD
VDD
VDD
PN8
PN8#
VSS
VTT
SN8
SN8#
VSS
VTT
SA2
SDA
SCL
VCCSPD
SA0
SA1
PN9
SN9
September 2007
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AEF-Fx
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
VSS
CS0#
CS1#
DQS0
DQS9
DQS9
DQS0#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ0
DQ4
I/O 0
I/O 0
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
DQS1
DQS10
DQS1#
DQS10#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
DQ10
DQ11
DQS2
DQS2#
DQS11
DQS11#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQ16
DQ20
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
DQ21
DQ22
DQ23
DQS3
DQS12
DQS3#
DQS12#
DM
DM
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
DQS4
DQS13
DQS4#
DQS13#
DM
DM
DQ32
DQ36
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
DQ37
DQ38
DQ39
DQS5
DQS14
DQS5#
DQS14#
DM
DM
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
DQS6
DQS15
DQS6#
DQS15#
DM
DM
DQ48
DQ52
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
DQ53
DQ54
DQ55
DQS7
DQS16
DQS7#
DQS16#
DM
DM
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
DQS8
DQS17
DQS8#
DQS17#
DM
DM
CB0
CB4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
CB5
CB6
CB7
Terminators
VTT
PN0-PN13
PN0#-PN13#
PS0-PS9
SN0-SN13
SN0#-SN13#
SS0-SS9
VCCSPD
Serial PD, AMB
Out to Ctrl
In from adj. FBDIMM
Out to adj. FBDIMM
VCC
VDD
AMB
In from Ctrl
PS0#-PS9#
SS0#-SS9#
DDR2 SDRAMs
DQ0-DQ63
DQS0-DQS17
DQS0#-DQS17#
CB0 -CB7
A0-A15
Data Input/Output
A
M
B
VREF
VSS
signals to DDR2 Channel
RAS#, CAS#
WE#, ODT0
CS0#, CS1#
CKE0, CKE1
DDR2 SDRAMs
Command, Address and
Clock signals to DDR2 Channel
DDR2 SDRAMs
Serial PD, AMB
SCL
SDA
SA0-SA2
CK0, CK0#
CK1, CK1#
Command, address and clock line terminations:
22
30
39
RAS#, CAS#, A0–A15,
ODT0, WE#, BA0–BA2
VTT
VTT
VTT
SCL
Serial PD
WP A0 A1 A2
SCK, SCK#
RESET#
SDA
CK0, CK0#, CK1, CK1#,
SA0 SA1 SA2
CS0, CS1#,
CKE0, CKE1
September 2007
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AEF-Fx
White Electronic Designs
ADVANCED*
GENERAL DESCRIPTION
in the center of each FBDIMM, acts as a repeater
and buffer for all signals and commands exchanged
between the host controller and the DDR2 SDRAM
devices, including data input and output. The AMB
communicates with the host controller and adjacent
FBDIMMs on a system board using an industry-
standard, high-speed, differential, point-to-point,
interface at 1.5V.
WEDC FBDIMM is a high-bandwidth, large-capacity-
channel solution that has narrow host interface.
FBDIMMs used DDR2 SDRAM devices isolated from
the channel behind a buffer on the FBDIMM. Memory
device capacity remains high and total memory capacity
scales with DDR2 SDRAM bit density.
As shown in Figure 1, the FBDIMM channel provides a
communication path from a host controller to an array of
DDR2 SDRAM devices, with the DDR2 SDRAM devices
buffered behind an AMB device. The physical isolation
of the DDR2 SDRAM devices from the channel enables
the flexibility to enhance the communication path to
significantly increase the reliability and availability of the
memory subsystem.
The AMB also allows buffering of memory traffic to
support large memory capacities. All memory control for
the DDR2 SDRAM devices resides in the host, including
memory request initiation, timing, refresh, scrubbing,
sparing, configuration access, and power management.
The AMB interface is responsible for handling channel
and memory requests to and from the local FBDIMM
and for forwarding requests to other FBDIMMs on the
memory channel.
WEDC FBDIMM features a novel architecture, including
the AMB that isolates the DDR2 SDRAM devices from
the channel. This single-chip AMB component, located
FIGURE 1: FBDIMM Solution Block Diagram
DDR2 connector with unique key
Commodity
DDR2 SDRAM
Devices
DDR2
DDR2
DDR2
DDR2
Component
Component
Component
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
Up to 8 modules
10
AMB
AMB
AMB
AMB
•
• •
DDR2
DDR2
DDR2
DDR2
Memory
Controller
14
Component
Component
Component
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
SMBus
DDR2
Component
DDR2
Component
DDR2
Component
DDR2
Component
CLK
Source
SMbus access
to buffer registers
Common clock source
September 2007
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AEF-Fx
White Electronic Designs
ADVANCED*
FUNCTIONAL DESCRIPTION
ADVANCED MEMORY BUFFER (AMB)
northbound frames, servicing requests directed to a
specific FBDIMM's AMB, as defined in the protocol
chapter of the specification, and merging the return
data into the northbound frames.
The AMB reference design complies with the "FBDIMM
Architecture and Protocol Specification" (JEDEC
standards, pending). It is expected that there will be
multiple vendors for the AMB which will offer at least
the minimum functionally as set forth in the industry
specification. To achieve optimal operation and
compatibility with DDR2 SDRAM device and host/
controller offerings, each vendor's AMB will have a
unique set of personality bytes contained in the SPD for
setting up and fine tuning their device.
•
Initialize northbound frames if the FBDIMM's AMB
is the last, southern-most on the channel, initialize
northbound frames.
•
•
Detect errors on the channel and report them to the
host memory controller
The FBDIMM specification defines a number of options
to support the requirements of different applications.
The capabilities of the AMB are communicated to the
host during the initialization process in the TS2 training
pattern and in bits readable in the features register in
the AMB.
Support the FBDIMM configuration register set as
defined in the FBDIMM AMB specification register
chapter of the specification
•
Act as a DRAM memory buffer for all read, write,
and configuration accesses addressed to a specific
FBDIMM's AMB
The AMB is responsible for handling FBDIMM channel
and memory requests to and from the local FBDIMM
and for forwarding requests to other FBDIMMs on
the channel. A complete and detailed description of
the AMB is contained in the proposed FBDIMM AMB
Specification. The AMB is a memory interface that
connects an array of DDR2 SDRAM devices to the
FBDIMM channel. The AMB is a slave device on
the channel responding to channel commands and
forwarding channel commands to other AMB devices.
•
•
Provide a read and write buffer FIFO
Supports an SMBus protocol interface for access to
the AMB configuration registers
•
•
•
•
Provide features to support MEMBIST and IBIST
test functions
Provide a register interface for the thermal sensor
and status indicator
All memory control for the DDR2 SDRAM resides in the
host, including memory request initiation, timing, refresh,
scrubbing, sparing, configuration access, and power-
management.
Function as a repeater to extend the maximum
length of FBDIMM Links
Reconfigures FBDIMM inputs from differential high-
speed link receivers to two single-ended, low-speed
receivers (~200 MHz). These inputs directly control
DDR2 command/address and input data that is
replicated to all DDR2 SDRAMs devices.
The AMB is expected to perform the following functions:
•
Support channel initialization procedures as
defined in the initialization chapter of the FBDIMM
Architecture and Protocol Specification to align the
clocks and the frame boundaries and verify channel
connectivity
•
Bypass high-speed parallel serial circuitry and
provide test results back to the tester, using low-
speed FBDIMM outputs
•
Support the forwarding of southbound and
September 2007
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AEF-Fx
White Electronic Designs
ADVANCED*
AMB INTERFACE
The northbound input link is 14 lanes wide. It carries
read return data or status information from one FBDIMM
to the next in the host direction and multiplexes in
any internally generated READ return data or status
information.
Figure 2: The AMB Interface Block Diagram illustrates
the AMB and all of its interfaces. They consist of two
FBDIMM links, one DDR2 channel and an SMBus
interface. Each FBDIMM link connects the AMB to a
host memory controller or an adjacent FBDIMM. The
DDR2 channel supports direct connection to the DDR2
SDRAM on an FBDIMM.
Data and commands sent to the DDR2 SDRAM devices
travel southbound on 10 primary differential signal
line pairs. Data and status information received from
the DDR2 SDRAM devices travel northbound on 14
primary differential pairs. Data and commands sent to
the adjacent FBDIMM are repeated and travel further
southbound on 10 secondary differential pairs. Data
and status information received from the upstream
adjacent FBDIMM travel further northbound on 14
secondary differential parts.
The FBDIMM channel uses a daisy-chain topology to
proved expansion from a single FBDIMM per channel
to up to eight FBDIMMs per channel. The host sends
data on the southbound link to the first FBDIMM, where
it is received and redriven to the second FBDIMM. On
the southbound data path, each FBDIMM receives the
data and redrives the data to the next FBDIMM, until the
last FBDIMM receives the data. The last FBDIMM in the
chain initiates the transmission of northbound data in
the direction of the host. On the northbound data path,
each FBDIMM receives the data and redrives the data
to the next FBDIMM until the host is reached.
DDR2 CHANNEL
The AMB DDR2 channel on the advanced memory
buffer supports direct connection to DDR2 SDRAM
devices. The DDR2 channel supports two ranks of eight
banks with 16 row/column-request, 64 data, and eight
check-bit signals. There are two copies of address
and command signals to support FBDIMM routing and
electrical requirements. Four transfer burst are driven
on the data and check-bit lines at 800 MHz.
FIGURE 2: AMB Interface Block Diagram
MEMORY INTERFACE
Primary or
Secondary direction or to
(optional) next FBDIMM
Host Direction
Propagation delays can differ between read data/check-
bit strobe lanes on a given channel. Each strobe
can be calibrated by hardware state machines using
WRITE/READ trial and error. Hardware aligns the
read data and check-bits to a single core clock. The
AMB provides four copies of the command clock phase
reference (CLK[3:0]) and write data/check-bit strobes
(DQS) for each DDR2 SDRAM device nibble.
NB FBD
Out Link
NB FBD
InLink
AMB
SB FBD
InLink
SB FBD
Out Link
SMBus
SMBus SLAVE INTERFACE
HIGH-SPEED, DIFFERENTIAL, POINT-
TO-POINT LINK (AT 1.5V) INTERFACES
The AMB supports a SMBus interface allows system
access to configuration registers independent of the
FBDIMM link. The AMB will never be a master on
the SMBus, only a slave. Serial SMBus data transfer
is supported at 100KHz. SMBus access to the AMB
may be a requirement to boot and to set link strength,
frequency and other parameters needed to ensure
robust configurations. It is also required for diagnostic
The AMB supports one FBDIMM channel consisting
of two bidirectional link interfaces using high-speed
differential point-to-point electrical signaling. The
southbound input link is 10 lanes wide. It carries
commands and write data from the host memory
controller, or the adjacent FBDIMM in the host direction,
to the next FBDIMM in the chain.
September 2007
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AEF-Fx
White Electronic Designs
ADVANCED*
DDR2 SDRAM command clock because of the fixed
6:1 ratio of the FBDIMM channel clock to the DDR2
SDRAM command clock. Therefore, the northbound
data connection will exhibit the same peak theoretical
throughput as a single DDR2 SDRAM channel. For
example, when using DDR2 533 componente, the peak
theoretical bandwidth of the northbound data connection
is 4.267 GB/sec.
support when the high speed link is down. The SMBus
address straps located on the FBDIMM connector are
used to set the unique ID.
CHANNEL LATENCY
FBDIMM channel latency is measured from the time
a read request is driven on the FBDIMM channel pins
to the time when the first 16 bytes (2nd chunk) of read
completion data is sampled by the memory controller.
Write data is transferred on the southbound command
and data connection, via Command + Wdata frames; 72
bits of data are transferred per frame. Two Command
+ Wdata frames match the 18-byte data transfer of
an ECC DDR2 SDRAM in a single DDR2 SDRAM
command clock.
When not using variable READ latency, the latency
for a specific FBDIMM on a channel is always equal
to the latency for any other FBDIMM on that channel.
However, the latency for each FBDIMM in a specific
configuration with some number of FBDIMMs installed
may not be equal to the latency for each FBDIMM in a
configuration with some different number of FBDIMMs
installed. As more FBDIMMs are added to the channel,
additional latency is required to read from each FBDIMM
on the channel.
A DDR2 SDRAM burst of eight transfers from a single
channel, or a burst of four from two lock-step channels,
provides a total of 72 bytes of data (64 bytes plus 8
bytes ECC). When the FBDIMM frame rate matches
the DDR2 SDRAM command clock, the southbound
command and data connection will exhibit one half the
peak theoretical throughput of a single DDR2 SDRAM
channel. For example, when using DDR2-533 SDRAMs,
the peak theoretical bandwidth of the southbound
command and data connection is 2.133 GB/sec.
Because the channel is based on point-to-point
interconnection of buffer components between
FBDIMMs, memory requests are required to travel
through N-1 buffers before reaching the Nth buffer. The
result is that a four-FBDIMM channel configuration will
have greater idle READ latency compared to a one
FBDIMM channel configuration.
The total peak-theoretical throughput for a single
FBDIMM channel is defined as the sum of the
peak-theoretical throughput of the northbound data
connection and the southbound command and data
connection. When the FBDIMM frame rate matches the
DDR2 SDRAM command clock, it equals 1.5 times the
peak-theoretical throughput of a single DDR2 SDRAM
channel. For example, when using DDR2-533 SDRAMs,
the peak theoretical throughput of a DDR2-533 channel
would be 4.267 GB/sec, while the peak theoretical
throughput of an FBDIMM-533 channel would be 6.4
GB/sec.
The variable READ latency capability can be used to
reduce latency for FBDIMMs closer to the host. The
idle latencies listed in this section are representative of
what might be achieved in typical AMB designs. Actual
implementations with latencies less than the values
listed will have higher application performance and vice
versa.
PEAK THEORETICAL THROUGHPUT
An FBDIMM channel transfers READ completion data
on the northbound data connection; 144 bits of data
are transferred for every northbound data frame. This
matches the 18-byte data transfer of an ECC DDR2
SDRAM device in a single DDR2 SDRAM command
clock. A DDR2 SDRAM device burst of eight from a
single channel, or burst of four from two lock-step
channels, provides a total of 72 bytes of data (64 bytes
plus 8 bytes ECC). The AMB frame rate matches the
September 2007
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ADVANCED
ABSOLUTE MAXIMUM RATINGS
All voltages referenced to VSS
Symbol
VIN, VOUT
VCC
Parameter
Voltage on any pin relative to VSS
Voltage on VCC pin relative to VSS
Voltage VCC pin relative to VSS
Voltage on VTT pin relative to VSS
Storage temperature
Min
-0.3
-0.3
-0.5
-0.5
-55
Max
1.75
1.75
2.3
Units
V
Notes
V
VDD
V
VTT
2.3
V
TSTG
100
95
°C
°C
°C
DDR2 SDRAM device operating temperature (Ambient)
AMB device operating temperature (Ambient)
0
0
1, 2
TCASE
110
Stresses greater than those listed in absolute maximum rating table may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
NOTES:
1. TCASE is specified at 95°C only when using 2X refresh timing (tREFI = 7.8μs at or below 85°C; tREFI = 3.9μs above 85°C);.DDR2 SDRAM component datasheet, though the
FBDIMM does not have an IT option.
2. See applicable DDR2 SDRAM component datasheet for tREFI and extended mode register setting. The tREFIIT parameter is used to specify the doubled refresh interval
neceassary to sustain 95°C operation; however, the FBDIMM does not have an IT option.
INPUT DC VOLTAGE AND OPERATING CONDITIONS
Symbol Parameter
Min
1.455
1.7
Nom
1.50
Max
1.575
1.9
Units
V
Notes
VCC
VDD
VTT
AMB supply voltage
DDR2 SDRAM supply voltage
Termination voltage
1.8
V
0.48 x VDD
3.0
0.50 x VDD
3.3
0.52 x VDD
3.6
V
VDDSPD SPD supply voltage
V
VIH(DC)
VIL(DC)
VIH(DC)
VIL(DC)
IL
SPD Input HIGH (logic 1) voltage
2.1
VDDSPD
0.8
V
1
1
2
1
2
3
SPD Input LOW (logic 0) voltage
RESET Input HIGH (logic 1) voltage
RESET Input LOW (logic 0) voltage
Leakage Current (RESET)
V
1.0
V
0.5
90
5
V
-90
-5
μA
μA
IL
Leakage Current (link)
NOTES:
1. Applies for SMB and SPD bus signals.
2. Applies for AMB CMOS signal RESET#.
3. For all other AMB related DC parameters, please refer to the high-speed differential link interface specification.
September 2007
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ADVANCED
Timing Parameters
Parameter
Symbol
tEl Propagate
Min
Typical
Max
4
Unit
CK
Notes
El assertion pass-through timing
El de assertion pass-through timing
El assertion duration
tEID
tEI
Bitlock
CK
2
1, 2
3
100
CK
FBD command to DDR2 clock out that latches command
FBD command to DDR2 WRITE
DDR2 READ to FBD (last FBDIMM)
Resample pass-through time
8.1
TBD
5.0
ns
ns
ns
4
1.075
2.075
ns
Resynch pass-through time
ns
Bitlock interval
tBitlock
tFramelock
119
154
frames
frames
1
1
Framelock interval
Note: 1. Defined in FBDIMM architecture and protocol specification.
2. Clocks defined as core clocks - 2x SCK input
3. For DDR2-667 (PC2-5300), this is measured from the beginning of the frame at the southbound input to the DDR2 clock output that latches the first command of a frame
to the DDR2 SDRAM devices
4. For DDR2-667 (PC2-5300), this is measured from the latest DQS input to the AMB to the start of the matching data frame at the northbound FBDIMM outputs.
AMB IDD SPECIFICATIONS AND CONDITIONS
Symbol
Condition
806
665
534
Units
@1.5v
@1.8v
2.6
2.2
A
TBD
Idle Current, single or last DIMM, LO state, idle (0 BW), Primary channel enabled,
Secondary Channel disabled , CKE high. Command and address lines stable. DRAM
clock active
Idd_Idle_0
0.9
3.4
0.9
3.0
A
A
TBD
TBD
@1.5v
@1.8v
Idle Current, first DIMM, LO state, idle (0 BW), Primary and Secondary channels
enabled CKE high, Command and address lines stable. DRAM clock active.
Idd_Idle_1
0.9
0.9
A
TBD
@1.5v
@1.8v
@1.5v
3.9
1.7
3.7
3.4
1.7
3.2
A
A
A
TBD
TBD
TBD
Active Power, LO state. 50% DRAM BW, 67% read, 33% write. Primary and Secondary
channels enabled. DRAM clock active, CKE high.
Idd_Active_1
Active Power, LO state. 50% DRAM BW, 67% read, 33% write. Primary and Secondary
channels enabled. DRAM clock active, CKE high.
Idd_Active_2
Idd_Training
@1.8v
@1.5v
@1.8v
0.9
4.0
0.9
0.9
3.5
0.9
A
A
A
TBD
TBD
Training, Primary and Secondary channels enabled. 100% toggle on all channel lanes
DRAMs idle. 0BW. CKE high, Command and address lines stable. DRAM clock active.
TBD
September 2007
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ADVANCED
VTT CURRENTS
Parameter
Symbol
Typ
500
500
Max
700
700
Unit
mA
mA
Idle current, DDR2 SDRAM device power down
Active power, 50% DDR2 BW
ITT1
ITT2
REFERENCE CLOCK INPUT SPECIFICATIONS
Values
Parameter
Symbol
Unit
Notes
Min
133.33
175
Max
200
700
850
Reference clock frequency
Rise time, fall time
fSCK
TSCK-RISE, TSCK-FALL
VSCK-HIGH
VSCK-LOW
MHz
ps
1, 2
3
Voltage high
600
mV
mV
mV
Voltage low
-150
250
Absolute crossing point
Relative crossing point
Percent mismatch between rise and fall times
Duty cycle of reference clock
Clock leakage current
VCROSS-ABS
VCROSS-REL
TSCK-RISE-FALL-MATCH
TSCK-DUTYCYCLE
Il-CK
550
4
calculated
-
calculated
4, 5
10
60
10
2
%
%
40
-10
μA
pF
6, 7
7
Clock input capacitance
Clock input capacitance delta
Transport delay
Cl-CK
0.5
Cl_CK (D)
-0.25
0.25
5
pF
8
T1
ns
9, 10
11
Phase jitter sample size
Reference clock jitter, filtered
Reference clock deterministic jitter
NSAMPLE
TREF-JITTER
TREF-DJ
1016
Periods
ps
40
12, 13
TBD
ps
NOTES:
10. The net transport delay is the difference in time of flight between
associated data and clock paths. The data path is defined from
the reference clock source, through the TX , to data arrival at the
data sampling point in the RX. The clock path is defined from the
reference clock source to clock arrival at the sampling point. The
path delays are caused by copper trace routes, on-chip routing, on-
chip buffering, etc. They include the time-of-flight of interpolators or
other clock adjustment mechanisms. They do not include the phase
delays caused by finite PLL loop bandwidth because these delays are
modeled by the PLL transfer functions.
1. 133 MHz for PC2-4200 and 166MHZ for PC2-5300
2. Measured with SSC disabled.
3. Measured differentially through the range of 0.175V to 0.525V.
4. The crossing point must meet the absolute and relative crossing point
specification simultaneously.
5. VCROSS_REL_(MIN) and VCROSS_REL_(MAX) are derived using the following
calculations: Min = 0.5 (Vhavg -0.710) + 0.250; and Max = 0.5 (Vhavg - 0.710) + 0.550, where
Vhavg is the average of VSCK-HIGHM.
6. Measured with a single-ended input voltage of 1V.
7. Applies to reference clocks SCK and SCK#.
11. Direct measurement of phase jitter records over 1016 periods is
impractical. It is expected that the jitter will be measured over a
smaller, yet statistically significant, sample size and total jitter at 1016
samples extrapolated from an estimated of the sigma of the random
jitter components.
8. Difference between SCK and SCK# input.
9. T1 = |Tdatapath - Tclockpath| (excluding PLL loop delays). This
parameter is not a direct clock output parameter but it indirectly
determines the clock output parameter TREF-JITTER
.
12. Measured with SSC enabled on reference clock generator.
13. As measured after the phase jitter filter. This number is separate
from the receiver jitter budget that is defined by the TRXTotal -Min
parameters.
September 2007
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ADVANCED
DIFFERENTIAL TRANSMITTER OUTPUT SPECIFICATIONS
Values
Parameter
Symbol
Units
Comments
Min
900
800
520
Max
Differential peak-to-peak output voltage for large voltage swing
Differential peak-to-peak output voltage for regular voltage swing
Differential peak-to-peak output voltage for small voltage swing
DC common code output voltage for large voltage swing
DC common code output voltage for small voltage swing
De-emphasized differential output voltage ratio for -3.5 dB de-emphasis
De-emphasized differential output voltage ratio for -6.0 dB de-emphasis
AC peak-to-peak common mode output voltage for large swing
AC peak-to-peak common mode output voltage for regular swing
AC peak-to-peak common mode output voltage for small swing
Maximum single-ended voltage in EI condition DC + AC
Maximum single-ended voltage in EI condition DC + AC
Maximum peak-to-peak differential voltage in EI condition
Single-ended voltage (w.r.t. VSS) ON D+/D-
V
TX-DIFF p-p_L
1,300
mV
mV
mV
mV
mV
dB
dB
mV
mV
mV
mV
mV
mV
mV
Ul
EQ 1, Note 1
EQ 1, Note 1
EQ 1, Note 1
EQ 2, Note 1
EQ 2, Note 1, 2
1, 3, 4
V
TX-DIFF p-p_R
VTX-DIFFp-p_S
VTX-CM_L
375
280
-4.0
-7.0
90
VTX-CM_S
135
-3.0
-5.0
VTX-CM-3.5-Ratio
VTX-CM-6.0-Ratio
VTX-CM-AC p-p-L
1, 3, 4
EQ3, Note 1, 5
EQ3, Note 1, 5
EQ3, Note 1, 5
6
V
TX-CM-AC p-p-R
80
VTX-CM-AC p-p-S
VTX-IDLE-SE-SE
VTX-IDLE-SE-DC
VTX-DIFF p-p
VTX-SE
70
50
20
6
40
-75
0.7
750
1, 7
1, 8
Minimum TX eye width, 3.2 and 4.0 Gb/s
TTX-EYE-MIN
TTX-EYE-MIN 4.8
TTX-DJ-DD
Minimum TX eye width 4.8 Gb/s
TBD
Ul
1, 8
Maximum TX deterministic jitter, 3.2 and 4.8 Gb/s
Maximum TX eye width 4.8 Gb/s
0.2
Ul
1, 8, 9
1, 8, 9
10
TTX-DJ-DD-4.8
TTX-PULSE
TBD
Ul
Instantaneous pulse width
0.85
30
Ul
20-80% voltage,
Note 1
Differential TX outout rise/fall time
Mismatch between rise and fall times
Differential return loss
TTX-RISE TTX-FALL
TTX-RF-MISMATCH
RLTX-DIFF
90
20
ps
ps
dB
1GHz - 2.4GHz
Note 11
8
1GHz - 2.4GHz
Note 11
Common mode return loss
RLTX-CM
RTX
6
dB
Transmitter termination impender
41
55
4
Ω
12
EQ; 4 Boundaries
are applied
separately to high
and low output
voltage states
D+/D- TX Impedance difference
RTX-MATCH -DC
%
Lane-to lane skew at Tx
Lane-to lane skew at TX
LTX-SKEW 1
LTX-SKEW 2
100 + 3Ul
100 + 2Ul
ps
ps
13, 15
14, 15
September 2007
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ADVANCED
DIFFERENTIAL TRANSMITTER OUTPUT SPECIFICATIONS
Values
Parameter
Symbol
Units
Comments
Min
—
Max
240
120
—
Maximum TX Drift (resync mode)
Maximum TX Drift (resample mode only)
Bit Error Ratio
TTX-DRIFT-RESYNC
TTX-DRIFT-RESAMPLE
BER
ps
ps
—
16
16
17
—
10-12
NOTES:
10. Pulse width measure at 0V differential.
1. Specified at the package pins into a timing and voltage compliance
test load as shown in Figure 4-2 and in steps outlined in 4.1.2.1 of the
JEDEC specification. Common-mode measurements to be performed
using a 101010 pattern.
2. The transmitter designer should not artificially elevate the common
mode in order to meet this specification.
3. This is the ration of the VTX-DIFFp-p of the second and following bits
after a transition divided by the VTX-DIFFp-p of the first bit after a
transition.
11. One of the components that contribute to the deterioration of the
return loss is the ESB structure which needs to be carefully designed.
12. The termination small signal resistance; tolerance across voltages
from 100 mV to 400 mV shall not exceed +/- 5 W with regard to the
average of the values measured at 100 mV and 400 mV for that pin.
13. Lane to Lane skew at the Transmitter pins for an end component.
14. Lane to Lane skew at the Transmitter pins or an intermediate
component (assuming zero Lane to Lane skew at the Receiver pins
of the incoming PORT).
4. De-emphasis shall be disabled in the calibration state.
5. Includes all sources of AC common mode noise.
6. Sinlge-ended voltages below that value that are simultaneously
detected on D+ and D- are interpreted as the Electrical Idle condition.
7. The maximum value is specified to be at least (VTX-DIFFp-pL/4) +
(VTX-CM-ACp-p2).
15. This is a static skew. An FBDIMM component is not allowed to
change its lane to lane phase relationship after initialization.
16. Measured from the reference clock edge to the center of the output
eye. This specification must be met across specified voltage and
temperature ranges for a single component. Drift rate change is
significantly below the tracking capability of the receiver.
17. BER per differential lane.
8. This number does not include the effects of SSC or reference clock
jitter.
9. Defined as the expected maximum jitter for the given probability as
measured in the system (JJ), less the unbounded jitter
VTX-DIFFp-p = 2 x|VTX-D+ -VTX-D-
VTX-CM = DC(avg) of (|VTX-D+ +VTX-D-|/2)
VTX-CM-AC = ((Max|VTX-D+ +VTX-D-|)/2) - (Min |VTX-D++VTX-D-|)/2)
RTX-MATCH-DC = 2x ((|RTX-D+ -RTX-D-|)/(RTX-D++RTX-D-|))
|
(EQ 1)
(EQ 2)
(EQ 3)
(EQ 4)
September 2007
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ADVANCED
DIFFERENTIAL RECEIVER INPUT SPECIFICATIONS
Values
Parameter
Units
Comments
Symbol
Min
170
—
Max
TBD
75
Differential peak-to-peak input voltage for large voltage swing
Maximum single-ended voltage in EI condition
Maximum single-ended voltage in El condition (DC only)
Maximum peak-to-peak differential voltage in El condition
Sinlge-ended voltage (w.r.t. Vss on D+/D-
Single-pulse peak differential input voltage
Amplitude ratio between adjacent symbols
Maximum RX inherent timing error, 3.2 and 4.0 Gb/s
Maximum RX inherent deterministic timing error, 3.2 and 4.8 Gb/s
Single-pulse width as zero-voltage crossing
Single-pulse width at minimum-level crossing
Differential RX input rise/fall time
V
RX-DIFF p-p
mV
mV
mV
mV
mV
mV
—
EQ 5, Note 1
VRX-IDLE-SE
2, 3
VRX-IDLE-SE-DC
—
50
2, 3
V
RX-IDLE-DIFF p-p
VRX-SE
—
65
3
-300
85
900
—
4
VRX-DIFF-PULSE
VRX-DIFF-ADJ-RATIO
TRX-TJ-MAX
4, 5
—
TBD
0.4
TBD
0.3
TBD
—
4, 6
—
UI
4, 7, 8
TRX-TJ-MAX 4.8
VRX-DJ-DD
VRX-DJ-DD-4.8
TRX-PW-ZC
—
UI
4, 7, 8
—
UI
4, 7, 8, 9
—
UI
4, 7, 8, 9
0.55
UI
4, 5
Common mode of the input voltage
TRX-PW-ML
—
UI
0.2
50
4, 5
Differential RX outout rise/fall time
T
RX-RISE TRX-FALL
VRX-CM
RX-CM-H-ACp-p
VRX-CM-EH-RATOP
RLRX-DIFF
—
ps
20-80% voltage
Common mode of input voltage
mV
mV
120
—
400
270
45
—
—
55
4
EQ6, Note1, 10
AC peak-to-peak common mode of input voltage
Ratio of VRX-CM-ACp-p to minimum VRX-DIFFp-p
Differential return loss
V
EQ7, Note1
—
9
%
dB
dB
Ω
11
Meas. 0.1-2.4GHz, Note 12
Common mode return loss
RLRX-CM
6
Meas. 0.1-2.4GHz, Note 12
RX termination impedance
RRX
41
—
—
13
D+/D- RX Impedance difference
RRX-MATCH-DC
LRX-PCB-SKEW
%
EQ 8
Lane-to lane PCB skew at RX
6
UI
Lane-to-lane skew at the
receiver that must be
tolerated. Note 14
Minimum RX drift tolerance
Minim data tracking 3dB bandwidth
Electrical idle entry detect time
Electrical idle exit detect time
Bit Error Ratio
TRX-DRIFT
FTRK
400
0.2
—
—
—
ps
MHz
ns
15
16
17
—
TEI-ENTRY-DETECT
TEI-EXIT-DETECT
BER
60
—
30
10-12
ns
—
—
18
4.. Specific at the package pins into a timing and voltage compliance test
setup
5. The single-pulse mask provides sufficient symbol energy for reliable
RX reception. Each symbol must comply with both the single-pulse
mask and the cumulative eyemask .
6. The relative amplitude ratio limit between adjacent symbols prevents
excessive intersymbol interference in the RX. Each symbol must
comply with the peak amplitude ratio with regard to both the preceding
and subsequent symbols.
NOTES:
1. Specified at the package pins into a timing and voltage compliance
test setup. Note that signal levels at the pad will be lower than at the
pin.
2. Single-ended voltages below that value that are simultaneously
detected on D+ and D- are interpreted as the Electrical Idle condition.
Worst- case margins are determined for the case with transmitter
using small voltage swing.
3. Multiple lanes need to detect the El condition before the device can act
upon the El detection.
September 2007
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ADVANCED
7. This number does not include the effects of SSC or reference clock
jitter.
8. This number includes setup and hold of the RX sampling flop.
9. Defined as the dual-dirac deterministic timing error.
14. This number represents the lane-to-lane skew between TX and
RX pins and does not include the transmitter output skew from the
component driving the signal to the receiver. This is one component
of the end-to-end channel skew in the AMB specification.
15. Measured from the reference clock edge to the center of the input
eye. This specification must be met across specified voltage and
temperature ranges for a single component. Drift rate of change is
significantly below the tracking capability of the receiver.
16. This bandwidth number assumes the specified minimum data
transition density. Maximum jitter at 0.2 MHz is 0.05 UI.
17. The specified time includes the time required to forward the El entry
condition.
10. Allows for 15mV DC offset between transmit and receive devices.
11. The received differential signal must satisfy both this ratio as well as
the absolute maximum AC peak-to-peak common mode specification.
For example, if VRX-DIFFp-p is 200mV, the maximum AC peak-
to-peak common mode is the lesser of (200mV x 0.45=90mV) and
VRX-CM-AC-p-p.
12. One of the components that contribute to the deterioration of the
return loss is the ESD structure which needs to be carefully designed.
13. The termination small signal resistance; tolerance across voltages
from 100mV to 400mV shell not exceed +/- 5W with regard to the
average of the values measured at 100mV and at 400mV for that pin.
18. BER per differential lane.
VRX-DIFFp-p = 2 x|VRX-D+ -VRX-D-
VRX-CM = DC(avg) of (|VRX-D+ +VRX-D-|/(2)
VRX CD-AC = ((Max|VRX-D+ +VRX-D-|)/(2) - ((Min |VRX-D++VRX-D-|)/2)
RRX-MATCH-DC = 2x ((|RRX-D+ -RRX-D-|)/(|RR-D++RRX-D-|))
|
(EQ 5)
(EQ 6)
(EQ 7)
(EQ 8)
-
September 2007
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ADVANCED
ORDERING INFORMATION FOR F1 (FmHS) Full metal Heat Spreader
Part Number
Speed
CAS Latency
tRCD
6
tRP
6
Height*
W3HG128M72AEF806F1xxG**
W3HG128M72AEF665F1xxG
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
6
5
4
30.35 (1.20") NOM
30.35 (1.20") NOM
30.35 (1.20") NOM
5
5
W3HG128M72AEF534F1xxG
4
4
** Consult factory for availability
NOTES:
• G = RoHS Compliant
• Vendor specific part numbers are used to provide memory components for source control. The place holder for this is shown as a lower case “x” in the part numbers above
and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• For the AMB, a specific character is used to provide component source control. The place holder for this is shown as lower case "x" (next to the G) in the part number above.
PACKAGE DIMENSIONS FOR F1 (FmHS) Full metal Heat Spreader
FRONT VIEW WITH HEAT SPREADER
133.50 (5.256)
133.20 (5.244)
7.14 (0.281)
MAX
66.68 (2.63) TYP.
0.595 (.0234) R
1.45 (0.057)
TYP.
1.50 (0.059) R
(4X)
30.50 (1.201)
30.20 (1.189)
2.60 (0.102) D
(2X)
17.3 (0.681)
TYP.
9.50 (0.374)
TYP.
5.20 (0.205) TYP.
1.25 (0.0492) TYP.
PIN 1
0.75 (0.0295) R
3.90 (0.153)
TYP.
(X2)
1.00 (.039)
TYP.
0.80 (0.031)
TYP.
1.37 (0.054)
1.17 (0.0476)
74.68 (2.94)
TYP.
PIN 120
123.0 (4.843)
TYP.
BACK VIEW WITH HEAT SPREADER
24.95 (0.982)
TYP.
3.05 (0.120) TYP.
2.18 (0.086) TYP.
120° (2X)
PIN 121
PIN 240
5.0 (0.197) TYP.
67.0 (2.638)
TYP.
51.0 (2.008)
TYP.
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
September 2007
Rev. 3
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AEF-Fx
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
W 3 H G 128M 72 A E F x xxx Fx x x G
WEDC
MEMORY (DRAM)
TECHNOLOGY(DDR 2)
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH (x4)
CORE VOLTAGE (1.8V)
FULLY BUFFERED
PRODUCT REVISION
("BLANK" = Initial revision. For all other
characters please see NOTES 1 & 2)
SPEED (Mb/s)
PACKAGE 240 PIN (30mm)
(F1 = Fully metal Heat Spreader option)
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
(G = Qimonda)
(See NOTES2)
AMB CODES
(IDT = A)
(NEC = B)
(Qimonda = C)
(See NOTES2)
G = RoHS COMPLIANT
NOTE1: This character represents the general product revision that is used to control and record any changes in the AMB and
memory die revision, as well as any other design changes.
NOTE2: In order to obtain the most current revision, please contact the factory.
September 2007
Rev. 3
16
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AEF-Fx
White Electronic Designs
ADVANCED
Document Title
1GB – 128Mx72 DDR2 SDRAM FBDIMM
DRAM Options:
• SAMSUNG: C = DIE
• MICRON: D = DIE
• QIMONDA: F = DIE
AMB OPTION:
• IDT = REV. A5
• NEC = REV. K (B5+)
• QIMONDA: TBD
Revision History
Rev #
Rev 0
History
Release Date Status
Created
September 2006
Concept
Rev 1
1.0 Update to part number guide
September 2006
Concept
Rev 2
Rev 3
2.0 Corrected Package Spec
October 2006
Concept
2.1 Updated Part Numbering Guide
3.0 Update DC voltage and operating conditions
3.1 Updated DDR2 IDD specs
September 2007
Advanced
3.2 Moved from concept to advanced
September 2007
Rev. 3
17
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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