W3HG128M72AER403AD6GG [WEDC]
DDR DRAM Module, 128MX72, 0.6ns, CMOS, ROHS COMPLIANT, RDIMM-240;
| 型号： | W3HG128M72AER403AD6GG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | DDR DRAM Module, 128MX72, 0.6ns, CMOS, ROHS COMPLIANT, RDIMM-240 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总12页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3HG128M72AER-AD6
White Electronic Designs
1GB – 128Mx72 DDR2 SDRAM RDIMM, VLP, w/PLL
FEATURES
DESCRIPTION
Registered VLP (very low profile) 240-pin, dual in-
line memory module
The W3HG128M72AER is a 128Mx72 Double Data Rate
DDR2 SDRAM high density module. This memory module
consists of eighteen 128Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
VLP 240-pin RDIMM FR4 substrate.
Fast data transfer rates: PC2-6400*, PC2-5300,
PC2-4300 and PC2-3200
Utilizes 800*, 667, 533 and 400 Mb/s DDR2
SDRAM components
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
V
V
CC = VCCQ = 1.8V
CCSPD = 1.7V to 3.6V
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
Multiple internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3, 4, 5 and 6*
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# additive latency: (AL)
Serial Presence Detect (SPD) with EEPROM
Auto &self refresh (64ms: 8,192 cycle refresh)
Gold edge contacts
Single Rank
RoHS compliant
Package option
• 240 Pin RDIMM (VLP)
• PCB – 18.29mm (0.720") TYP
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4300
266MHz
4-4-4
PC2-5300
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
February 2007
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
PIN CONFIGURATION
PIN NAMES
Pin No.
1
Symbol
VREF
VSS
Pin No.
Symbol
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
VCCQ
A3
Pin Name
Function
61
A4
VSS
CK0,CK0#
CKE0
Clock Inputs
2
62
VCCQ
A2
DQ4
DQ5
VSS
Clock Enable
3
DQ0
DQ1
VSS
63
A1
4
64
VCC
VCC
DQ0-DQ63
CB0-CB7
RAS#
Data Input/Output
Check Bits
5
65
VSS
DQS9
DQS9#
VSS
CK0
6
DQS0#
DQS0
VSS
66
VSS
CK0#
VCC
Row Address Strobe
Column Address Strobe
Write Enable
7
67
VCC
8
68
NC
DQ6
DQ7
VSS
A0
CAS#
9
DQ2
DQ3
VSS
69
VCC
VCC
WE#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
A10/AP
BA0
BA1
S0#
Chip Select
71
DQ12
DQ13
VSS
VCCQ
RAS#
S0#
DQ8
DQ9
VSS
72
VCCQ
WE#
CAS#
VCCQ
NC
A0-A13
BA0,BA1
ODT0
Address Inputs
Bank Address Inputs
On-die termination control
SPD Clock Input
SPD Data Input/Output
SPD address
73
74
DQS10
DQS10#
VSS
VCCQ
ODT0
A13
DQS1#
DQS1
VSS
75
76
SCL
77
NC
NC
VCC
SDA
RESET#
NC
78
VCCQ
VSS
NC
VSS
SA0-SA2
DQS0-DQS17
79
VSS
DQ36
DQ37
VSS
VSS
80
DQ32
DQ33
VSS
DQ14
DQ15
VSS
Data strobes
DQ10
DQ11
VSS
81
DQS0#-DQS17# Data strobes complement
82
DQS13
DQS13#
VSS
V
CC, VCCQ
Core and I/O Power
Ground
83
DQS4#
DQS4
VSS
DQ20
DQ21
VSS
DQ16
DQ17
VSS
84
VSS
85
DQ38
DQ39
VSS
VREF
Input/Output Reference
SPD Power
86
DQ34
DQ35
VSS
DQS11
DQS11#
VSS
V
CCSPD
DQS2#
DQS2
VSS
87
88
DQ44
DQ45
VSS
NC
No connect
89
DQ40
DQ41
VSS
DQ22
DQ23
VSS
RESET#
Reset Input
DQ18
DQ19
VSS
90
91
14
92
DQS5#
DQS5
VSS
DQ28
DQ29
VSS
DQS14#
VSS
DQ24
DQ25
VSS
93
94
DQ46
DQ47
VSS
95
DQ42
DQ43
VSS
DQS12
DQS12#
VSS
DQS3#
DQS3
VSS
96
97
DQ52
DQ53
VSS
98
DQ48
DQ49
VSS
DQ30
DQ31
VSS
DQ26
DQ27
VSS
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
NC
SA2
CB4
NC
CB0
NC
CB5
VSS
CB1
VSS
VSS
DQS15
DQS15#
VSS
VSS
DQS6#
DQS6
VSS
DQS17
DQS17#
VSS
DQS8#
DQS8
VSS
DQ54
DQ55
VSS
DQ50
DQ51
VSS
CB6
CB2
CB7
CB3
VSS
DQ60
DQ61
VSS
VSS
DQ56
DQ57
VSS
VCCQ
NC
VCCQ
CKE0
VCC
VCC
DQS16
DQS16#
VSS
DQS7#
DQS7
VSS
NC
NC
NC
NC
VCCQ
A12
DQ62
DQ63
VSS
VCCQ
A11
DQ58
DQ59
VSS
A9
A7
VCC
VCCSPD
SA0
VCC
SDA
SCL
A8
A5
A6
SA1
February 2007
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
VSS
RS0#
DQS0
DQS0#
DQS9
DQS9#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
I/O 0
I/O 1
I/O 2
I/O 3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
DQS1
DQS1#
DQS10
DQS10#
DM
DM
DQ8
DQ9
DQ10
DQ11
I/O 0
I/O 1
I/O 2
I/O 3
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
DQS2
DQS2#
DQS11
DQS11#
DM
DM
DQ16
I/O 0
I/O 1
I/O 2
I/O 3
DQ20
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
DQ21
DQ22
DQ23
DQS3
DQS3#
DQS12
DQS12#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQ24
I/O 0
I/O 1
I/O 2
I/O 3
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
DQS4
DQS4#
DQS13
DQS13#
DM
DM
DQ32
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
DQ37
DQ38
DQ39
DQS5
DQS5#
DQS14
DQS14#
DM
DM
DQ40
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
Serial PD
DQS6
DQS6#
DQS15
DQS15#
SCL
SDA
DM
DM
WP A0 A1 A2
SA0 SA1 SA2
DQ48
I/O 0
I/O 1
I/O 2
I/O 3
DQ52
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
DQ53
DQ54
DQ55
DQS7
DQS7#
DQS16
DQS16#
DM
DM
VCCSPD
VCC/VCCQ
VREF
Serial PD
DQ56
I/O 0
I/O 1
I/O 2
I/O 3
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DQS8
DQS8#
DQS17
DQS17#
DM
DM
VSS
CB0
CB1
CB2
CB3
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
CK0
120Ω
PCK0-PCK6, PCK8, PCK9 ꢀ CK : DDR2 SDRAMs
1:2
R
E
G
I
RS0# : DDR2 SDRAMs
S0#
P
L
L
RBA0 - RBA1 : DDR2 SDRAMs
RA0 - RA13 : DDR2 SDRAMs
RRAS# : DDR2 SDRAMs
RCAS# : DDR2 SDRAMs
RWE# : DDR2 SDRAMs
RCKE0 : DDR2 SDRAMs
RODT0 : DDR2 SDRAMs
BA0 - BA1
A0 - A13
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
PCK0#-PCK6#, PCK8#, PCK9# ꢀ CK# : DDR2 SDRAMs
PCK7 ꢀ CK : Register
PCK7# ꢀ CK# : Register
CK0#
S
T
OE
RESET#
E
R
RST#
PCK7
PCK7#
NOTE: All resistor values are 22 ohms unless otherwise specified.
February 2007
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
VCC
Min
1.7
Typical
1.8
Max
1.9
Unit
V
Notes
Supply Voltage
I/O Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Notes:
3
1
2
VREF
0.49 x VCC
VREF-0.04
1.7
0.50 x VCC
VREF
0.51 x VCC
VREF+0.04
3.6
V
VTT
V
VCCSPD
-
V
1
V
REF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
3. CCQ of all IC's are tied to VCC
V
.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Min
-0.5
-0.5
-55
Max
2.3
2.3
100
10
Units
V
Voltage on VCC pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
VIN, VOUT
TSTG
V
°C
μA
Command/Address,
RAS#, CAS#, WE#,
-10
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
IL
CK, CK#
-10
-10
-46
10
10
46
μA
μA
μA
IOZ
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
VREF leakage current; VREF = Valid VREF level
DQ, DQS, DQS#
IVREF
February 2007
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Case Temperature (Commercial)
TOPER
0 to +85°C
°C
1, 2
NOTE:
1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2
2. At 0 - 85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
Max
Unit
Input High (Logic 1) Voltage
Input High (Logic 0) Voltage
VREF + 0.125
-0.300
VCC + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Unit
AC Input High (Logic 1) Voltage
DDR2-400 & DDR2-533
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
VREF + 0.250
-
V
AC Input High (Logic 1) Voltage
DDR2-667
VREF + 0.200
-
V
V
V
AC Input High (Logic 0) Voltage
DDR2-400 & DDR2-533
-
-
VREF - 0.250
VREF - 0.200
AC Input High (Logic 0) Voltage
DDR2-667
February 2007
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
Operating one bank active-precharge current;
806
665
534
403
Units
ICC0
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,278 1,170 1,098
mA
TDB
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
= tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are
SWITCHING; Data pattern is same as IDAD6W
ICC1
1,530 1,350 1,260
mA
TDB
Precharge power-down current;
ICC2P
ICC2Q
ICC2N
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
126
720
810
126
630
684
126
576
612
mA
mA
mA
TDB
TDB
TDB
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
594
162
504
162
432
162
mA
mA
TDB
TDB
ICC3P
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC3N
900
774
702
mA
mA
mA
TDB
TDB
TDB
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
ICC4W
2,340 1,980 1,710
2,340 1,980 1,710
2,520 2,340 2,250
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
= tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDAD6W
ICC4R
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC5B
mA
mA
TDB
TDB
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
ICC6
126
126
126
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK
=
ICC7
tCK(ICC), tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid
2,736 2,610 2,538
mA
TDB
commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDAD6R
;
Refer to the following page for detailed timing conditions
Note: ICC specification is based on QIMONDA components. Other DRAM Manufacturers specification may be different.
February 2007
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL
MIN
TBD
TBD
TBD
TBD
MAX
TBD
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ps
CL = 6
CL =5
CL = 4
CL = 3
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
3,000
3,750
5,000
0.45
8,000
8,000
8,000
0.55
3,750
3,750
5,000
0.45
8,000
8,000
8,000
0.55
5,000
5,000
5,000
0.45
8,000
8,000
8,000
0.55
ps
TBD
Clock cycle time
ps
TBD
ps
TBD
CK high-level width
CK low-level width
tCK
tCK
TBD
TBD
TBD
TBD
tCL
0.45
0.55
0.45
0.55
0.45
0.55
MIN (tCH
,
MIN (tCH
tCL
-500
,
MIN (tCH
tCL
-600
,
Half clock period
tHP
tAC
tHZ
ps
ps
ps
TBD
TBD
TBD
TBD
TBD
TBD
tCL)
)
)
DQ output access time from CK/CK#
-450
+450
+500
+600
Data-out high-impedance window from
CK/CK#
tAC MAX
tAC MAX
tAC MAX
Data-out low-impedance window from
CK/CK#
2x
tAC MIN
tLZ
tDS
tDH
tAC MAX tAC MIN tAC MAX tAC MIN tAC MAX
ps
ps
ps
TBD
TBD
TBD
TBD
TBD
TBD
DQ and DM input setup time relative to
DQS
100
175
0.35
100
225
0.35
150
275
0.35
DQ and DM input hold time relative to
DQS
A DQ and DM input pulse width (for each
input)
tDIPW
tQHS
tQH
tCK
ps
ps
TBD
TBD
TBD
TBD
TBD
TBD
Data hold skew factor
340
400
450
DQ - DQS hold, DQS to first DQ to go
nonvalid, per access
tHP - tQHS
tHP - tQHS
tHP - tQHS
Data valid output window (DVW)
DQS input high pulse width
tDVW
tDQSH
tDQSL
tDQSCK
tDSS
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
tQH - tDQSQ
0.35
ns
tCK
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
DQS input low pulse width
0.35
0.35
0.35
DQS output access time from CK/CK#
DQS falling edge to CK rising - setup time
-400
+400
240
-450
+450
300
-500
+500
350
0.2
0.2
0.2
tCK
DQS falling edge from CK rising - hold
time
tDSH
0.2
0.2
0.2
tCK
ps
TBD
TBD
TBD
TBD
DQS - DQ skew, DQS to last DQ valid,
per group, per access
tDQSQ
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
tRPRE
tRPST
tWPRE
tWPST
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
0.9
0.4
1.1
0.6
tCK
tCK
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.35
0.4
0.25
0.4
0.25
0.4
0.6
0.6
0.6
Write command to first DQS latching
transition
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
WL
- 0.25
WL +
0.25
tDQSS
tCK
TBD
TBD
Continued on next page
Note: AC specification is based on QIMONDA components. Other DRAM manufactures specification may be different
February 2007
Rev. 1
7
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W3HG128M72AER-AD6
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Address and control input pulse width for
each input
tIPW
0.6
0.6
0.6
tCK
TBD
TBD
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
tIS
tIH
200
275
2
250
375
2
350
475
2
ps
ps
tCK
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
tCCD
tRC
ACTIVE to ACTIVE (same bank) command
60
60
55
ACTIVE bank a to ACTIVE bank b
command
tRRD
7.5
7.5
7.5
ns
TBD
TBD
ACTIVE to READ or WRITE delay
ACTIVE to PRECHARGE command
tRCD
tRAS
15
45
15
45
15
40
ns
ns
TBD
TBD
TBD
TBD
70,000
70,000
70,000
Internal READ to precharge command
delay
tRTP
tWR
tDAL
7.5
15
7.5
15
7.5
15
ns
ns
ns
TBD
TBD
TBD
TBD
TBD
TBD
6 Write recovery time
Auto precharge write recovery + precharge
time
tWR
+
tWR
+
tWR
+
tRP
tRP
tRP
Internal WRITE to READ command delay
PRECHARGE command period
LOAD MODE command cycle time
OCD Drive mode delay
tWTR
tRP
tMRD
tOIT
7.5
15
2
7.5
15
2
10
15
2
ns
ns
tCK
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0
0
12
0
12
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
CKE low to CK,CK# uncertainty
tDELAY
ns
TBD
TBD
REFRESH to REFRESH command interval
Average periodic refresh interval
tRFC
tREF
105
105
70,000
7.8
105
70,000
7.8
ns
TBD
TBD
TBD
TBD
7.8
μs
Exit self refresh to non-READ command
Exit self refresh to READ command
Exit self refresh timing reference
tXSNR
tXSRD
tISXR
tRFC + 10
200
tRFC + 10
200
tRFC + 10
200
ns
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
250
350
Continued on next page
Note: AC specification is based on QIMONDA components. Other DRAM manufactures specification may be different
February 2007
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
AC CHARACTERISTICS
806
665
534
403
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
ODT turn-on delay
tAOND
2
2
2
2
2
2
tCK
TBD
TBD
tAC
(MAX)
+ 700
tAC
(MAX)
+ 1000
tAC
(MAX)
+ 1000
tAC
(MIN)
tAC
(MIN)
tAC
(MIN)
ODT turn-on
tAON
tAOFD
tAOF
ps
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
2.5
2.5
2.5
tAC
(MAX)
+ 600
tAC
(MAX)
+ 600
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MIN)
tAC
(MIN)
2 x tCK
+ tAC
(MAX)
+ 1,000
2 x tCK
+ tAC
(MAX)
+ 1,000
tAC
(MIN) +
2,000
tAC
(MIN) +
2,000
tAC
(MIN) +
2,000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
ps
ps
TBD
TBD
TBD
TBD
2.5
x tCK
+ tAC
(MAX)
+ 1,000
2.5
x tCK
+ tAC
(MAX)
+ 1000
2.5
x tCK
+ tAC
(MAX)
+ 1,000
tAC
(MIN) +
2,000
tAC
(MIN) +
2,000
tAC
(MIN) +
2,000
tAOFPD
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
3
8
3
8
3
8
tCK
tCK
TBD
TBD
TBD
TBD
Exit active power-down to READ command,
MR[bit12=0]
tXARD
2
2
2
tCK
tCK
TBD
TBD
TBD
TBD
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
7 - AL
6 - AL
6 - AL
A Exit precharge power-down to any non-
READ command.
tXP
2
3
2
3
2
3
tCK
tCK
TBD
TBD
TBD
TBD
CKE minimum high/low time
tCKE
Note: AC specification is based on QIMONDA components. Other DRAM manufactures specification may be different
February 2007
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
ORDERING INFORMATION FOR AD6
Part Number
Speed/Data Rate
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
CAS Latency tRCD
tRP
6
Height*
W3HG128M72AER806AD6xxG
W3HG128M72AER665AD6xxG
W3HG128M72AER534AD6xxG
W3HG128M72AER403AD6xxG
6
5
4
3
6
5
4
3
18.29mm (0.72") TYP
18.29mm (0.72") TYP
18.29mm (0.72") TYP
18.29mm (0.72") TYP
5
4
3
NOTES:
• For part numbering interpretation, please see "part numbering guide" on page 11.
PACKAGE DIMENSIONS FOR AD6
FRONT VIEW
3.99 (0.157)
MAX
133.50 (5.256)
133.20 (5.244)
2.00 (0.079) R
(4X)
18.45 (0.726)
17.75 (0.699)
2.50 (0.098) D
(2X)
10.00 (0.394)
TYP
2.30 (0.091)
TYP
0.75 (0.029) R
PIN 1
PIN 120
1.0 (0.039)
TYP
0.80 (0.040)
TYP
1.0 (0.039)
TYP
5.0 (0.250) TYP
1.37 (0.054)
1.17 (0.046)
63.0 (2.48)
TYP
55.0 (2.16)
TYP
123.0 (4.84)
TYP
BACK VIEW
3.05 (0.012)
TYP
PIN 240
PIN 121
2.20 (0.087)
TYP
70.68 (2.78)
TYP
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
February 2007
Rev. 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
PART NUMBERING GUIDE
W 3 H G 128M 72 A E R xxx AD6 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DEPTH
BUS WIDTH
COMPONENT WIDTH x4
1.8V
REGISTERED
SPEED (Mb/s)
PACKAGE 240 PIN (.72) RDIMM VLP
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(G = Qimonda)
Note: Consult factory for other vendor options
G = RoHS COMPLIANT
February 2007
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG128M72AER-AD6
White Electronic Designs
Document Title
1GB – 128Mx72 DDR2 SDRAM RDIMM VLP, w/PLL
DRAM DIE OPTIONS:
• QIMONDA: B-Die
Revision History
Rev #
Rev 0
History
Release Date Status
Created
January 2007
Concept
Rev 1
1.0 Updated Icc, AC and operating specifications
February 2007
Advanced
1.1 Updated package outline
February 2007
Rev. 1
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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