W3HG2256M72ACER806AD6MG [WEDC]
DDR DRAM Module, 512MX72, CMOS, ROHS COMPLIANT, DIMM-240;
| 型号： | W3HG2256M72ACER806AD6MG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | DDR DRAM Module, 512MX72, CMOS, ROHS COMPLIANT, DIMM-240 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总13页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED*
4GB – 2x256Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP
FEATURES
DESCRIPTION
240-pin, dual in-line very low profile (VLP) memory
module. Raw card "W"
The W3HG2256M72ACER is a 2x256Mx72 Double
Data Rate DDR2 SDRAM high density module based
on DDR2 SDRAM components. This memory module
consists of eighteen 512Mx4 (2Gb) bit with 8 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
Fast data transfer rates: PC2-6400*, PC2-5300,
PC2-4300 and PC2-3200
Support ECC error detection and correction
Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM
components
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
V
CC = VCCQ = 1.8V
VCCSPD = +1.7V to +3.6V
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity function
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# additive latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
ECC error detection and correction
Dual Rank
RoHS compliant
Package option
• 240 Pin VLP: 18.29mm (0.720") TYP
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4300
266MHz
4-4-4
PC2-5300
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
June 2007
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Pin No.
1
Symbol
VREF
VSS
Pin No.
Symbol
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
VCCQ
A3
Pin Name
Function
61
A4
VSS
A0-A13
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
2
62
VCCQ
A2
DQ4
DQ5
VSS
BA0,BA2
3
DQ0
DQ1
VSS
63
A1
4
64
VCC
VCC
DQ0-DQ63
CB0-CB7
DQS0-DQS17
5
65
VSS
DQS9
DQS9#
VSS
CK0
6
DQS0#
DQS0
VSS
66
VSS
CK0#
VCC
Data strobes
7
67
VCC
8
68
NC
DQ6
DQ7
VSS
A0
DQS0#-DQS17# Data strobes complement
9
DQ2
DQ3
VSS
69
VCC
VCC
ODT0, ODT1
CK0,CK0#
CKE0, CKE1
S0#, S1#
RAS#
On-die termination control
Clock Inputs, positive line
Clock Enables
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
70
A10/AP
BA0
BA1
71
DQ12
DQ13
VSS
VCCQ
RAS#
S0#
DQ8
DQ9
VSS
72
VCCQ
WE#
CAS#
VCCQ
S1#
73
Chip Selects
74
DQS10
DQS10#
VSS
VCCQ
ODT0
A13
Row Address Strobe
Column Address Strobe
Write Enable
DQS1#
DQS1
VSS
75
76
CAS#
77
ODT1
VCCQ
VSS
NC
VCC
WE#
RESET#
NC
78
NC
VSS
RESET#
SA0-SA2
SDA
Register Reset Input
SPD address
79
VSS
DQ36
DQ37
VSS
VSS
80
DQ32
DQ33
VSS
DQ14
DQ15
VSS
DQ10
DQ11
VSS
81
SPD Data Input/Output
Serial Presence Detect(SPD) Clock Input
Core Power
82
DQS13
DQS13#
VSS
SCL
83
DQS4#
DQS4
VSS
DQ20
DQ21
VSS
DQ16
DQ17
VSS
84
VCC
85
DQ38
DQ39
VSS
VCCQ
I/O Power
86
DQ34
DQ35
VSS
DQS11
DQS11#
VSS
VSS
Ground
DQS2#
DQS2
VSS
87
88
DQ44
DQ45
VSS
VREF
Power Supply for Reference
SPD Power
89
DQ40
DQ41
VSS
DQ22
DQ23
VSS
V
CCSPD
DQ18
DQ19
VSS
90
NC
Spare pins, No connect
91
DQS14
DQS14#
VSS
92
DQS5#
DQS5
VSS
DQ28
DQ29
VSS
DQ24
DQ25
VSS
93
94
DQ46
DQ47
VSS
95
DQ42
DQ43
VSS
DQS12
DQS12#
VSS
DQS3#
DQS3
VSS
96
97
DQ52
DQ53
VSS
98
DQ48
DQ49
VSS
DQ30
DQ31
VSS
DQ26
DQ27
VSS
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
NC
SA2
CB4
NC
CB0
NC
CB5
VSS
CB1
VSS
VSS
DQS15
DQS15#
VSS
VSS
DQS6#
DQS6
VSS
DQS17
DQS17#
VSS
DQS8#
DQS8
VSS
DQ54
DQ55
VSS
DQ50
DQ51
VSS
CB6
CB2
CB7
CB3
VSS
DQ60
DQ61
VSS
VSS
DQ56
DQ57
VSS
VCCQ
CKE1
VCC
VCCQ
CKE0
VCC
DQS16
DQS16#
VSS
DQS7#
DQS7
VSS
NC
BA2
NC
NC
VCCQ
A12
DQ62
DQ63
VSS
VCCQ
A11
DQ58
DQ59
VSS
A9
A7
VCC
VCCSPD
SA0
VCC
SDA
SCL
A8
A5
A6
SA1
June 2007
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
VSS
RS1#
RS0#
DQS0
DQS0#
DQS9
DQS9#
DM
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
DQ0
DQ4
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
DQS1
DQS1#
DQS10
DQS10#
DM
DM
DM
DM
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
DQ10
DQ11
DQS2
DQS2#
DQS11
DQS11#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQ16
DQ20
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
DQ21
DQ22
DQ23
DQS3
DQS3#
DQS12
DQS12#
DM
DM
DM
DM
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
DQS4
DQS4#
DQS13
DQS13#
DM
DM
DM
DM
DQ32
DQ36
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
DQ37
DQ38
DQ39
DQS5
DQS5#
DQS14
DQS14#
DM
DM
DM
DM
DQ40
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQS6
DQS6#
DQS15
DQS15#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQ48
DQ52
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
DQ53
DQ54
DQ55
DQS#7
DQS7#
DQS16
DQS16#
DM
DM
DM
DM
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
DQS8
DQS8#
DQS17
DQS17#
DM
DM
DM
DM
CB0
CB4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
CB5
CB6
CB7
VCCSPD
VCC/VCCQ
VREF
Serial PD
S0#
S1#
RS0# ꢀ CS# : DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
1:2
RS1# ꢀ CS# : DDR2 SDRAMs
BA0-BA2
A0-A13
RAS#
RBA0-RBA2 ꢀ BA0-BA2 : DDR2 SDRAMs
RA0-RA13 ꢀ A0-A13 : DDR2 SDRAMs
RRAS# ꢀ RAS# : DDR2 SDRAMs
RCAS# ꢀ CAS# : DDR2 SDRAMs
RWE# ꢀ WE# : DDR2 SDRAMs
RCKE0 ꢀ CKE : DDR2 SDRAMs
RCKE1 ꢀ CKE : DDR2 SDRAMs
RODT0 ꢀ ODT : DDR2 SDRAMs
RODT1 ꢀ ODT : DDR2 SDRAMs
R
E
G
I
S
T
E
R
VSS
Serial PD
CAS#
WE#
SCL
SDA
CKE0
WP A0 A1 A2
SA0 SA1 SA2
CKE1
ODT0
ODT1
RESET#
RST#
CK0
PCK0-PCK6, PCK8, PCK9 ꢀ CK : DDR2 SDRAMs
P
L
L
PCK7**
PCK7#**
PCK0#-PCK6#, PCK8#, PCK9# ꢀ CK# : DDR2 SDRAMs
PCK7 ꢀ CK : Register
PCK7# ꢀ CK# : Register
CK0#
OE
RESET#**
NOTE: All resistor values are 22 ohms unless otherwise specified.
June 2007
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED
RECOMMENDED DC OPERATING CONDITIONS
All Voltages Referenced to VSS
Rating
Parameter
Symbol
VCC
Min.
1.7
Type
1.8
Max.
1.9
Units
Notes
Supply Voltage
V
V
V
V
V
4
4
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
VCCL
VCCQ
VREF
VTT
1.7
1.8
1.9
1.7
1.8
1.9
4
0.49*VCCQ
VREF-0.04
0.50*VCCQ
VREF
0.51*VCCQ
VREF+0.04
1, 2
3
There is no specific device VCC supply voltage requirement for SSTL-1.8 compliance. However under all conditions VCCQ must be less than or equal to VCC
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is expected to be about 0.5 x VCCQ of the transmitting
device and VREF is expected to track variations in VCCQ
2. Peak to peak AC noise on VREF may not exceed ±2% VREF(DC).
.
.
3.
4.
V
V
TT of transmitting device must track VREF of receiving device.
CC, VCCQ and VCCL are tied together on this module.
ABSOLUTE MAXIMUM RATINGS
SSTL_1.8V
Symbol
VCC
Parameter
Rating
Units
Notes
Voltage on VCC pin relative to VSS
Voltage on VCCQ pin relative to VSS
Voltage on VCCL pin relative to VSS
Voltage on any pin relative to VSS
Storage Temperature
- 1.0 V - 2.3 V
- 0.5 V - 2.3 V
- 0.5 V - 2.3 V
- 0.5 V - 2.3 V
-55 to +100
V
V
V
V
C
5
5
VCCQ
VCCL
5
VIN, VOUT
TSTG
5
5, 6
5. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
6. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
June 2007
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
Operating one bank active-precharge current;
806
665
534
403
Units
ICC0 tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
1,746 1,476 1,476
mA
TBD
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as ICC4W
=
ICC1
2,016 1,926 1,836
mA
TBD
Precharge power-down current;
ICC2P All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
256
846
936
252
846
936
252
756
846
mA
mA
mA
TBD
TBD
TBD
Precharge quiet standby current;
ICC2Q All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
Precharge standby current;
ICC2N All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
666
306
666
306
666
306
mA
mA
TBD
TBD
ICC3P
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC3N
1,206 1,026
936
mA
mA
mA
TBD
TBD
TBD
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
ICC4W
2,646 2,466 2,106
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
=
ICC4R
2,646 2,466 2,106
4,086 3,996 3,906
Burst auto refresh current;
ICC5B tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
mA
TBD
TBD
Self refresh current;
ICC6 CK and CK# at 0V; CKE 0.2V; Other control and address bus inputs
are FLOATING; Data bus inputs are FLOATING
252
252
252
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
ICC7 tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the
following page for detailed timing conditions
5,256 5,076 4,896
mA
TBD
NOTES: ICC specs are based on MICRON components. Other DRAM manufacturers parameters may be different.
Inactive chips are in ICC2P condition with inputs switching.
June 2007
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION
0°C≤TCASE<+85°C
AC CHARACTERISTICS
PARAMETER
806
667
534
403
SYMBOL
UNIT Notes
MIN
TBD
TBD
TBD
TBD
TBD
TBD
MAX
TBD
TBD
TBD
TBD
TBD
TBD
MIN
MAX
MIN
MAX
MIN
MAX
CL = 6
CL = 5
CL = 4
CL = 3
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
ps
ps
ps
ps
tCK
tCK
16, 24
16, 24
16, 24
16, 24
18
3,000 8,000
Clock cycle time
3,750 8,000 3,750 8,000 5,000 8,000
5,000 8,000 5,000 8,000 5,000 8,000
CK high-level width
CK low-level width
0.48
0.48
MIN
0.52
0.55
0.48
0.48
MIN
0.52
0.55
0.48
0.48
MIN
0.52
0.55
tCL
18
Half clock period
tHP
(tCH
,
(tCH
,
(tCH
,
ps
19
TBD
TBD
tCL
)
tCL
)
tCL
)
DQ output access time from CK/CK#
tAC
tHZ
-450
+450
-500
+500
-600
+600
ps
ps
TBD
TBD
TBD
TBD
Data-out high-impedance window from
CK/CK#
tAC
(MAX)
tAC
MAX
tAC
MAX
8, 9
tAC
tAC
tAC
tAC
tAC
tAC
Data-out low-impedance window from CK/CK#
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
tLZ
ps
ps
ps
tCK
ps
tCK
8, 10
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(MIN) (MAX) (MIN) (MAX) (MIN) (MAX)
7, 15,
21
tDSa
tDHa
tDSb
tQHb
300
300
100
175
0.35
350
350
100
225
0.35
400
400
150
275
0.35
7, 15,
21
7, 15,
21
7, 15,
21
DQ…DQS hold, DQS to first DQ to go
nonvalid, per access relative to DQS
tDIPW
tQHS
tQH
TBD
TBD
TBD
TBD
TBD
TBD
Data hold skew factor
340
400
450
DQ–DQS hold, DQS to first DQ to go nonvalid,
per access
tHP
-
tHP
-
tHP
-
15, 17
15, 17
tQHS
tQHS
tQHS
tQH
-
tQH
-
tQH-
Data valid output window (DVW)
tDVW
TBD
TBD
tDQSQ
0.35
0.35
-400
tDQSQ
0.35
0.35
-450
tDQSQ
0.35
0.35
-500
DQS input high pulse width
tDQSH
tDQSL
tCK
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
DQS input low pulse width
DQS output access time from CK/CK#
tDQSCK
+400
+450
+500
DQS falling edge to CK rising– setup time
DQS falling edge from CK rising – hold time
tDSS
0.2
0.2
0.2
0.2
0.2
0.2
tCK
TBD
TBD
TBD
TBD
tDSH
tCK
DQS–DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ
tRPRE
240
1.1
300
1.1
350
1.1
ps
15, 17
35
TBD
TBD
TBD
TBD
DQS read preamble
0.9
0.9
0.9
tCK
NOTE:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
June 2007
Rev. 1
6
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ADVANCED
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION (Con't)
0°C≤TCASE<+85°C
AC CHARACTERISTICS
806
665
534
403
SYMBOL
UNIT
Notes
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
DQS read preamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ps
35
TBD
TBD
12, 13,
36
DQS write preamble setup time
tWPRES
0
0
0
TBD
TBD
DQS write preamble
DQS write postamble
tWPRE
tWPST
0.35
0.4
0.35
0.4
0.35
0.4
tCK
tCK
TBD
TBD
TBD
TBD
0.6
0.6
0.6
11
Write command to first DQS
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
tDQSS
tIPW
tISa
tCK
tCK
ps
ps
ps
ps
tCK
ns
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
latching transition
Address and control input
pulse width for each input
0.6
400
400
200
275
2
0.6
500
500
250
375
2
0.6
600
600
350
475
2
Address and control input
setup time
6, 21
6, 21
6, 21
6, 21
Address and control input
hold time
tIHa
Address and control input
setup time
tISb
Address and control input
hold time
tIHb
CAS# to CAS# command
delay
tCCD
tRC
Active to Active (same bank)
command
55
55
55
33
27
Active bank a to Active b bank
command
tRRD
7.5
7.5
7.5
Active to Read or Write delay
Four Bank Activate period
Active to precharge command
tRCD
tFAW
tRAS
15
37.5
40
15
37.5
40
15
37.5
40
ns
ns
ns
TBD
TBD
TBD
TBD
TBD
TBD
30
70,000
70,000
70,000
20, 33
Internal Read to precharge
command delay
tRTP
tWR
tDAL
7.5
15
7.5
15
7.5
15
ns
ns
ns
23, 27
27
TBD
TBD
TBD
TBD
TBD
TBD
Write recovery time
Auto precharge write recovery
and precharge time
tWR+tRP
tWR+tRP
tWR+tRP
22
Interval Write to Read
command delay
tWTR
7.5
7.5
10
ns
27
TBD
TBD
Precharge command period
tRP
15
18
15
15
20
ns
ns
31
31
TBD
TBD
TBD
TBD
Precharge All command period
tRPA
18.75
Load Mode command cycle
time
tMRD
2
2
2
tCK
ns
TBD
TBD
TBD
TBD
CKE low to CK,CK#
uncertainty
tDELAY
tIS+tCK+ IH
t
tIS+tCK+ IH
t
tIS+tCK+ IH
t
28
NOTE:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
June 2007
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG2256M72ACER-AD6
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ADVANCED
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION (Con't)
0°C≤TCASE<+85°C
AC CHARACTERISTICS
PARAMETER
806
665
534
403
SYMBOL
UNIT
Notes
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Refresh to Active or Refresh to
Refresh command interval
tRFC
tREFI
tXSNR
tXSRD
127.5
70,000
127.5
70,000
127.5
70,000
ns
µs
ns
14
14
TBD
TBD
Average periodic refresh
interval
7.8
7.8
7.8
TBD
TBD
TBD
TBD
TBD
TBD
Exit self refresh to non-read
command
tRFC
(MIN)+10
tRFC
(MIN)+10
tRFC
(MIN)+10
Exit self refresh to read
command
200
200
200
tCK
Exit self refresh timing
reference
tISXR
tIS
2
tIS
2
tIS
2
ps
6, 29
25
TBD
TBD
TBD
TBD
ODT turn-on delay
tAOND
2
2
2
tCK
tAC(MAX)
+700
tAC(MAX)
+1,000
tAC(MAX)
+1,000
ODT turn-on
tAON
tAOFD
tAOF
tAC(MIN)
2.5
tAC(MIN)
2.5
tAC(MIN)
2.5
ps
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MIN)
tAC(MIN)
tAC(MIN)
26
2x tCK
tAC (MAX)
+ 1,000
+
2x tCK
tAC (MAX)
+ 1,000
+
2x tCK +
tAC (MAX)
+ 1,000
tAC(MIN)
+2,000
tAC(MIN)
+2,000
tAC(MIN)
+2,000
ODT turn-on (power-down
mode)
tAONPD
ps
TBD
TBD
TBD
TBD
2.5x tCK
+ tAC
2.5x tCK
+ tAC
2.5x tCK
+ tAC
+
(MAX)
1,000
tAC(MIN)
+2,000
tAC(MIN)
+2,000
tAC(MIN)
+2,000
ODT turn-off (power-down
mode)
tAOFPD
tCK
+
+
(MAX)
(MAX)
1,000
1,000
ODT to power-down entry
latency
tANPD
tAXPD
tXARD
3
8
2
3
8
2
3
8
2
tCK
tCK
tCK
TBD
TBD
TBD
TBD
TBD
TBD
ODT power-down exit latency
Exit active power-down to
READ command, MR[bit12=0]
Exit active power-down to
READ command, MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
tCK
TBD
TBD
Exit precharge power-down to
any non-READ command.
tXP
2
3
2
3
2
3
tCK
tCK
TBD
TBD
TBD
TBD
CKE minimum high/low time
tCKE
34
NOTE:
• AC specification is based on MICRON components. Other DRAM manufactures specification may be different.
June 2007
Rev. 1
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ADVANCED
10. tLZ (MIN) tLZ will prevail over a tDQSCK (MIN) + tRPRE (MAX)
condition.
Notes
1.
All voltages referenced to VSS
11. The intent of the Don’t Care state after completion of the
postamble is the DQS-driven signal should either be high, low or
High-Z and that any signal transition within the input switching
region must follow valid input requirements. That is if DQS
transitions high (above VIH DC (MIN) then it must not transition low
(below VIH (DC) prior to tDQSH (MIN).
2.
Tests for AC timing, ICC, and electrical AC and DC characteristics
may be conducted at nominal reference/supply voltage levels, but
the related specifications and device operation are guaranteed for
the full voltage range specified.
3.
4.
Outputs measured with equivalent load:
VTT = VCCQ/2
12. This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus turn
around.
25Ω
Reference
Point
Output
(VOUT)
13. It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
HIGH during this time, depending on tDQSS.
AC timing and ICC tests may use a VIL to VIH swing of up to 1.0V
in the test environment parameter specifications are guaranteed
for the specified AC input levels under normal use conditions. The
minimum slew rate for the input signals used to test the device is
1.0V/ns for signals in the range between VIL (AC) and VIH (AC).
Slew derates less than 1.0V/ns require the timing parameters to be
rated as specified.
14. The refresh period is 64ms. This equates to an average refresh
rate of 7.8125µs. However, a REFRESH command must be
asserted at least once every 70.3µs or tRFC (MAX). To ensure
all rows of all banks are properly refreshed, 8192 REFRESH
commands must be issued every 64ms.
5.
6.
The AC and DC input level specifications are as defined in the
SSTL_18 standard (i.e., the receiver will effectively switch as a
result of the signal crossing the AC input level and will remain in
that state as long as the signal does not ring back above [below]
the DC input LOW [HIGH] level).
15. Each half-byte lane has a corresponding DQS.
16. CK and CK# input slew rate must be ≥ 1V/ns (≥ 2V/ns if measured
differentially).
1. There are two sets of values listed for command/address: tISa,
tIHa and tISb, tIHb. The tISa, tIHa values (for reference only) are
equivalent to the baseline values of tISb, tIHb at VREF when
the slew rate is 1 V/ns. The baseline values, tISb, tIHb, are the
JEDEC-defined values, referenced from the logic trip points. tISb
is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling
signal, while tIHb is referenced from VIL(DC) for a rising signal and
17. The data valid window is derived by achieving other specifications
- tHP. (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window
derates in direct proportion to the clock duty cycle and a practical
data valid window can be derived.
18.
tHP (MIN) is the lesser of tCL minimum and tCH minimum actually
applied to the device CK and CK# inputs.
V
IH(DC) for a falling signal. If the command/address slew rate is
19. READs and WRITEs with auto precharge are allowed to be
issued before tRAS (MIN) is satisfied since tRAS lockout feature is
supported in DDR2 SDRAM devices.
not equal to 1 V/ns, then the baseline values must be derated by
adding the values.
7.
1. The values listed are for the differential DQS strobe (DQS and
DQS#) with a differential slew rate of 2 V/ns (1 V/ns for each
signal). There are two sets of values listed: tDSa, tDHa and tDSb,
tDHb. The tDSa, tDHa values (for reference only) are equivalent
to the baseline values of tDS~, tDHb at VREF when the slew rate
is 2 V/ns, differentially. The baseline values, tDSb, DHb, are the
JEDEC-defined values, referenced from the logic trip points. tDSb
is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling
signal, while tDHb is referenced from VIL(DC) for a rising signal
and VIH(DC) for a falling signal. If the differential DQS slew rate
is not equal to 2 V/ns, then the baseline values must be derated
by adding the values from Tables 24 and 25 on pages 91–92. If
the DQS differential strobe feature is not enabled, then the DQS
strobe is single-ended, the baseline values are not applicable, and
timing is not referenced to the logic trip points. Single-ended DQS
20. VIL/VIH DDR2 overshoot/undershoot. REFER to the 512Mb or 1Gb
DDR2 SDRAM data sheet for more detail.
21.
tDAL = (nWR) + (tRP/tCK): For each of the terms above, if not already
an integer, round to the next highest integer. tCK refers to the
application clock period; nWR refers to the tWR parameter stored
in the MR[11,10,9]. Example: For 534 at tCK= 3.75 ns with tWR
programmed to four clocks. tDAL = 4 + (15 ns/3.75ns) clock = 4 +
(4) clocks = 8 clocks.
22. The minimum READ to internal PRECHARGE time. This
parameter is only applicable when tRTP/2*tCK) > 1. If tRTP/2*tCK) ≤ 1,
then equation AL + BL/2 applies. Notwithstanding, tRAS (MIN) has
to be satisfied as well. The DDR2 SDRAM device will automatically
delay the internal PRECHARGE command until tRAS (MIN) has
been satisfied.
data timing is referenced to DQS crossing VREF
.
23. Operating frequency is only allowed to change during self refresh
mode, precharge power-down mode, and system reset condition.
8.
9.
tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (when the device output is no longer driving (tHZ) or
begins driving (tLZ).
24. ODT turn-on time tAON (MIN) is when the device leaves high
impedance and ODT resistance begins to turn on. ODT turn-on
time tAON (MAX) is when the ODT resistance is fully on. Both are
measured from tAOND
.
This maximum value is derived from the referenced test load. tHZ
(MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition.
25. ODT turn-off time tAOF (MIN) is when the device starts to turn off
ODT resistance. ODT turn off time tAOF (MAX) is when the bus is in
June 2007
Rev. 1
9
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W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED
high impedance. Both are measured from tAOFD
.
registrations.
26. This parameter has a two clock minimum requirement at any tCK
27. tDELAY is calculated from tIS + tCK + tIH so that CKE registration
.
32. Applicable to Read cycles only. Write cycles generally require
additional time due to Write recovery time (tWR) during auto
precharge.
LOW is guaranteed prior to CK, CK# being removed in a system
RESET condition.
33.
tCKE (MIN) of 3 clocks means CKE must be registered on three
consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the 3 clocks of
registration. Thus, after any CKE transition, CKE may not transition
28.
t
ISXR is equal to tIS and is used for CKE setup time during self
refresh exit.
29. No more than 4 bank ACTIVE commands may be issued in
a given tFAW (MIN) period. tRRRD (MIN) restriction still applies.
The tFAW (MIN) parameter applies to all 8 bank DDR2 devices,
regardless of the number of banks already open or closed.
from its valid level during the time period of tIS + 2* tCK + tIH
.
34. This parameter is not referenced to a specific voltage level, but
specified when the device output is no longer driving (tRPST) or
beginning to drive (tRPRE).
30.
tRPA timing applies when the PRECHARGE(ALL) command is
35. When DQS is used single-ended, the minimum limit is reduced by
100ps.
issued, regardless of the number of banks already open or closed.
If a single-bank PRECHARGE command is issued, tRP timing
applies. tRPA (MIN) applies to all 8-bank DDR2 devices.
31. Value is minimum pulse width, not the number of clock
June 2007
Rev. 1
10
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W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR AD6
Part Number
Speed/Data Rate
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
CAS Latency
tRCD
6
tRP
6
Height*
W3HG2256M72ACER806AD6xxG**
W3HG2256M72ACER665AD6xxG
W3HG2256M72ACER534AD6xxG
W3HG2256M72ACER403AD6xxG
6
5
4
3
18.29mm (0.72") TYP
18.29mm (0.72") TYP
18.29mm (0.72") TYP
18.29mm (0.72") TYP
5
5
4
4
3
3
** Contact factory for availability
NOTES:
• For part numbering interpretation, please see "part numbering guide" on page 12.
PACKAGE DIMENSIONS FOR AD6
Front View
133.35 (5.25ꢀ
3.00
(0.118ꢀ
18.29
(0.720ꢀ TYP
4.00
0.80 0.05
4.00 (0.157ꢀ
4.06 MAX
(0.160ꢀ
(0.157ꢀ
(0.031 0.002ꢀ
2.50 0.20
(0.098 0.007ꢀ
1.50 0.10
1.00 (0.039ꢀ
(0.059 0.004ꢀ
5.00
(0.196ꢀ
Back View
63.00 (2.48ꢀ
55.00 (2.165ꢀ
1.27 0.10
(0.050 -0.004ꢀ
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
June 2007
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
W 3 H G 2 256M 72 A C E R xxx AD6 x x G
WEDC
MEMORY (SDRAM)
TECHNOLOGY DDR 2
GOLD
2 RANK
("BLANK" = 1 RANK)
DEPTH
BUS WIDTH
COMPONENT WIDTH x4
C = DIE STACKED BGA
("BLANK" = Standard FBGA Packaging)
CORE VOLTAGE 1.8V
REGISTERED
SPEED (Mb/s)
PACKAGE 240 PIN (.72)
INDUSTRIAL TEMP OPTION
(For commercial leave "BLANK" for industrial add "I"
COMPONENT VENDOR NAME
(M = Micron)
Note: consult factory for other vendor options
G = RoHS COMPLIANT
NOTES:
1: This character represents the general product revision that is used to control and record any changes in the memory die revision.
2: In order to obtain the most current revision, please contact the factors.
June 2007
Rev. 1
12
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W3HG2256M72ACER-AD6
White Electronic Designs
ADVANCED
Document Title
4GB – 2x256Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP
Revision History
DRAM OPTIONS:
• MICRON: U 28A, RevA
Rev #
History
Release Date Status
Rev 0
Rev 1
Evaluation and review
Moved to advanced
May 2007
June 2007
Concept
Advanced
June 2007
Rev. 1
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
相关型号：
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