W72M64VK90BC [WEDC]
2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package; 2Mx64 3.3V同步操作闪存多芯片封装
| 型号： | W72M64VK90BC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package |
| 文件： | 总16页 (文件大小：556K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W72M64VK-XBX
White Electronic Designs
2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package
FEATURES
ꢀ
ꢀ
Access Times of 90, 100, 120ns
Packaging
ꢀ
ꢀ
ꢀ
ꢀ
Unlock Bypass Program command
• Reduces overall programming time when issuing
multiple program command sequences
• 159 PBGA, 13x22mm - 1.27mm pitch
1,000,000 Erase/Program Cycles
Sector Architecture
Ready/Busy# output (RY/BY#)
ꢀ
ꢀ
• Hardware method for detecting program or erase
cycle completion
• Bank 1 (4Mb): eight 4K word, eight 32K word
• Bank 2 (12Mb): twenty-four 32K word
• Bank 3 (12Mb): twenty-four 32K word
• Bank 4 (4Mb): eight 32K word
Bottom boot block
Hardware reset pin (RESET#)
• Hardware method of resetting the internal state
machine to the read mode
WP#/ACC input pin
ꢀ
ꢀ
ꢀ
ꢀ
• Write protect (WP#) function allows protection
two outermost boot sectors, regardless of sector
protect status
Zero Power Operation
Organized as 2Mx64 or 2x2Mx32
• Acceleration (ACC) function accelerates program
timing
Commercial, Industrial and Military Temperature
Ranges
ꢀ
Sector Protection
ꢀ
ꢀ
3.3 Volt for Read and Write Operations
Simultaneous Read/Write Operation:
• Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within
that sector
• Data can be continuously read from one bank
while executing erase/program functions in
another bank
• Temporary Sector Unprotect allows changing
data in protected sectors in-system
• Zero latency between read and write operations
Erase Suspend/Resume
ꢀ
ꢀ
• Suspends erase operations to allow programming
in same bank
Note: For programming information refer to Flash Programming
W72M64V-XBX Application Note.
Data# Polling and Toggle Bits
This product is subject to change without notice.
• Provides a software method of detecting the
status of program or erase cycles
April 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
FIGURE 1: PIN CONFIGURATION FOR W72M64V-XBX
Top View Pin Description
1
2
GND
GND
DQ33
DQ40
DQ32
CS3#
OE#
A2
3
GND
DQ41
DQ43
DQ35
DQ42
DQ34
A0
4
5
VCC
6
7
8
9 10
DQ0-63
A0-20
WE1-4#
CS1-4#
OE#
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Hardware Reset
GND
WE3#
DQ45
DQ37
DQ44
DQ36
DNU*
A11
VCC
GND
DNU
DQ59
DQ51
GND
WE4#
DQ61
DQ53
GND
VCC
A
B
C
D
E
F
VCC
VCC
VCC
DQ57
DQ49
DQ56
DQ48
VCC
VCC
DQ47
DQ39
DQ46
DQ63
DQ55
DQ62
DQ54
A20
VCC
RESET#
WP#/ACC Hardware Write
VCC
VCC
Protect/Acceleration
VCC
DQ58 DQ60
VCC
RY/BY#
VCC
GND
DNU
Ready/Busy Output
Power Supply
Ground
GND
GND
GND
GND
GND
GND
VCC
DQ38 CS4#
DQ50
A16
DQ52
DNU*
A10
GND
GND
GND*
GND
GND
GND
VCC
Do Not Use
VCC
GND
VCC
A12
VCC
G
H
J
WP#/ACC
A6
A7
A15
A3
A9
GND
A14
A1
RESET#
A18
A13
A4
A17
RY/BY#
DQ29
DQ21
DQ28
DQ20
DQ27
GND
GND
DNU
DQ31
DQ23
DQ30
DQ22
VCC
A5
A8
K
L
DQ17 WE2#
DQ9
DQ1
DQ8
DQ0
CS1#
VCC
DQ4
DQ11
DQ3
DQ10
DQ2
GND
WE1#
DQ6
A19
DQ24
DQ16
CS2#
VCC
DQ19
DQ26
DQ18
DQ25
GND
DQ15
DQ7
DQ14
GND
GND
M
N
P
R
T
VCC
DQ13
DQ5
VCC
VCC
VCC
VCC
DQ12
GND
VCC
VCC
GND
VCC
* Ball G8 is reserved for A21 and ball G4 is reserved for A22 on
W78M64V-XSBX.
Block Diagram
WE1
#
WE2
#
WE3
#
WE4#
CS4
#
CS3
#
CS1
#
CS2
#
RY/BY#
RESET#
OE#
A0-20
BYTE#
BYTE#
BYTE#
2M x 16
DQ0-15
2M x 16
DQ16-31
2M x 16
DQ32-47
2M x 16 BYTE#
V
CC
WP#/ACC
DQ48-63
April 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
TA = +25°C, F = 1.0MHz
Parameter
Unit
°C
V
V
°C
Parameter
Symbol
CWE
CCS
Max
8
8
10
30
26
26
32
Unit
pF
pF
pF
pF
pF
pF
pF
Operating Temperature
Supply Voltage Range (VCC)
Signal Voltage Range
Storage Temperature Range
Endurance (write/erase cycles)
NOTES:
-55 to +125
-0.5 to +4.0
-0.5 to Vcc +0.5
-55 to +150
WE1-4# capacitance
CS1-4# capacitance
Data I/O capacitance
CI/O
Address input capacitance
RESET# capacitance
RY/BY# capacitance
OE# capacitance
CAD
CRS
CRB
COE
1,000,000 min.
cycles
1. Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
This parameter is guaranteed by design but not tested.
RECOMMENDED OPERATING CONDITIONS
DATA RETENTION
Parameter
Supply Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
Symbol
VCC
TA
Min
3.0
-55
-40
Max
3.6
+125
+85
Unit
V
°C
°C
Parameter
Test Conditions
150°C
Min
10
Unit
Years
Years
Pattern Data
Retention Time
125°C
20
TA
DC CHARACTERISTICS – CMOS COMPATIBLE
VCC = 3.3V 0.3V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
VCC Active Current for Read (1)
VCC Active Current for Program or Erase (2,3)
VCC Standby Current (2)
Symbol Conditions
Min
-10
-10
Max
10
10
65
120
400
Unit
µA
µA
mA
mA
µA
ILI
VCC = 3.6V, VIN = GND to VCC
VCC = 3.6V, VOUT = GND to VCC
CS# = VIL#, OE = VIH, f = 5MHz
CS# = VIL#, OE = VIH, WE# = VIL
CS# = RESET# = VCC 0.3V
ILO
ICC1
ICC2
ICC3
VIH = VCC 0.3V;
VIL = VSS 0.3V
Automatic Sleep Mode (2,4,5)
ICC5
400
µA
VCC Active Read-While-Program Current (1,2)
VCC Active Program-While-Erase Current (1,2)
VCC Active Program-While-Erase-Suspended Current (2,5)
ACC Accelerated Program Current
ICC6
ICC7
ICC8
IACC
CS# = VIL#, OE = VIH
CS# = VIL#, OE = VIH
CS# = VIL#, OE = VIH
CS# = VIL#, OE = VIH ACC Pin
VCC Pin
180
180
140
40
120
0.8
mA
mA
mA
mA
Input Low Voltage
Input High Voltage
Voltage for WP#/ACC Sector
Protect/Unprotect and Program Acceleration
VIL
VIH
VHH
-0.5
2.1
8.5
V
V
V
VCC = min
VCC = 3.0V + 0.3V
VCC + 0.3
9.5
Voltage for Autoselect and Temporary Sector Unprotect
Output Low Voltage
Output High Voltage
VID
VOL
VOH1
VLKO
VCC = 3.0V + 0.3V
IOL = 4.0 mA, VCC = 3.0V
IOH = -2.0 mA, VCC = 3.0V
8.5
12.5
0.45
V
V
V
V
2.55
2.3
Low VCC Lock-Out Voltage (5)
2.5
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 8 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCC MAX
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30ns.
5. Not tested.
April 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS – CS# CONTROLLED
VCC = 3.3V 0.3V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-90
-100
-120
Unit
Min
90
0
35
0
45
0
45
30
Max
Min
100
0
45
0
45
0
45
30
Max
Min
120
0
50
0
50
0
50
30
Max
Write Cycle Time (3)
tAVAV
tWLEL
tELEH
tAVWL
tDVEH
tEHDX
tELAX
tWC
tWS
tCP
tAS
tDS
tDH
tAH
tCPH
ns
ns
ns
ns
ns
ns
ns
ns
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High (3)
Duration of Word Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time Before Write (3)
Chip Programming Time (4)
tEHEL
tWHWH1
tWHWH2
tGHEL
300
5
300
5
300
5
µs
sec
ns
0
0
0
42
42
42
sec
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 0.4 sec.
3. Guaranteed by design, but not tested.
4. Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip
programming time listed, since most bytes program faster than the maximum program times listed.
FIGURE 2
AC Test Circuit
AC Test Conditions
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Notes:
Z is programmable from -2V to +7V.
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75W.
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
Typ
Unit
IOL
VIL = 0, VIH = 2.5
V
ns
V
Current Source
5
1.5
1.5
V
VZ » 1.5V
(Bipolar Supply)
D.U.T.
CEFF = 50 pf
V
I
V
I
.
IOH
Current Source
April 2005
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS – WE# CONTROLLED
VCC = 3.3V 0.3V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-90
-100
-120
Unit
Min
90
0
35
0
Max
Min
100
0
50
0
Max
Min
120
0
50
0
Max
Write Cycle Time (3)
tAVAV
tWC
tCS
tWP
tAS
ns
ns
ns
Chip Select Setup Time (3)
Write Enable Pulse Width
Address Setup Time
tELWL
tWLWH
tAVWL
ns
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High (3)
Duration of Byte Programming Operation (1)
Sector Erase (2)
Read Recovery Time before Write (3)
VCC Setup Time
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWHWH2
tGHWL
tVCS
tDS
tDH
tAH
45
0
45
30
50
0
50
30
50
0
50
30
ns
ns
ns
ns
µs
sec
ns
µs
sec
ns
tWPH
300
5
300
5
300
5
0
50
0
50
0
50
Chip Programming Time (4)
Address Setup Time to OE# low during toggle
bit polling
42
42
42
tASO
15
15
15
Write Recovery Time from RY/BY# (3)
Program/Erase Valid to RY/BY#
tRB
tBUSY
0
90
0
90
0
90
ns
ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 0.4 sec.
3. Guaranteed by design, but not tested.
4. Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip
programming time listed, since most bytes program faster than the maximum program times listed.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
VCC = 3.3V 0.3V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-90
-100
-120
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time (1)
tAVAV
tRC
tACC
tCE
tOE
tDF
90
100
120
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
90
90
40
20
20
100
100
40
120
120
50
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z
Output Enable High to Output High Z
20
20
tDF
20
20
Output Hold from Addresses, CS# or OE#
Change, Whichever occurs first
tOH
0
0
0
Output Enable Hold Time (1) Read
tOEH
0
0
0
Toggle and
Data# Polling
10
10
10
1. Guaranteed by design, not tested.
April 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
FIGURE 3: AC WAVEFORMS FOR READ OPERATIONS
tRC
Addresses Stable
tACC
Addresses
CS#
tDF
tOE
OE#
WE#
tOEH
tCE
tOH
High Z
High Z
Outputs
Output Valid
RESET#
RY/BY#
OV
April 2005
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
AC CHARACTERISTICS – HARDWARE RESET (RESET#)
Parameter
Symbol
-90
-100
-120
Unit
Min
Max
Min
Max
Min
Max
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (1)
tready
20
20
20
µs
RESET# Pin Low (NOT During Embedded Algorithms)
to Read Mode (1)
tready
500
500
500
ns
RESET# Pulse Width
tRP
tRH
500
50
500
50
500
50
ns
ns
µs
RESET# High Time Before Read (1)
RESET# Low to Standby Mode (1)
NOTE: 1. Not tested.
tRPD
20
20
20
FIGURE 4: RESET TIMINGS NOT DURING EMBEDDED ALGORITHMS
RY/BY#
CS#, OE#
t
RH
RESET#
t
RP
t
Ready
FIGURE 5: RESET TIMINGS DURING EMBEDDED ALGORITHMS
t
Ready
RY/BY#
CS#, OE#
RESET#
t
RP
April 2005
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
FIGURE 6: PROGRAM OPERATIONS
tWC
tAS
Addresses
CS#
555h
PA
PA
PA
tAS
tCH
OE#
tWHWH1
tWP
tDS
WE#
tCS
tWPH
tDH
A0h
Status
DOUT
tRB
PD
Data
tBUSY
RY/BY#
VCC
tVCS
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. DOUT is the output of the data written to the device.
4. Figure indicates last two bus cycles of four bus cycle sequence.
April 2005
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
FIGURE 7: ACCELERATED PROGRAM TIMING DIAGRAM
VHH
VIL or VIH
VIL or VIH
WP#/ACC
tVHH
tVHH
FIGURE 8: CHIP/SECTOR ERASE OPERATION TIMINGS
tWC
tAS
Addresses
2AAh
SA
VA
VA
555h for
tAH
chip erase
CS#
OE#
tCH
tDH
tWP
WE#
tCS
tWHWH2
tWPH
tDS
In
55h
Complete
tRB
30h
10 for Chip Erase
Data
Progress
tBUSY
RY/BY#
VCC
tVCS
NOTES: 1. SA = Sector Address (for Sector Erase), VA = Valid Address for reading status data
April 2005
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
FIGURE 9: BACK TO BACK READ/WRITE CYCLE TIMINGS
tWC
tWC
tRC
tWC
Valid PA
Valid PA
Valid PA
tAH
Valid RA
Addresses
CS#
tCPH
tACC
tCE
tCP
tOE
OE#
WE#
tOEH
tWP
tDS
tGHWL
tDF
tOH
tWPH
tDH
Valid In
Data
Valid In
Valid In
Valid Out
tSR/W
WE# Controlled Write Cycle
Read Cycle
CS# Controlled Write Cycle
FIGURE 10: DATA POLLING TIMINGS (DURING EMBEDDED ALGORITHMS)
tRC
Addresses
CS#
VA
tACC
tCE
VA
VA
tCH
tOE
OE#
WE#
tOEH
tDF
tOH
High Z
High Z
DQ7
Complement
True
True
Valid Data
Complement
Status Data
Valid Data
Status Data
DQ0-DQ6
tBUSY
RY/BY#
NOTE: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
April 2005
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
FIGURE 11: TOGGLE BIT TIMINGS (DURING EMBEDDED ALGORITHMS)
tAHT
tAS
Addresses
tAHT
tASO
CS#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
tOE
Valid
Data
Valid
Status
Valid
Valid
Valid Data
DQ6/DQ2
Status
Status
(Stops Toggling)
(First Read)
(Second Read)
RY/BY#
NOTE: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
FIGURE 12: DQ2 Vs. DQ6
Enter
Erase
Enter Erase
Erase
Embedded
Erasing
Resume
Suspend Program
Suspend
Erase
Erase
Erase Suspend
Read
Erase
Erase Suspend
Read
Erase
WE#
Complete
Suspend
Program
DQ6
DQ2
NOTE: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CS# to toggle DQ2 and DQ6.
April 2005
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
FIGURE 13: SECTOR/SECTOR BLOCK PROTECT AND UNPROTECT TIMING DIAGRAM
VID
VIH
RESET#
SA, A6,
Valid*
Verify
40h
Valid*
Valid*
A1, A0
Sector/Sector Block Protect or Unprotect
Status
60h
60h
Data
Sector/Sector Block Protect: 150 µs
Sector/Sector Block Unprotect: 15 ms
1 µs
CS#
WE#
OE#
NOTE: VA = Valid address, not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
AC CHARACTERISTICS – ALTERNATE CS# CONTROLLED ERASE AND PROGRAM OPERATIONS
Parameter
Speed Options
JEDEC
Std
tWC
tAS
tAH
tDS
Description
Write Cycle Time (1)
Address Setup Time
Address Hold Time
Data Setup Time
Data Hold Time
Read Recovery Time Before Write (OE# High to WE# Low)
WE# Setup Time
WE# Hold Time
90
90
0
45
45
0
0
0
0
35
30
7
4
0.4
100
100
0
45
45
0
0
0
0
45
30
7
4
0.4
120
120
0
50
50
0
0
0
0
50
30
7
4
0.4
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
sec
tAVAV
tAVWL
tELAX
tDVEH
tEHDX
tGHEL
tWLEL
tEHWH
tELEH
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Typ
Typ
Typ
tDH
tGHEL
TWS
tWH
tCP
CS# Pulse Width
tEHEL
tCPH
tWHWH1
tWHWH1
tWHWH2
CS# Pulse Width High
Programming Operation
Accelerated Programming Operation
Sector Erase Operation
tWHWH1
tWHWH1
tWHWH2
NOTE: 1. Not tested.
April 2005
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
FIGURE 14: ALTERNATE CS# CONTROLLED WRITE (ERASE/PROGRAM) OPERATION TIMINGS
555 for Program
2AA for Erase
PA for Program
SA for Sector Erase
555 for Chip Erase
Data# Polling
PA
Addresses
WE#
tAS
t
WC
tAH
tWH
tGHEL
OE#
CS#
t
CP
t
WHWH1 OR 2
t
WS
tCPH
t
BUSY
t
DS
tDH
Data
DQ
7
#
DOUT
tHR
A0 for Program
55 for Erase
PD for Program
30 for Sector Erase
10 for Chip Erase
RESET#
RY/BY#
NOTES:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7 is the complement of the data written to the device. DOUT is the data written to the device.
April 2005
Rev. 0
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
PACKAGE: 159 PBGA
Bottom View
159 X Ø 0.762 (0.030) NOM
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
0.61 (0.024)
NOM
1.27 (0.050) NOM
11.43 (0.450) NOM
13.1 (0.516) MAX
2.03 (0.080) MAX
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES.
April 2005
Rev. 0
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
PACKAGE: 159 PBGA
W 7 2M64 V K XXX B X
WHITE ELECTRONIC DESIGNS CORP.:
Flash:
Organization, 2M x 64:
User Configurable as 2 x 2M x 32
3.3V Power Supply:
Internal Bank Architecture:
K = 4 bank architecture per 2Mx16 die
Access Time (ns):
90 = 90ns
100 = 100ns
120 = 120ns
Package Type:
B = 159 Plastic BGA, 13mm x 22mm
Device Grade:
M = Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
April 2005
Rev. 0
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W72M64VK-XBX
White Electronic Designs
Document Title
2M x 64 Simultaneous Operation Flash Multi-Chip Package
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
April 2005
Final
April 2005
Rev. 0
16
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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