WE128K32N-200G4I [WEDC]
EEPROM,;
| 型号： | WE128K32N-200G4I |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | EEPROM, 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总15页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WE128K32-XXX
HI-RELIABILITY PRODUCT
128Kx32 EEPROM MODULE, SMD 5962-94585
FEATURES
■ Access Times of 120, 140, 150, 200, 250, 300ns
■ Automatic Page Write Operation
■ Page Write Cycle Time: 10ms Max
■ Packaging:
■ Data Polling for End of Write Detection
■ Hardware and Software Data Protection
■ TTL Compatible Inputs and Outputs
■ 5 Volt Power Supply
• 66-pin, PGA Type, 27.3mm (1.075") square, Hermetic
Ceramic HIP (Package 400)
• 68 lead, 40mm CQFP (G4), (Package 501)
• 68 lead, 22.4mm sq. CQFP (G2T), 4.57mm (0.180") high,
(Package 509)
• 68 lead, 22.4mm sq. Low Profile CQFP (G1U), 3.57mm
(0.140") high, (Package 519)
■ Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
■ Weight
■ Organized as 128Kx32; User Configurable as 256Kx16 or 512Kx8
■ Write Endurance 10,000 Cycles
WE128K32-XG2TX - 8 grams typical
WE128K32-XG1UX - 5 grams typical
WE128K32-XH1X - 13 grams typical
WE128K32-XG4X - 20 grams typical
■ Data Retention Ten Years Minimum (at +25°C)
■ Commercial, Industrial and Military Temperature Ranges
■ Low Power CMOS
FIG. 1 PIN CONFIGURATION FOR WE128K32N-XH1X
PIN DESCRIPTION
TOP VIEW
1
12
23
34
45
56
I/O0-31 Data Inputs/Outputs
A0-16
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
I/O
I/O
8
9
WE
CS
2
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
2
CS
4
4
I/O10
GND
I/O11
WE
Output Enable
Power Supply
A
A
A
A
13
14
15
16
A
A
6
7
I/O27
VCC
A
A
A
V
10
11
12
CC
A
A
3
4
5
3
3
A
A
A
0
1
2
GND
NC
Ground
Not Connected
NC
NC
WE
1
A
A
8
9
A
BLOCK DIAGRAM
WE1CS1
WE2CS2
WE3CS3
WE4CS4
NC
I/O
I/O
I/O
I/O
7
WE
CS
I/O23
I/O22
I/O21
I/O20
OE
0-16
A
I/O
I/O
I/O
0
CS
NC
I/O
1
6
I/O16
I/O17
I/O18
128K x 8
128K x 8
128K x 8
128K x 8
1
2
5
4
GND
I/O19
3
8
8
8
8
11
22
33
44
55
66
I/O16-23
I/O24-31
I/O0-7
I/O8-15
Nov 2000 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WE128K32-XXX
FIG. 2 PIN CONFIGURATION FOR WE128K32-XG4X
PIN DESCRIPTION
TOP VIEW
I/O0-31 Data Inputs/Outputs
A0-16
WE
Address Inputs
Write Enables
Chip Selects
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
CS1-4
OE
Output Enable
Power Supply
VCC
GND
NC
Ground
Not Connected
GND
I/O
I/O
8
9
BLOCK DIAGRAM
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS
CS
4
CS
CS
3
1
2
WE
OE
A0-16
128K x 8
128K x 8
128K x 8
128K x 8
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
FIG. 3 PIN CONFIGURATION FOR WE128K32-XG2TX AND WE128K32-XG1UX
TOP VIEW
PIN DESCRIPTION
I/O0-31 Data Inputs/Outputs
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
A0-16
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Output Enable
Power Supply
0.940"
VCC
GND
NC
Ground
GND
The White 68 lead G2T/G1U
CQFP fills the same fit and
function as the JEDEC 68 lead
CQFJ or 68 PLCC. But the G2T/
G1U has the TCE and lead
inspection advantage of the
I/O
I/O
8
9
Not Connected
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
BLOCK DIAGRAM
WE1CS1
WE2CS2
WE3CS3
WE4CS4
CQFP form.
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
OE
0-16
A
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
WE128K32-XXX
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Symbol
Unit
°C
°C
V
CS
H
L
L
X
OE
X
L
H
H
X
WE
X
H
L
X
Mode
Standby
Read
Write
Out Disable
Write
Data I/O
High Z
Data Out
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE and A9
NOTE:
TA
TSTG
VG
-55 to +125
-65 to +150
-0.6 to +6.25
-0.6 to +13.5
Data In
High Z/Data Out
V
X
X
H
X
L
Inhibit
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect
device reliability.
CAPACITANCE
(TA = +25°C)
Parameter
Symbol
COE
Conditions
Max Unit
RECOMMENDED OPERATING CONDITIONS
OE capacitance
V
V
IN = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
50
pF
pF
Parameter
Symbol
VCC
VIH
Min
4.5
Max
5.5
Unit
V
WE1-4 capacitance
HIP (PGA)
CWE
20
50
20
Supply Voltage
CQFP G4
CQFP G2T/G1U
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
2.0
VCC + 0.3
+0.8
V
VIL
-0.5
-55
-40
V
CS1-4 capacitance
CCS
CI/O
CAD
V
IN = 0 V, f = 1.0 MHz
I/O = 0 V, f = 1.0 MHz
IN = 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
TA
+125
+85
°C
°C
Data I/O capacitance
Address input capacitance
V
TA
V
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
Conditions
VCC = 5.5, VIN = GND to VCC
CS = VIH, OE = VIH, VOUT = GND to VCC
CS = VIL, OE = VIH, f = 5MHz
CS = VIH, OE = VIH, f = 5MHz
IOL = 2.1mA, VCC = 4.5V
Min
Max
10
Unit
µA
µA
mA
mA
V
Input Leakage Current
Output Leakage Current
ILI
ILOx32
ICCx32
ISB
10
Operating Supply Current x 32 Mode
Standby Current
250
2.5
0.45
Output Low Voltage
VOL
Output High Voltage
VOH
IOH = -400µA, VCC = 4.5V
2.4
V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
FIG. 4
AC TEST CONDITIONS
AC TEST CIRCUIT
IOL
Parameter
Typ
Unit
V
Current Source
Input Pulse Levels
VIL = 0, VIH = 3.0
Input Rise and Fall
5
ns
V
Input and Output Reference Level
Output Timing Reference Level
1.5
1.5
V
VZ
≈ 1.5V
D.U.T.
(Bipolar Supply)
Ceff = 50 pf
NOTES:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
IOH
Current Source
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WE128K32-XXX
AC WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
WRITE
A write cycle is initiated when OE is high and a low pulse is on WE
or CS with CS or WE low. The address is latched on the falling
edge of CS or WE whichever occurs last. The data is latched by
the rising edge of CS or WE, whichever occurs first. A byte write
operation will automatically continue to completion.
Write Cycle Parameter
Symbol Min
Max Unit
Write Cycle Time, TYP = 6ms
Address Set-up Time
Write Pulse Width (WE or CS)
Chip Select Set-up Time
Address Hold Time
tWC
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAS
tWP
tCS
0
150
0
tAH
100
10
0
WRITE CYCLE TIMING
Data Hold Time
tDH
Figures 5 and 6 show the write cycle timing relationships. A
write cycle begins with address application, write enable and
chip select. Chip select is accomplished by placing the CS line
low. Write enable consists of setting the WE line low. The
write cycle begins when the last of either CS or WE goes low.
Chip Select Hold Time
Data Set-up Time
tCSH
tDS
100
10
10
50
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
tOES
tOEH
tWPH
The WE line transition from high to low also initiates an
internal 150 µsec delay timer to permit page mode operation.
Each subsequent WE transition from high to low that occurs
before the completion of the 150 µsec time out will restart the
timer from zero. The operation of the timer is the same as a
retriggerable one-shot.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
WE128K32-XXX
FIG. 5
WRITE WAVEFORMS
WE CONTROLLED
t
WC
OE
t
t
OEH
OES
ADDRESS
CS 1-4
t
CSH
t
AS
t
AH
t
CS
WE 1-4
t
WP
t
WPH
DH
t
t
DS
DATA IN
FIG. 6
WRITE WAVEFORMS
CS CONTROLLED
t
WC
OE
t
t
OEH
OES
ADDRESS
WE1 - 4
t
CSH
t
t
AS
AH
t
CS
CS1 - 4
t
WP
t
WPH
DH
t
t
DS
DATA IN
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WE128K32-XXX
READ
The WE128K32-XXX stores data at the memory location
determined by the address pins. When CS and OE are low and
WE is high, this data is present on the outputs. When CS and
OE are high, the outputs are in a high impedance state. This
two line control prevents bus contention.
AC READ CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Read Cycle Parameter
Symbol
-120
-140
-150
-200
-250
Min Max
-300
Min Max
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
tACC
tACS
tOH
tOE
120
140
150
200
250
250
250
0
300
300
300
0
ns
ns
ns
ns
ns
ns
Address Access Time
120
120
140
140
150
150
200
200
Chip Select Access Time
Output Hold from Add. Change, OE or CS
Output Enable to Output Valid
Chip Select or OE to High Z Output
0
0
0
0
0
0
0
0
50
70
55
70
55
70
55
70
0
85
70
0
85
70
tDF
FIG. 7
READ WAVEFORMS
t
RC
ADDRESS VALID
ADDRESS
CS1-4
t
ACS
t
OE
OE
t
DF
t
ACC
t
OH
NOTES:
HIGH Z
OUTPUT
VALID
OE may be delayed up to tACS - tOE after the
falling edge of CS without impact on tOE or by
tACC - tOE after an address change without
impact on tACC.
OUTPUT
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6
WE128K32-XXX
DATA POLLING
The WE128K32-XXX offers a data polling feature which allows
a faster method of writing to the device. Figure 8 shows the
timing diagram for this function. During a byte or page write
cycle, an attempted read of the last byte written will result in
the complement of the written data on D7 (for each chip.) Once
the write cycle has been completed, true data is valid on all
outputs and the next cycle may begin. Data polling may begin
at any time during the write cycle.
DATA POLLING CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
Parameter
Symbol
tDH
Min Max Unit
Data Hold Time
OE Hold Time
10
10
ns
ns
ns
ns
tOEH
tOE
OE To Output Valid
Write Recovery Time
55
tWR
0
FIG. 8
DATA POLLING
WAVEFORMS
WE1-4
CS1-4
OE
tOEH
tOE
tDH
I/O
7
HIGH Z
tWR
ADDRESS
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WE128K32-XXX
PAGE WRITE CHARACTERISTICS
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
PAGE WRITE OPERATION
The WE128K32-XXX has a page write operation that allows one to
128 bytes of data to be written into the device and consecutively
loads during the internal programming period. Successive bytes
may be loaded in the same manner after the first data byte has
been loaded. An internal timer begins a time out operation at each
write cycle. If another write cycle is completed within 150µs or
less, a new time out period begins. Each write cycle restarts the
delay period. The write cycles can be continued as long as the
interval is less than the time out period.
Page Mode Write Characteristics
Symbol
Unit
Parameter
Min Max
Write Cycle Time, TYP = 6ms
Address Set-up Time
Address Hold Time (1)
Data Set-up Time
tWC
tAS
10
ms
ns
ns
ns
ns
ns
µs
ns
0
tAH
100
100
10
tDS
Data Hold Time
tDH
Write Pulse Width
tWP
tBLC
tWPH
150
150
50
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In this
manner a page of up to 128 bytes can be loaded in to the
EEPROM in a burst mode before beginning the relatively long
interval programming cycle.
Byte Load Cycle Time
Write Pulse Width High
1. Page address must remain valid for duration of write cycle.
After the 150µs time out is completed, the EEPROM begins an
internal write cycle. During this cycle the entire page of bytes
will be written at the same time. The internal programming
cycle is the same regardless of the number of bytes accessed.
FIG. 9
PAGE MODE
WRITE WAVEFORMS
OE
CS
x
tWP
tWPH
tBLC
WE
x
tAS
tAH
VALID
ADDRESS
ADDRESS
DATA
tDS
tWC
tDH
VALID DATA
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 127
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
8
WE128K32-XXX
FIG. 10
SOFTWARE DATA PROTECTION
ENABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
WRITES ENABLED(2)
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
ENTER DATA
PROTECT STATE
NOTES:
1. Data Format: D7 - D0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WE128K32-XXX
SOFTWARE DATA PROTECTION
FIG. 11
A software write protection feature may be enabled or disabled
by the user. When shipped by White Microelectronics, the WE-
128K32-XXX has the feature disabled. Write access to the
device is unrestricted.
SOFTWARE DATA PROTECTION
(1)
DISABLE ALGORITHM
To enable software write protection, the user writes three
access code bytes to three special internal locations. Once
write protection has been enabled, each write to the EEPROM
must use the same three byte write sequence to permit writing.
After setting software data protection, any attempt to write to
the device without the three-byte command sequence will start
the internal write timers. No data will be written to the device,
however, for the duration of tWC. The write protection feature
can be disabled by a six byte write sequence of specific data to
specific locations. Power transitions will not reset the
software write protection.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
Each 128K byte block of the EEPROM has independent write
protection. One or more blocks may be enabled and the rest
disabled in any combination. The software write protection
guards against inadvertent writes during power transitions, or
unauthorized modification using a PROM programmer.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WE128K32-XXX. These are included to improve reliability
during normal operation:
LOAD DATA 20
TO
(3)
ADDRESS 5555
EXIT DATA
PROTECT STATE
LOAD DATA XX
TO
a) VCC power on delay
As VCC climbs past 3.8V typical the device will wait 5msec
typical before allowing write cycles.
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
b) VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE low and either CS or WE high inhibits write
cycles.
d) Noise filter
Pulses of <8ns (typ) on WE or CS will not initiate a write
cycle.
NOTES:
1. Data Format: D7 - D0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other
data is loaded.
3. Write Protect state will be deactivated at end of write period even if
no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
10
WE128K32-XXX
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
27.3 (1.075) ± 0.25 (0.010) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
4.34 (0.171)
MAX
3.81 (0.150)
± 0.13 (0.005)
1.42 (0.056) ± 0.13 (0.005)
0.76 (0.030) ± 0.13 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
0.46 (0.018) ± 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)
30.1 (1.185) ± 0.38 (0.015) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
6.22 (0.245)
MAX
3.81 (0.150)
± 0.1 (0.005)
1.27 (0.050) ± 0.1 (0.005)
0.76 (0.030) ± 0.1 (0.005)
2.54 (0.100)
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
TYP
0.46 (0.018) ± 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WE128K32-XXX
PACKAGE 501: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G4)
5.1 (0.200) MAX
39.6 (1.56) ± 0.38 (0.015) SQ
1.27 (0.050)
± 0.1 (0.005)
PIN 1 IDENTIFIER
Pin 1
12.7 (0.500)
± 0.5 (0.020)
4 PLACES
5.1 (0.200)
± 0.25 (0.010)
4 PLACES
0.25 (0.010)
± 0.05 (0.002)
1.27 (0.050)
TYP
0.38 (0.015)
± 0.08 (0.003)
68 PLACES
38 (1.50) TYP
4 PLACES
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
25.15 (0.990) ± 0.26 (0.010) SQ
22.36 (0.880) ± 0.26 (0.010) SQ
4.57 (0.180) MAX
0.27 (0.011) ± 0.04 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
(0.010)
24.03 (0.946)
± 0.26 (0.010)
0.19 (0.007)
± 0.06 (0.002)
1° / 7°
1.0 (0.040)
± 0.127 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G2T CQFP fills the same fit
and function as the JEDEC 68 lead CQFJ or 68
PLCC. But the G2T has the TCE and lead
inspection advantage of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
12
WE128K32-XXX
PACKAGE 519: 68 LEAD, CERAMIC QUAD FLAT PACK, LOW PROFILE CQFP (G1U)
25.27 (0.995) ± 0.13 (0.005) SQ
3.56 (0.140) MAX
23.88 (0.940) ± 0.25 (0.010) SQ
0.25 (0.010)
0.61 (0.024)
± 0.15 (0.006)
0.84 (0.033) REF
DETAIL A
SEE DETAIL "A"
1.27 (0.050)
0.38 (0.015) ± 0.05 (0.002)
20.3 (0.800) REF
The White 68 lead G1U CQFP
fills the same fit and function as
the JEDEC 68 lead CQFJ or 68
PLCC. But the G1U has the TCE
and lead inspection advantage
of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WE128K32-XXX
FIG. 12 ALTERNATE PIN CONFIGURATION FOR WE128K32NP-XH1X
PIN DESCRIPTION
TOP VIEW
1
12
23
34
45
56
I/O0-31 Data Inputs/Outputs
A0-16
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
I/O
I/O
8
9
WE
CS
2
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
2
CS
4
I/O10
GND
I/O11
WE
4
A
A
A
A
14
16
11
0
A
7
I/O27
VCC
A
A
A
V
10
9
A
12
A
4
5
6
3
3
A
A
A
1
2
3
GND
NC
NC
NC
A
Not Connected
BLOCK DIAGRAM
WE1CS1
WE2CS2
WE3CS3
WE4CS4
15
CC
WE1
A13
A
OE
0-16
A
NC
I/O
I/O
I/O
I/O
7
A
8
WE
CS
I/O23
I/O22
I/O21
I/O20
128K x 8
128K x 8
128K x 8
128K x 8
I/O
I/O
I/O
0
CS
NC
I/O
1
6
I/O16
I/O17
I/O18
1
2
5
4
GND
I/O19
8
8
8
8
3
I/O16-23
I/O24-31
I/O0-7
I/O8-15
11
22
33
44
55
66
ORDERING INFORMATION
W E 128K32 X - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
Q = Compliant
M = Military Screened -55°C to +125°C
I
= Industrial
-40°C to +85°C
0°C to +70°C
C = Commercial
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400*)
G2T = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 509)
G1U = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 519)
G4 = 40mm Ceramic Quad Flat Pack, CQFP (Package 501)
ACCESS TIME (ns)
IMPROVEMENT MARK
N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade
P = Alternate Pin Configuration for HIP package
ORGANIZATION 128K x 32
User Configurable as 256K x 16 or 512K x 8
EEPROM
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
14
WE128K32-XXX
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
300ns
250ns
200ns
150ns
140ns
120ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-94585 01H5X
5962-94585 02H5X
5962-94585 03H5X
5962-94585 04H5X
5962-94585 05H5X
5962-94585 06H5X
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
300ns
250ns
200ns
150ns
140ns
120ns
66 pin HIP (H1, P type pinout)
66 pin HIP (H1, P type pinout)
66 pin HIP (H1, P type pinout)
66 pin HIP (H1, P type pinout)
66 pin HIP (H1, P type pinout)
66 pin HIP (H1, P type pinout)
5962-94585 01H6X
5962-94585 02H6X
5962-94585 03H6X
5962-94585 04H6X
5962-94585 05H6X
5962-94585 06H6X
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
300ns
250ns
200ns
150ns
140ns
120ns
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
5962-94585 01HMX
5962-94585 02HMX
5962-94585 03HMX
5962-94585 04HMX
5962-94585 05HMX
5962-94585 06HMX
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
300ns
250ns
200ns
150ns
140ns
120ns
68 lead CQFP (G4)
68 lead CQFP (G4)
68 lead CQFP (G4)
68 lead CQFP (G4)
68 lead CQFP (G4)
68 lead CQFP (G4)
5962-94585 01HNX
5962-94585 02HNX
5962-94585 03HNX
5962-94585 04HNX
5962-94585 05HNX
5962-94585 06HNX
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
300ns
250ns
200ns
150ns
140ns
120ns
68 lead CQFP (G1U)
68 lead CQFP (G1U)
68 lead CQFP (G1U)
68 lead CQFP (G1U)
68 lead CQFP (G1U)
68 lead CQFP (G1U)
5962-94585 01H9X
5962-94585 02H9X
5962-94585 03H9X
5962-94585 04H9X
5962-94585 05H9X
5962-94585 06H9X
15
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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