WED3DG6435V10AD1 [WEDC]
256MB - 32Mx64 SDRAM UNBUFFERED; 256MB - 32Mx64 SDRAM UNBUFFERED
| 型号： | WED3DG6435V10AD1 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 256MB - 32Mx64 SDRAM UNBUFFERED |
| 文件： | 总7页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED3DG6435V-AD1
White Electronic Designs
256MB – 32Mx64 SDRAM UNBUFFERED
FEATURES
DESCRIPTION
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ꢀ
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ꢀ
ꢀ
PC100 and PC133 compatible
The WED3DG6435V is a 32Mx64 synchronous DRAM
module which consists of eight 32Mx8 SDRAM components
in TSOP II package, and one 2Kb EEPROM in an 8
pin TSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
* This product is subject to change without notice.
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Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
NOTE: Consult factory for availability of:
• RoHS compliant products
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3.3V 0.3V Power Supply
144 Pin SO-DIMM
• Vendor source control options
• Industrial temperature option
• Ultra-low package height:
AD1: 27.94 mm (1.1”) MAX
• Because of the low package height, there are no
termination resistors.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
PINOUT
A0 – A12
BA0-1
DQ0-63
CK0, CK1
CKE0
CS0
Address Input (Multiplexed)
PIN FRONT PIN
BACK
VSS
PIN FRONT PIN
BACK
DQ45
DQ46
DQ47
VSS
NC
NC
CKE0
VCC
CAS#
NC
A12
NC
CK1
VSS
NC
PIN
97
99
BACK
DQ22
DQ23
VCC
A6
A8
VSS
A9
A10
VCC
DQMB2
DQMB3
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
PIN
98
BACK
DQ54
DQ55
VCC
A7
BA0
VSS
BA1
A11
VCC
DQMB6
DQMB7
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
Select Bank
1
3
5
7
VSS
DQ0
DQ1
DQ2
DQ3
VCC
2
4
6
8
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
DQ13
DQ14
DQ15
VSS
NC
NC
CK0
VCC
RAS#
WE#
CS0#
NC
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
Data Input/Output
Clock Input
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
VSS
DQMB4
DQMB5
VCC
A3
A4
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
RAS#
CAS#
WE#
DQ4
DQ5
DQ6
DQ7
VSS
DQMB0
DQMB1
VCC
A0
A1
A2
VSS
DQ8
DQ9
DQ10
DQ11
VCC
DQMB0-7
VCC
DQM
Power Supply (3.3V)
Ground
NC
VSS
NC
NC
VSS
SDA
Serial Data I/O
Serial Clock
SCL
NC
VCC
DNU
Do Not Use
A5
VSS
VCC
DQ16
DQ17
DQ18
DQ19
VSS
DQ48
DQ49
DQ50
DQ51
VSS
NC
No Connect
DQ40
DQ41
DQ42
DQ43
VCC
** These pins should be NC in the system which
does not support SPD.
DQ20
DQ21
DQ52
DQ53
SDA
VCC
SCL
VCC
DQ12
DQ44
July 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG6435V-AD1
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
WE#
S0#
DQMB0
DQMB4
DQ32
DQM
S0#
WE#
DQM
S0#
WE#
DQ0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB1
DQMB5
S0#
WE#
S0#
WE#
DQM
DQM
DQ8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB2
DQMB6
S0#
WE#
S0#
WE#
DQM
DQM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB3
DQMB7
DQM
S0#
WE#
DQM
S0#
WE#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
NOTE: DQ writing may differ than described in this drawing,
however DQ/DQMB/CKE/S relationships must be
maintained as shown.
RAS#
CAS#
CKE0
BA0-BA1
A0-A12
RAS#: SDRAM
CAS#: SDRAM
CKE0: SDRAM
BA0-BA1: SDRAM
A0-A12: SDRAM
*CLOCK WIRING
CLOCK
SDRAMS
INPUT
*CK0
*CK1
4 - SDRAMS
4 - SDRAMS
*Wire per Clock Loading Table/Wiring Diagrams
SERIAL PD
VCC
VSS
SDRAM
SDRAM
SDA
SCL
A1
A2
A0
July 2005
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG6435V-AD1
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
9
Units
V
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
V
°C
W
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C
Parameter
Symbol
VCC
VIH
Min
3.0
2.0
-0.3
2.4
—
Typ
3.3
3.0
—
Max
3.6
Unit
V
Note
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
VCCQ+0.3
0.8
V
1
2
VIL
V
VOH
VOL
ILI
—
—
V
IOH= -2mA
IOL= -2mA
3
—
0.4
V
-10
—
10
µA
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VCCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV
Parameter
Symbol
CIN1
Max
36
36
36
16
36
7
Unit
Input Capacitance (A0-A12)
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
CIN2
CIN3
Input Capacitance (CK0)
CIN4
Input Capacitance (CS0#)
CIN5
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data Input/Output Capacitance (DQ0-DQ63)
CIN6
CIN7
36
10
COUT
July 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG6435V-AD1
White Electronic Designs
OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V, TA = 0°C to +70°C
Version
Parameter
Symbol
Conditions
100/133
Units
Note
Operating Current
(One bank active)
ICC1
Burst Length = 1
tRC ≤ tRC(min)
IOL = 0mA
mA
1
1080
Precharge Standby Current
in Power Down Mode
ICC2P
ICC3N
ICC4
mA
mA
CKE ≤ VIL(max), tCC = 10ns
16
Active Standby Current in
Non-Power Down Mode
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns Input
signals are changed one time during 20ns
360
Io = mA
Page burst
4 Banks activated
tCCD = 2CK
Operating Current (Burst mode)
1,200
mA
1
2
Refresh Current
ICC5
ICC6
2,280
24
mA
mA
tRC ≥ tRC(min)
CKE ≤ 0.2V
Self Refresh Current
Notes:
1.
2.
Measured with outputs open.
Refresh period is 64ms.
July 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG6435V-AD1
White Electronic Designs
AC TIMING PARAMETERS
Speed Grade
100MHz
Speed Grade
133MHz
Symbol Parameter
Min
10
3
3
2
2
1
1
Max
Min
7.5
2.5
2.5
1.5
1.5
0.8
0.8
Max
Units
ns
ns
ns
ns
ns
ns
ns
Notes
tCK
tCH
tCL
tIS
Clock Period
Clock High Time Rated @1.5V
Clock Low Time
Input Setup Times
Address/ Command & CKE
Data
Address/Command & CKE
Data
tIH
Input Hold Times
tAC
Output Valid From Clock
CAS# Latency = 2 or 3,
LVTTL levels, Rated @ 50
pF all outputs switching
6.0
(tco = 5.2)
5.4
(tco = 4.6)
ns
1
tOH
tOHZ
tCCD
tCBD
tCKE
tRP
tRAS
tRCD
tRRD
tRC
tDQD
tDWD
tMRD
tROH
tDQZ
tDQM
tDPL
tDAL
tSB
tSRX
tPDE
tCKSTP
tREF
tRFC
Output Hold From Clock Rated @ 50 pF (1.8 ns @ 0 pf)
Output Valid to Z
CAS to CAS Delay
CAS Bank Delay
CKE to Clock Disable
RAS Precharge Time
RAS Active Time
Activate to Command Delay (RAS to CAS Delay)
RAS to RAS Bank Activate Delay
RAS Cycle Time
3
3
1
1
1
20
50
20
20
70
0
2.7
2.7
1
1
1
20
45
20
15
67.5
0
ns
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
tCK
tCK
ns
9
7
DQM to Input Data Delay
Write Cmd. to Input Data Delay
Mode Register set to Active delay
Precharge to O/P in High Z
DQM to Data in High Z for read
DQM to Data mask for write
Data-in to PRE Command Period
Data-in to ACT (PRE) Command period (Auto precharge)
Power Down Mode Entry
0
3
0
3
CL
CL
2
3
2
0
20
5
2
0
15
5
1
1
Self Refresh Exit Time
10
1
200
10
1
200
4
5
6
Power Down Exit Set up Time
Clock Stop During Self Refresh or Power Down
Refresh Period
tCK
tCK
ms
ns
64
64
Row Refresh Cycle Time
80.0
75.0
1.
2.
3.
4.
5.
6.
Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load.
CL = CAS Latency
Data Masked on the same clock
Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC.
Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle.
If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high.
July 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG6435V-AD1
White Electronic Designs
PACKAGE DIMENSIONS FOR AD1
Ordering Information
WED3DG6435V10AD1
WED3DG6435V7AD1
WED3DG6435V75AD1
Speed
100MHz
133MHz
133MHz
CAS Latency
CL=2
Height*
27.94 (1.1”) MAX
27.94 (1.1”) MAX
27.94 (1.1”) MAX
CL=2
CL=3
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR AD1
67.72
(2.661 Max)
3.81
2.01 (0.079 Min)
(0.150)
MAX.
27.94
(1.1)
Max
3.99
(0.157)
19.99
(0.787)
0.99
(0.039)
0.004)
32.79
(1.291)
(
23.14
(0.913)
4.60 (0.181)
28.2
(1.112)
1.50 (0.059)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
July 2005
Rev. 3
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED3DG6435V-AD1
White Electronic Designs
Document Title
256MB – 32Mx64 SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date Status
Rev 0
Created
9-7-04
Preliminary
Rev 1
1.1 Added timing parameters
9-04
Final
1.2 Moved from Preliminary to Final
Rev 2
Rev 3
2.1 Added RoHS compliant notification
2.2 Added industrial temperature option
2.3 Provide source control options
7-05
7-05
Final
Final
3.1 Added “ED” to part number
July 2005
Rev. 3
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
WED3DG6435V10D1-GG
Synchronous DRAM Module, 32MX8, 5.4ns, CMOS, ROHS COMPLIANT, SODIMM-144
MICROSEMI
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