WED3DG644V10WD1-S [WEDC]
Synchronous DRAM Module, 4MX64, CMOS, SODIMM-144;
| 型号： | WED3DG644V10WD1-S |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Synchronous DRAM Module, 4MX64, CMOS, SODIMM-144 动态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED3DG644V-D1
White Electronic Designs
32MB – 4Mx64 SDRAM, UNBUFFERED
FEATURES
DESCRIPTION
PC100 and PC133 compatible
The WED3DG644V is a 4Mx64 synchronous DRAM
module which consists of four 4Mx16 SDRAM components
in TSOP II package, and one 2Kb EEPROM in an 8
pin TSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
* This product is subject to change without notice.
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
3.3V ± 0.3V Power Supply
144 Pin SO-DIMM JEDEC
• D1: 27.94 (1.10”)
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
A0 – A11
BA0-1
DQ0-63
CLK0
CKE0
CS0#
RAS#
CAS#
WE#
DQM0-7
VCC
VSS
*VREF
SDA
SCL
Address input (Multiplexed)
Select Bank
Data Input/Output
Clock input
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
Power supply for reference
Serial data I/O
Serial clock
Pin Front Pin Back Pin Front Pin Back Pin Back Pin Back
1
3
5
7
9
11
13
15
17
19
21
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
VSS
2
4
6
8
VSS
51 DQ14 52 DQ46 95 DQ21 96 DQ53
DQ32 53 DQ15 54 DQ47 97 DQ22 98 DQ54
DQ33 55
DQ34 57
VSS
NC
NC
56
58
60
VSSv
NC
NC
99 DQ23 100 DQ55
101 VCC 102 VCC
10 DQ35 59
12 VCC
14 DQ36
16 DQ37
103
105
A6
A8
104
106 BA0
A7
107 VSS 108 VSS
109 A9 110 BA1
VOLTAGE KEY
18 DQ38 61 CLK0 62 CKE0 111 A10/AP 112 A11
20 DQ39 63 VCC 64 VCC 113 VCC 114 VCC
22 VSS 65 RAS# 66 CAS# 115 DQM2 116 DQM6
23 DQM0 24 DQM4 67 WE# 68 *CKE1 117 DQM3 118 DQM7
25 DQM1 26 DQM5 69 CS0# 70 *A12 119 VSS 120 VSS
DNU
NC
Do not use
No Connect
27
29
31
33
35
37
39
VCC
A0
A1
28
30
32
34
36
VCC
A3
A4
A5
VSS
71 *CS1# 72 *A13 121 DQ24 122 DQ56
73 DNU 74 *CK1 123 DQ25 124 DQ57
75
77
79
VSS
NC
NC
VCC
76
78
80
82
VSS 125 DQ26 126 DQ58
*
These pins are not used in this module.
A2
NC
NC
127 DQ27 128 DQ59
129 VCC 130 VCC
** These pins should be NC in the system
which does not support SPD.
VSS
DQ8
DQ9
38 DQ40 81
VCC 131 DQ28 132 DQ60
40 DQ41 83 DQ16 84 DQ48 133 DQ29 134 DQ61
41 DQ10 42 DQ42 85 DQ17 86 DQ49 135 DQ30 136 DQ62
43 DQ11 44 DQ43 87 DQ18 88 DQ50 137 DQ31 138 DQ63
45
47 DQ12 48 DQ44 91
49 DQ13 50 DQ45 93 DQ20 94 DQ52 143 VCC 144 VCC
VCC
46
VCC
89 DQ19 90 DQ51 139 VSS 140 VSS
VSS 92 VSS 141 **SDA 142 **SCL
September 2007
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG644V-D1
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQM0
DQM4
CS#
CS#
LDQM
LDQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ32
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ6
DQ7
DQ6
DQ7
DQM1
UDQM
DQM5
UDQM
DQ8
DQ9
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ14
DQ15
DQ14
DQ15
DQM2
DQM6
LDQM
CS#
LDQM
CS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM3
UDQM
DQM7
UDQM
DQ8
DQ8
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
SERIAL PD
A0
A0-A11
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
BA0
RAS#
CAS#
WE#
SCL
WP
SDA
A1 A2
CKE0
47Ω
10Ω
10Ω
SDRAM
V
V
CC
TWO 0.1 uF CAPACITORS
PER EACH SDRAM
CLK0
SDRAM
SDRAM
SDRAM
To all SDRAMS
CC
Notes: D1 option does not have series resistors.
September 2007
Rev. 5
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG644V-D1
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
Voltage on VCC supply relative to VSS
Storage Temperature
VIN, VOUT
VCC, VCCQ
TSTG
-1.0 ~ 4.6
-1.0 ~ 4.6
V
V
-55 ~ +150
°C
W
Power Dissipation
PD
4
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C
Parameter
Symbol
VCC
VIH
Min
3.0
2.0
-0.3
2.4
—
Typ
3.3
3.0
—
Max
3.6
Unit
V
Note
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
VCCQ+0.3
0.8
V
1
2
VIL
V
VOH
VOL
ILI
—
—
V
IOH= -2mA
IOL= -2mA
3
—
0.4
V
-10
—
10
μA
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VCCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-State outputs.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 3.3V, VREF = 1.4V ± 200mV
Parameter
Symbol
CIN1
Max
25
25
25
19
25
8
Unit
Input Capacitance (A0-A12)
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
CIN2
CIN3
Input Capacitance (CLK0)
CIN4
Input Capacitance (CS0#)
CIN5
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data Input/Output Capacitance (DQ0-DQ63)
CIN6
CIN7
25
10
COUT
September 2007
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG644V-D1
White Electronic Designs
OPERATING CURRENT CHARACTERISTICS
(VCC = 3.3V, TA = 0°C to +70°C)
Version
Parameter
Symbol
Conditions
Units
mA
Note
133/100
Burst Length = 1
tRC tRC(min)
300
Operating Current
(One bank active)
ICC1
1
I
OL = 0mA
ICC2P
CKE VIL(max), tCC = 10ns
4
4
Precharge Standby Current
in Power Down Mode
mA
ICC2PS
CKE & CLK VIL(max), tCC = ∞
CKE VIH(min), CS VIH(min), tcc =10ns
Input signals are charged one time during 20
ICC2N
48
24
Precharge Standby Current
in Non-Power Down Mode
CKE VIH(min), CLK VIL(max), tCC = ∞
Input signals are stable
mA
mA
ICC2NS
ICC3P
CKE VIL(max), tCC = 10ns
8
8
Active Standby Current in
Power-Down Mode
ICC3PS
CKE & CLK VIL(max), tCC = ∞
CKE VIH(min), CS VIH(min), tcc = 10ns
Input signals are changed one time during 20ns
ICC3N
80
40
mA
mA
Active Standby Current in
Non-Power Down Mode
CKE VIH(min), CLK VIL(max), tcc = ∞
Input signals are stable
ICC3NS
Io = mA
Page burst
4 Banks activated
tCCD = 2CLK
ICC4
460
mA
1
2
Operating Current (Burst mode)
Refresh Current
ICC5
ICC6
tRC tRC(min)
CKE 0.2V
360
4
mA
mA
Self Refresh Current
Notes:
1.
2.
Measured with outputs open.
Refresh period is 64ms.
September 2007
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG644V-D1
White Electronic Designs
AC OPERATING TEST CONDITIONS
VCC = 3.3V ± 0.3V, 0 ≤ TA ≤ 70°C
Parameter
Value
Unit
V
AC input levels (VIH/VIL)
2.4/0.4
1.4
Input timing measurement reference level
Input rise and fall time
V
tR/tF = 1/1
1.4
ns
V
Output timing measurement reference level
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
7.5, 10
Row active to row active delay
RAS# to CAS# delay
tRRD (min)
tRCD (min)
15
ns
ns
1
1
1
1
20
Row precharge time
t
RP (min)
20
ns
tRAS (min)
45
ns
Row active time
t
RAS (max)
tRC (min)
tRDL (min)
100
us
Row cycle time
65
ns
1
2
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
2
CLK
—
t
DAL (min)
2 CLK + tRP
t
CDL (min)
1
1
1
2
1
CLK
CLK
CLK
2
2
3
tBDL (min)
tCCD (min)
Col. address to col. address delay
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
Notes :
1.
2.
3.
4.
The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
Minimum delay is required to complete write.
All parts allow every cycle column address change.
In case of row precharge interrupt, auto precharge and read burst stop.
September 2007
Rev. 5
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG644V-D1
White Electronic Designs
ORDERING INFORMATION FOR D1
Part Number
Clock Speed
100MHz
CAS Latency
CL=2
Height*
WED3DG644V10WD1x-xx
WED3DG644V7WD1x-xx
WED3DG644V75WD1x-xx
27.94 (1.100”)
27.94 (1.100”)
27.94 (1.100”)
133MHz
CL=2
133MHz
CL=3
NOTES:
• Consult Factory for availability of RoHS products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is
to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
• WD1: Includes the write protected EPROM option
PACKAGE DIMENSIONS FOR D1
67.74 (2.667ꢀ MAX
3.81
(0.150ꢀ
TYP
2.01 (0.079ꢀ MIN
3.99
(0.157ꢀ
27.94
(1.100ꢀ
MAX
3.99
(0.157ꢀ
MIN
19.99
(0.787ꢀ
3.20
(0.126ꢀ
MIN
32.79 (1.291ꢀ
23.19
(0.913ꢀ
4.60 (0.181ꢀ
1.50 (0.059ꢀ
0.99 0.10
28.24
(0.039 0.004ꢀ
(1.112ꢀ
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
September 2007
Rev. 5
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG644V-D1
White Electronic Designs
ORDERING INFORMATION FOR D1
Part Number
Clock Speed
100MHz
CAS Latency
CL=2
Height*
WED3DG644V10D1x-xx
WED3DG644V7D1x-xx
WED3DG644V75D1x-xx
27.94 (1.100”)
27.94 (1.100”)
27.94 (1.100”)
133MHz
CL=2
133MHz
CL=3
NOTES:
• Consult Factory for availability of RoHS products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “-x” in the part numbers above and is
to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D1
67.74 (2.667ꢀ MAX
3.81
(0.150ꢀ
TYP
2.01 (0.079ꢀ MIN
3.99
(0.157ꢀ
27.94
(1.100ꢀ
MAX
3.99
(0.157ꢀ
MIN
19.99
(0.787ꢀ
3.20
(0.126ꢀ
MIN
32.79 (1.291ꢀ
23.19
(0.913ꢀ
4.60 (0.181ꢀ
1.50 (0.059ꢀ
0.99 0.10
28.24
(0.039 0.004ꢀ
(1.112ꢀ
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
September 2007
Rev. 5
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG644V-D1
White Electronic Designs
PART NUMBERING GUIDE
WED 3 D G 64 4 V xxx x D1 x -x G
WEDC
MEMORY (SDRAM)
SDRAM
GOLD
DEPTH x64
DENSITY
3.3 Volts
CLOCK SPEED (MHz)
WRITE PROTECTION OPTION
W = write procted SPD
EEPROM
Blank = standard
PACKAGE D1 = 144 PIN SO-DIMM
INDUSTRIAL TEMP OPTION
(For commercial leave "blank" for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
(For non-compliant "blank" for RoHS add “G”)
September 2007
Rev. 5
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WED3DG644V-D1
White Electronic Designs
Document Title
32MB – 4Mx64 SDRAM, UNBUFFERED
DRAM DIE OPTIONS:
• SAMSUNG: K-Die
• MICRON: Y14W:G
Revision History
Rev #
History
Release Date Status
Rev A
Rev 0
Rev 1
Rev 2
Created
11-15-01
9-6-02
6-04
Advanced
Final
Changed from Advanced to Final
1.1 Updated CAP and IDD specs
Final
2.1 Added RoHS and lead-free notes
2.2 Added vendor source and industrial tem notes
2.3 Added part number matrix
1-06
Final
Rev 3
3.1 Updated part number guide
6-06
Final
3.2 Updated “ordering information” part number
3.3 Added DRAM die options
Rev 4
Rev 5
4.1 Added “write protect option”
6-07
9-07
Final
Final
5.1 Removed termination resistors because it was added in
error
5.2 Updated block diagram
September 2007
Rev. 5
9
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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