WED3DG7265V75D2 [WEDC]
Synchronous DRAM Module, 64MX72, CMOS, DIMM-168;
| 型号： | WED3DG7265V75D2 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Synchronous DRAM Module, 64MX72, CMOS, DIMM-168 动态存储器 |
| 文件： | 总6页 (文件大小：453K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED3DG7265V-D2
512MB- 64Mx72 SDRAM UNBUFFERED
FEATURES
DESCRIPTION
n Burst Mode Operation
The WED3DG7265V is a 64Mx72 synchronous DRAM module
which consists of nine 64Mx 8 SDRAM components in TSOP- 11
package, and one 2K EEPROM in an 8- pin TSSOP package for
Serial Presence Detect which are mounted on a 168 Pin DIMM
multilayer FR4 Substrate.
n Auto and Self Refresh capability
n LVTTL compatible inputs and outputs
n Serial Presence Detect with EEPROM
n Fully synchronous: All signals are registered on the positive
edge of the system clock
n Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
n 3.3 volt 6 0.3v Power Supply
*
This datasheet describes a product that may or may not be under development
and is subject to change or cancellation without notice.
n 168- Pin DIMM JEDEC
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
Pin
1
2
Front
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VDD
DQ14
DQ15
CB0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
CS0
DNU
VSS
A0
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
VDD
DQ20
NC
*VREF
*CKE1
VSS
Pin
85
86
Back
VSS
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
Back
DQM5
*CS1
RAS
VSS
A1
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
Back
DQ50
DQ51
VDD
DQ52
NC
*VREF
NC
VSS
A0
A12Address
input
(Multi
Input
BA0-1
DQ0-63
CB0-7
Select Bank
Data Input/Output
DQ32
DQ33
DQ34
DQ35
VDD
3
4
87
88
Check bit (Data-in/data-out)
CLK0,CLK2Clock
Clock Enable input
CS0,CS2Chip
input
5
6
89
90
CKE0
A2
A3
select
7
8
A4
A6
91
92
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VDD
A5
A7
RAS
CAS
WE
DQM0-7
VDD
VSS
*VREF
SDA
Row Address Strobe
ColumnAddress Strobe
Write Enable
9
A8
A10/AP
BA1
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VDD
93
94
A9
BA0
A11
VDD
*CLK1
A12
VSS
CKE0
*CS3
DQM6
DQM7
*A13
VDD
NC
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VDD
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
95
96
97
DQM
Power Supply (3.3V)
Ground
VDD
VDD
CLK0
VSS
DNU
CS2
DQM2
DQM3
DNU
VDD
NC
98
99
Power supply for reference
Serial data I/O
100
101
102
103
104
105
106
107
108
109
SCL
Serial clock
SA0-2Address
Do not use
No Connect
DQ28
DQ29
DQ30
DQ31
VSS
DQ60
DQ61
DQ62
DQ63
VSS
in
EEPR
DQ46
DQ47
CB4
DNU
NC
CB1
VSS
NC
CB5
VSS
NC
NC
CLK2
NC
NC
CB6
CB7
*CLK3
NC
CB2
CB3
VSS
DQ16
DQ17
*
These pins are not used in this module.
NC
VDD
WE
NC
NC
**SA0
** These pins should be NC in the system which
does not support SPD.
**SDA110
**SCL
VDD
VDD
138
VSS
166 1 **SA
111
112
CAS
DQM4
139
140
DQ48
DQ49
167
168
**SA2
VDD
DQM0
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15459
1
WED3DG7265V-D2
FUNCTIONAL BLOCK DIAGRAM
CS0
DQM0
·
DQM4
DQM
DQM
CS
CS
U0
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
U5
DQM1
DQM5
DQM
DQM
CS
U6
CS
U1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM6
DQM
CS
U2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM
CS
U7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
·
CS2
DQM2
DQM7
DQM
CS
U3
DQM
CS
U8
Serial PD
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM3
DQM
CS
U4
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
SSCL
SDA
WP
A0 A1 A2
47KΩ
SA0 SA1 SA2
U0/U3
A0 ~ A12,BA0 & 1
SDRAM U0 ~ U8
SDRAM U0 ~ U8
SDRAM U0 ~ U8
·
U5/U7
U1/U4
U6/U8
U2
RAS
CAS
10Ω
·
CLK0/2
·
·
WE
SDRAM U0 ~ U8
SDRAM U0 ~ U8
CKE0
*1
3.3pF
10Ω
*1 : For 4 loads, CLK2 only.
DQn
Every DQpin of SDRAM
10Ω
V
DD
·
·
·
·
CLK1/3
One 0.1uF and one 0.22 uF Cap.
per each SDRAM
10pF
To all SDRAMs
Vss
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15459
2
WED3DG7265V-D2
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN, Vout
VDD, VDDQ
TSTG
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
9
Units
V
V
°C
W
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage Temperature
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C)
Parameter
Supply Voltage
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
Typ
3.3
Max
3.6
Unit
V
V
V
V
Note
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
3.0 VDDQ+0.3
1
2
VIL
0.8
0.4
10
VOH
VOL
ILI
IOH= -2mA
IOL= -2mA
3
V
µA
-10
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is £ 3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is £ 3ns.
3. Any input 0V £ VIN £ VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State
outputs.
CAPACITANCE
(TA = 23°C, f = 1MHz, VDD = 3.3V, VREF=1.4V 6200mV)
Parameter
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
Cout
Min
Max
45
45
45
35
30
15
45
10
10
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12)
Input Capacitance (RAS,CAS,WE)
Input Capacitance (CKE0)
-
-
-
-
-
-
-
-
-
Input Capacitance (CLK0)
Input Capacitance (CS0,CS2)
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)
Data input/output capacitance (CB0-CB7)
Cout1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15459
3
WED3DG7265V-D2
OPERATING CURRENT CHARACTERISTICS
(VCC = 3.3V, TA = 0°C to +70°C)
Version
Parameter
Operating Current
(One bank active)
Symbol
ICC1
Conditions
Burst Length = 1
tRC ³ tRC(min)
133
1,800
100
1,620
Units Note
mA
1
IOL = 0mA
Precharge Standby Current
in Power Down Mode
ICC2P
ICC2PS
Icc2N
CKE £VIL(max), tCC = 10ns
CKE & CLK £ VIL(max), tCC = ¥
CKE ³ VIH(min), CS ³ VIH(min), tcc = 10ns
Input signals are charged one time during 20
CKE ³ VIH(min), CLK £VIL(max), tcc = ¥
Input signals are stable
CKE ³ VIL(max), tCC = 10ns
CKE & CLK £ VIL(max), tcc = ¥
CKE ³ VIH(min), CS ³ VIH(min), tcc = 10ns
Input signals are changed one time during 20ns
CKE ³ VIH(min), CLK £VIL(max), tcc = ¥
input signals are stable
60
45
mA
Precharge Standby Current
in Non-Power Down Mode
270
Icc2NS
mA
mA
90
90
80
Active standby current in
power-down mode
ICC3P
ICC3PS
ICC3N
Active standby current in
non power-down mode
450
315
mA
mA
mA
ICC3NS
ICC4
Io = mA
Page burst
4 Banks activated
tCCD = 2CLK
tRC ³ tRC(min)
CKE £ 0.2V
Operating current (Burst mode)
1,800
2,970
1,530
1
2
Refresh current
Self refresh current
ICC5
ICC6
2,790
mA
mA
65
Notes: 1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL = VDDQ/VssQ)
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15459
4
WED3DG7265V-D2
ORDERING INFORMATION
Part Number
Speed
CAS Latency
CL=2
WED3DG7265V10D2
WED3DG7265V7D2
WED3DG7265V75D2
100MHz
133MHz
133MHz
CL=2
CL=3
PACKAGE DIMENSIONS
1.100
57
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15459
5
WED3DG7265V-D2
REV.
A
DATE
REQUESTED BY
PAUL MARIEN
DETAILS
3-25-02
CREATED
0
9-16-02
PAUL MARIEN -CHANGED FROM ADVANCED
TO FINAL
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15459
6
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