WED9LC6816V1312BI [WEDC]
256Kx32 SSRAM/4Mx32 SDRAM; 256Kx32 SSRAM / SDRAM 4Mx32
| 型号： | WED9LC6816V1312BI |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 256Kx32 SSRAM/4Mx32 SDRAM |
| 文件： | 总27页 (文件大小：1138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED9LC6816V
White Electronic Designs
256Kx32 SSRAM/4Mx32 SDRAM
EXTERNAL MEMORY SOLUTION FOR TEXAS INSTRUMENTS
TMS320C6000 DSP
DESCRIPTION
The WED9LC6816V is a 3.3V, 256K x 32 Synchronous
Pipeline SRAM and a 4Mx32 Synchronous DRAM array
constructed with one 256K x 32 SBSRAM and two 4Mx16
SDRAM die mounted on a multilayer laminate substrate.
The device is packaged in a 153 lead, 14mm x 22mm,
BGA.
FEATURES
Clock speeds:
SSRAM: 200, 166,150, and 133 MHz
SDRAMs: 125 and 100 MHz
DSP Memory Solution
The WED9LC6816V provides a total memory solution
for the Texas Instruments TMS320C6201 and the
TMS320C6701 DSPs The Synchronous Pipeline SRAM
is available with clock speeds of 200, 166,150,v and 133
MHz, allowing the user to develop a fast external memory
for the SSRAM interface port .
Texas Instruments TMS320C6201
Texas Instruments TMS320C6701
Packaging:
153 pin BGA, JEDEC MO 163
3.3V Operating supply voltage
The SDRAM is available in clock speeds of 125 and 100
MHz, allowing the user to develop a fast external memory
for the SDRAM interface port.
Direct control interface to both the SSRAM and
SDRAM ports on the “C6x”
Common address and databus
The WED9LC6816V is available in both commercial and
industrial temperature ranges.
65% space savings vs. monolithic solution
Reduced system inductance and capacitance
This product is subject to change without notice.
FIG. 1 PIN CONFIGURATION
TOP VIEW
PIN DESCRIPTION
1
2
3
4
5
6
7
8
9
A0-17
Address Bus
Data Bus
A
B
C
D
E
F
DQ19
DQ18
VCCQ
DQ17
DQ16
VCCQ
NC
DQ23
DQ22
VCCQ
DQ21
DQ20
VCCQ
NC
VCC
VCC
VSS
VSS
VSS
VSS VCC DQ24 DQ28
DQ0-31
SDCE# VSS VCC DQ25 DQ29
SSCK#
SSADC#
SSWE#
SSOE#
SDCK
SSRAM Clock
VCC SDWE# SDA10 NC VCC VCCQ VCCQ
SSRAM Address Status Control
SSRAM Write Enable
VCC
VCC
VCC
VSS
VSS
VSS
VSS
SDCK
VSS
VSS VCC DQ26 DQ30
VSS VCC DQ27 DQ31
SSRAM Output Enable
VSS
VCC
A2
VCCQ VCCQ
SDRAM Clock
G
H
J
NC SDRAS# SDCAS# VSS
A4
A3
A5
SDRAS#
SDCAS#
SDWE#
SDA10
SDRAM Row Address Strobe
SDRAM Column Address Strobe
SDRAM Write Enable
NC
NC
A8
A9
VSS
VSS
VSS
VSS
VSS
VSS
NC
NC
A1
A10
A12
A14
A16
A6
A7
A0
A11
A13
A15
K
L
A17
NC/A18 NC/A19
NC NC
SDRAM Address 10/auto precharge
SSRAM Byte Write Enables SDRAM SDQM 0-3
Chip Enable SSRAM Device
Chip Enable SDRAM Device
Power Supply pins, 3.3V
Data Bus Power Supply pins, 3.3V (2.5V future)
Ground
NC
NC
NC BWE2# BWE3# NC NC
BWE0-3
SSCE
SDCE
VCC
#
M
N
P
R
T
VCCQ
DQ12
DQ13
VCCQ
DQ14
DQ15
VCCQ
DQ11
DQ10
VCCQ
DQ9
DQ8
VCC BWE0# BWE1# NC VCC VCCQ VCCQ
VCC
VCC
VCC
VSS
VSS
VSS
VSS
SSCK
VSS
VSS VCC DQ4 DQ0
VSS VCC DQ5 DQ1
VSS
VCC
VCCQ VCCQ
VCCQ
VSS
VCC SSADC# SSWE# NC VCC DQ6 DQ2
SSOE# SSCE# NC DQ7 DQ3
U
VCC
VCC
NC
No Contact
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED9LC6816V
White Electronic Designs
FIG. 2 BLOCK DIAGRAM
A
0-17
A0
A0
A1
A1
A2
A3
A4
DQ1-8
DQ0-7
A5
A6
DQ9-16
DQ8-15
DQ16-23
DQ24-31
A7
A8
DQ17-24
A9
A10
A11
A12
A13
A14
A15
A16
DQ25-32
SSWE#
BWE#
BWE
BWE
BWE
BWE
0
1
2
3
#
#
#
#
BW1
BW2
BW3
BW4
#
#
#
#
SSCE#
SSOE#
CE
2#
OE#
SSADC#
ADSC#
CK#
SSCK#
DQ0-31
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
DQ0-7
DQ0-7
9
DQ8-15 DQ8-15
11
SDA10
10/AP
A
12
13
BA0
A
BA1
LDQM#
UDQM#
CS#
SDCE#
SDRAS#
SDCAS#
SDWE#
RAS#
CAS#
WE#
SDCK#
CK#
A
A
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
DQ16-23
DQ0-7
9
DQ24-31
DQ8-15
11
10/AP
A
12
13
BA
BA
0
1
A
LDQM#
UDQM#
CS#
RAS#
CAS#
WE#
CK#
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White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
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WED9LC6816V
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Output Functional Descriptions
Symbol
Type
Signal
Polarity
Function
SSCK#
Input
Pulse
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
SSADS#
SSOE#
SSWE#
When sampled at the positive rising edge of the clock, SSADS#, SSOE#, and SSWE# define
the operation to be executed by the SSRAM.
Input
Pulse
Active Low
SSCE#
SDCK#
Input
Input
Pulse
Pulse
Active Low
SSCE# disable or enable SSRAM device operation.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
SDCE disable or enable device operation by masking or enabling all inputs except SDCK# and BWE0-3.
SDCE
Input
Pulse
Active Low
Active Low
SDRAS#
SDCAS#
SDWE#
When sampled at the positive rising edge of the clock, SDCAS#, SDRAS#, and SDWE#
define the operation to be executed by the SDRAM.
Input
Pulse
Address bus for SSRAM and SDRAM
A0 and A1 are the burst address inputs for the SSRAM
During a Bank Active command cycle, A0-11, SDA10 defines the row address (RA0-10) when
sampled at the rising clock edge.
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when
sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke
Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA10 is high,
autoprecharge is selected and A12 and A13 define the bank to be precharged. If SDA10 is low,
autoprecharge is disabled.
A0-17
SDA10
Input
Level
—
During a Precharge command cycle, SDA10 is used in conjunction with A12 and A13 to control
which bank(s) to precharge. If SDA10 is high, all banks will be precharged regardless of
the state of A12 and A13. If SDA10 is low, then A12 and A13 are used to define which bank to
precharge.
Input
Output
Data Input/Output are multiplexed on the same pins.
Level
Pulse
—
DQ0-31
BWE0-3
VCC, VSS
BWE0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM BWE0 is
associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31
Input
.
Power and ground for the input buffers and the core logic.
Supply
,
VCCQ
Supply
Data base power supply pins, 3.3V (2.5V future).
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
3
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Absolute Maximum Ratings
Recommended DC Operating Conditions
(Vcc = 3.3V -5% / +10% unless otherwise noted;
0°C Ta 70°C, Commercial; -40°C Ta 85°C, Industrial)
Voltage on VCC Relative to VSS
-0.5V to +4.6V
-0.5V to Vcc +0.5V
-55°C to +125°C
+150°C
VIN (DQx)
Parameter
Symbol Min
Max
3.6
Units
Storage Temperature (BGA)
Junction Temperature
Short Circuit Output Current
Supply Voltage (1)
Input High Voltage (1,2)
Input Low Voltage (1,2)
VCC
VIH
VIL
ILI
3.135
2.0
V
V
V
A
VCC +0.3
0.8
100 mA
-0.3
-10
Input Leakage Current
10
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those indicated
in operational sections of this specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
0 VIN VCC
Output Leakage (Output Disabled)
ILO
-10
10
A
0 VIN VCC
SSRAM Output High (IOH = -4mA) (1)
SSRAM Output Low (IOL = 8mA) (1)
SDRAM Output High (IOH = -2mA)
SDRAM Output Low (IOL = 2mA)
VOH
VOL
VOH
VOL
2.4
—
—
0.4
—
V
V
V
V
2.4
—
0.4
NOTES:
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH +6.0V for t tKC/2 Underershoot: VIL -2.0V for
t tKC/2
DC Electrical Characteristics
(Vcc = 3.3V -5% / +10% unless otherwise noted; 0°C Ta 70°C, Commercial; -40°C Ta 85°C, Industrial)
Description
Conditions
Symbol Frequency
Typ
500
500
550
600
325
350
400
450
500
500
550
Max
625
650
700
800
425
450
495
585
625
650
700
Units
133MHz
150MHz
ICC1
Power Supply Current
Operating (1, 2, 3)
SSRAM Active / DRAM Auto Refresh
mA
166MHz
200MHz
133MHz
150MHz
ICC2
Power Supply Current
Operating (1, 2, 3)
SSRAM Active / DRAM Idle
SSRAM Active / SSRAM Idle
mA
166MHz
200MHz
83MHz
Power Supply Current
Operating (1, 2, 3)
ICC3
100MHz
125MHz
mA
mA
SSCE# and SDCE# VCC -0.2V,
All other inputs at VSS +0.2 VIN or
VIN VCC -0.2V, Clk frequency = 0
CMOS Standby
ISB1
20.0
40.0
SSCE# and SDCE# VIH min
All other inputs at VIL max VIN or
VIN VCC -0.2V, CK# frequency = 0
TTL Standby
Auto Refresh
ISB2
ICC5
30.0
250
55.0
300
mA
mA
NOTES:
1. ICC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading.
2. "Device idle" means device is deselected (CE# = VIH) Clock is running at max frequency and Addresses are switching each cycle.
3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
4
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WED9LC6816V
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SSRAM AC Characteristics
(Vcc = 3.3V -5% / +10% unless otherwise noted; 0°C Ta 70°C, Commercial; -40°C Ta 85°C, Industrial)
200MHz
166MHz
Min Max
150MHz
133MHz
Min Max
Parameter
Symbol
tKHKH
tKLKH
tKHKL
tKHQV
tKHQX
tKQLZ
tKQHZ
tOELQV
tOELZ
tOEHZ
tS
Min
Max
Min
Max
Units
ns
Clock Cycle Time
5
6
7
8
Clock HIGH Time
1.6
1.6
2.4
2.4
3.5
1.5
0
2.6
2.6
2.8
2.8
ns
Clock LOW Time
ns
Clock to output valid
2.5
3.8
4.0
ns
Clock to output invalid
1.5
0
1.5
0
1.5
0
ns
Clock to output on Low-Z
Clock to output in High-Z
Output Enable to output valid
Output Enable to output in Low-Z
Output Enable to output in High-Z
Address, Control, Data-in Setup Time to Clock
Address, Control, Data-in Hold Time to Clock
ns
1.5
3
1.5
3.5
3.5
1.5
3.8
3.8
1.5
4.0
4.0
ns
2.5
ns
0
0
0
0
ns
3.0
3.5
3.5
3.8
ns
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
ns
tH
ns
BGA Capacitance
Description
Conditions
Symbol
Typ
Max Units
Address Input Capacitance (1)
Input/Output Capacitance (DQ) (1)
Control Input Capacitance (1)
Clock Input Capacitance (1)
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
CI
CO
CA
5
8
5
4
8
10
8
pF
pF
pF
pF
CCK
6
NOTE:
1. This parameter is sampled.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
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SSRAM Operation Truth Table
Operation
Address Used
None
SSCE# SSADS# SSWE# SSOE#
DQ
High-Z
D
Deselected Cycle, Power Down
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
H
L
L
L
X
L
X
X
L
External
External
External
Current
Current
Current
Current
Current
Current
L
L
H
H
H
H
H
H
L
Q
L
L
H
L
High-Z
Q
X
X
H
H
X
H
H
H
H
H
H
H
H
L
High-Z
Q
H
X
X
High-Z
D
D
L
NOTE:
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE# must meet setup and hold times around the rising edge (LOW to HIGH) of SSCK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE# must be HIGH before the input data required setup time plus High-Z time
for SSOE# and staying HIGH through out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
SSRAM Partial Truth Table
Function
SSWE#
BWE0#
BWE1# BWE2# BWE3#
READ
H
X
X
X
X
WRITE one Byte (DQ0-7)
WRITE all Bytes
L
L
L
L
H
L
H
L
H
L
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
6
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FIG. 3 SSRAM READ TIMING
t
K
H
K
L
t
K
L
K
H
tKHKH
SSCK
tS
tH
SSADS#
SSCE#
tS
tH
tS
A1
A5
A2
A3
A4
ADDR
tH
SSOE#
tOEHZ
tOELQV
SSWE#
tKHQX
tKHQV
tKQLZ
Q(A1)
Q(A2)
Q(A3)
Q(A4)
Q(A5)
DQ
FIG. 4 SSRAM WRITE TIMING
t
t
tKHKH
K
H
K
L
K
L
K
H
SSCK
tH
tS
SSADS#
SSCE#
tH
tH
tS
A4
A1
A2
A3
A5
ADDR
SSOE#
SSWE#
tH
tOEHZ
Must be HIGH
K
tS
tH
tH
tS
D(A2)
D(A3)
D(A5)
D(A1)
D(A4)
DQ
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
7
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WED9LC6816V
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SDRAM AC Characteristics
(Vcc = 3.3V -5% / +10% unless otherwise noted; 0°C Ta 70°C, Commercial; -40°C Ta 85°C, Industrial)
125MHz
100MHz
83MHz
Min
Parameter
Symbol
tCC
Min
Max
1000
1000
6
Min
Max
1000
1000
7
Max
1000
1000
8
Units
ns
Clock Cycle Time (1)
CL = 3
CL = 2
8
10
12
12
15
tCC
10
ns
Clock to valid Output delay (1,2)
Output Data Hold Time (2)
tSAC
tOH
ns
3
3
3
2
1
2
3
3
3
2
1
2
3
3
3
2
1
2
ns
Clock HIGH Pulse Width (3)
Clock LOW Pulse Width (3)
Input Setup Time (3)
tCH
ns
tCL
ns
tSS
ns
Input Hold Time (3)
tSH
ns
CK# to Output Low-Z (2)
tSLZ
tSHZ
tRRD
tRCD
tRP
ns
CK# to Output High-Z
7
7
8
ns
Row Active to Row Active Delay (4)
RAS# to CAS# Delay (4)
20
20
20
50
70
70
1
20
20
20
50
80
80
1
24
24
24
60
90
90
1
ns
ns
Row Precharge Time (4)
ns
Row Active Time (4)
tRAS
tRC
10,000
10,000
10,000
ns
Row Cycle Time - Operation (4)
Row Cycle Time - Auto Refresh (4,8)
Last Data in to New Column Address Delay (5)
Last Data in to Row Precharge (5)
Last Data in to Burst Stop (5)
Column Address to Column Address Delay (6)
Number of Valid Output Data (7)
ns
tRFC
tCDL
tRDL
tBDL
tCCD
ns
CK#
CK#
CK#
CK#
1
1
1
1
1
1
1.5
2
1.5
2
1.5
2
ea
1
2
1
NOTES:
1. Parameters depend on programmed CAS latency.
2. If clock rise time is longer than 1ns (trise/2 -0.5)ns should be added to the parameter.
3. Assumed input rise and fall time = 1ns. If trise of tfall are longer than 1ns. [(trise = tfall)/2] - 1ns should be added to the parameter.
4. The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the next higher integer.
5. Minimum delay is required to complete write.
6. All devices allow every cycle column address changes.
7. In case of row precharge interrupt, auto precharge and read burst stop.
8. A new command may be given tRFC after self-refresh exit.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
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Clock Frequency and Latency Parameters - 125MHz SDRAM
(Unit = number of clock)
tRC
70ns
tRAS
50ns
tRP
20ns
tRRD
20ns
tRCD
20ns
tCCD
10ns
tCDL
10ns
tRDL
10ns
CAS
Latency
Frequency
125MHz (8.0ns)
100MHz (10.0ns)
83MHz (12.0ns)
3
3
2
9
7
6
6
5
4
3
2
2
2
2
2
3
2
2
1
1
1
1
1
1
1
1
1
Clock Frequency and Latency Parameters - 100MHz SDRAM
(Unit = number of clock)
tRC
70ns
7
tRAS
50ns
5
tRP
tRRD
tRCD
20ns
2
tCCD
10ns
1
tCDL
10ns
1
tRDL
10ns
1
CAS
Latency
Frequency
20ns 20ns
100MHz (12.0ns)
83MHz (12.0ns)
3
2
2
2
2
2
6
5
2
1
1
Refresh Cycle Parameters
-10
-12
Parameter
Symbol
Min
Max
Min
Max
Units
ms
Refresh Period (1,2)
tREF
—
64
—
64
NOTES:
1. 4096 cycles
2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to
"wake-up" the device.
SDRAM Command Truth Table
SDA10
A11-0
Function
SDCE# SDRAS# SDCAS# SDWE # BWE# A12, A13
Notes
Mode Register Set
Auto Refresh (CBR)
L
L
L
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
L
OP CODE
L
X
BA
X
X
Single Bank
L
L
L
L
L
L
L
L
L
H
X
X
L
H
H
H
L
L
2
Precharge
Precharge all Banks
L
L
H
Bank Activate
L
H
L
BA
BA
BA
BA
BA
X
Row Address
2
2
2
2
2
3
Write
H
H
H
H
H
H
X
X
X
L
H
L
Write with Auto Precharge
Read
L
L
L
L
Read with Auto Precharge
Burst Termination
No Operation
L
H
L
H
X
X
X
X
X
H
H
X
X
X
H
X
X
X
X
Device Deselect
Data Write/Output Disable
X
X
4
4
Data Mask/Output Disable
H
X
NOTES:
1. All of the SDRAM operations are defined by states of SDCE#, SDWE#, SDRAS#, SDCAS#, and BWE0-3# at the positive rising edge of the clock.
2. Bank Select (BA), A12 (BA0) and A13 (BA1) select between different banks.
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE# has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE# goes high at a clock timing the data outputs are disabled
and become high impedance after a two clock delay. BWE# also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is
prohibited (zero clock latency).
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
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MODE REGISTER SET TABLE
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A4
A3
A2
A1
A0
Address Bus
Mode Register (Mx)
Reserved*
WB Op Mode
CAS# Latency
BT
Burst Length
*Should program
M11, M10 = "0, 0"
to ensure compatibility
with future devices.
Burst Length
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Burst Type
M3
0
Sequential
Interleaved
1
CAS Latency
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
Reserved
Reserved
M8
M7
0
M6-M0
Defined
-
Operating Mode
0
Standard Operation
All other states reserved
-
-
Write Burst Mode
M9
0
Programmed Burst Length
Single Location Access
1
Contact factory for ordering information.
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September, 2003
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SDRAM CURRENT STATE TRUTH TABLE
Command
Current State
Action
Notes
1
SDCE#
SDRAS #
SDCAS#
SDWE#
A12 & A13 (BA)
A11-A0
Description
Set the Mode Register
Auto or Self Refresh
Precharge
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
OP Code
Mode Register Set
1
Start Auto
X
X
X
L
H
H
L
X
Row Address
Column
Column
X
No Operation
L
H
L
BA
BA
BA
X
Bank Activate
Activate the specified bank and row
ILLEGAL
H
H
H
H
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
2
1
1
Idle
L
H
L
ILLEGAL
H
H
No Operation
H
X
X
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L
L
L
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
Precharge
ILLEGA
X
X
H
H
X
X
3
1
H
BA
Row Address
Bank Activate
L
H
L
L
BA
Column
Write
Start Write; Determine if Auto Precharge
4,5
4,5
Row Active
L
L
L
H
H
H
L
H
H
H
L
BA
X
Column
Read
Start Read; Determine if Auto Precharge
No Operation
X
X
Burst Termination
No Operation
H
X
No Operation
H
X
X
X
X
X
Device Deselect
No Operation
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
OP Code
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
X
X
X
L
H
H
L
X
Terminate Burst; Start the Precharge
ILLEGAL
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
2
Read
H
H
H
H
X
Column
Terminate Burst; Start the Write cycle
Terminate Burst; Start a new Read cycle
Terminate the Burst
5,6
5,6
L
H
L
Column
Read
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
H
X
X
Continue the Burst
X
Continue the Burst
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
X
X
X
Auto or Self Refresh
Precharge
ILLEGAL
Terminate Burst; Start the Precharge
ILLEGAL
X
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
2
Write
H
H
H
H
X
L
Column
Terminate Burst; Start a new Write cycle
Terminate Burst; Start the Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
5,6
5,6
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
X
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Row Address
Column
Column
X
ILLEGAL
2
2
L
H
L
BA
BA
BA
X
Bank Activate
Write
ILLEGAL
Read with
Auto Precharge
H
H
H
H
ILLEGAL
L
H
L
Read
ILLEGAL
H
H
Burst Termination
No Operation
ILLEGAL
H
X
X
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
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WED9LC6816V
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SDRAM Current State Truth Table (cont.)
Command
Current State
Action
Notes
SDCE#
SDRAS #
SDCAS#
SDWE#
A12 & A13 (BA)
A11-A0
Description
Mode Register Set
Auto or Self Refresh
Precharge
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
OP Code
ILLEGAL
ILLEGAL
X
X
X
L
H
H
L
X
Row Address
Column
Column
X
ILLEGAL
2
2
L
H
L
BA
BA
BA
X
Bank Activate
Write
ILLEGAL
Write with Auto
Precharge
H
H
H
H
ILLEGAL
L
H
L
Read
ILLEGAL
H
H
Burst Termination
No Operation
ILLEGAL
H
X
X
Continue the Burst
H
X
X
X
X
X
Device Deselect
Continue the Burst
L
L
L
L
L
L
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
X
X
H
H
X
X
No Operation; Bank(s) idle after tRP
ILLEGAL
H
BA
Row Address
Bank Activate
2
2
L
H
L
L
BA
Column
Write w/o Precharge
ILLEGAL
Precharging
L
L
L
H
H
H
L
H
H
H
L
BA
X
Column
Read w/o Precharge
Burst Termination
No Operation
ILLEGAL
20
X
X
No Operation; Bank(s) idle after tRP
No Operation; Bank(s) idle after tRP
H
X
H
X
X
X
X
X
Device Deselect
No Operation; Bank(s) idle after tRP
L
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
OP Code
OP Code
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
X
X
X
L
H
H
L
X
ILLEGAL
2
2
2
2
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Row Activating
H
H
H
H
X
Column
ILLEGAL
L
H
L
Column
Read
ILLEGAL
H
H
X
X
X
X
Burst Termination
No Operation
Device Deselect
No Operation; Row active after tRCD
No Operation; Row active after tRCD
No Operation; Row active after tRCD
H
X
X
X
L
L
L
L
Mode Register Set
ILLEGAL
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
X
X
X
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
X
2
2
6
6
L
H
L
BA
BA
BA
X
Row Address
Bank Activate
Write
ILLEGAL
Write
Recovering
H
H
H
H
X
L
Column
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
ILLEGAL
L
H
L
Column
Read
H
H
X
L
X
X
X
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
H
X
L
X
X
L
L
H
L
X
X
X
ILLEGAL
L
H
H
L
X
Row Address
Column
Column
X
ILLEGAL
2
L
H
L
BA
BA
BA
X
Bank Activate
Write
ILLEGAL
2
With Recovering
with Auto
Precharging
H
H
H
H
ILLEGAL
2,6
2,6
L
H
L
Read
ILLEGAL
H
H
Burst Termination
No Operation
No Operation; Precharge after tDPL
No Operation; Precharge after tDPL
H
X
X
H
X
X
X
X
X
Device Deselect
No Operation; Precharge after tDPL
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
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WED9LC6816V
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SDRAM Current State Truth Table (cont.)
Command
Current State
Action
Notes
SDCE#
SDRAS #
SDCAS#
SDWE#
A12 & A13 (BA)
A11-A0
Description
Mode Register Set
Auto or Self Refresh
Precharge
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
OP Code
ILLEGAL
ILLEGAL
X
X
X
L
H
H
L
X
Row Address
Column
Column
X
ILLEGAL
L
H
L
BA
BA
BA
X
Bank Activate
Write
ILLEGAL
H
H
H
H
ILLEGAL
Refreshing
L
H
L
Read
ILLEGAL
H
H
Burst Termination
No Operation
No Operation; Idle after tRC
No Operation; Idle after tRC
H
X
X
H
X
X
X
X
X
Device Deselect
No Operation; Idle after tRC
L
L
L
L
L
L
L
L
L
L
L
H
L
OP Code
Mode Register Set
Auto or Self Refresh
Precharge
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
X
X
H
H
X
X
H
BA
Row Address
Bank Activate
Mode Register
Accessing
L
H
L
L
BA
Column
Write
ILLEGAL
L
L
L
H
H
H
L
H
H
H
L
BA
X
Column
Read
ILLEGAL
ILLEGAL
X
X
Burst Termination
No Operation
H
X
No Operation; Idle after two clock cycles
H
X
X
X
X
X
Device Deselect
No Operation; Idle after two clock cycles
NOTES:
1. Both Banks must be idle otherwise it is an illegal action.
2. The Current State refers only refers to one of the banks, if BA selects this bank then the action is illegal. If BA selects the bank not being referenced by the Current
State then the action may be legal depending on the state of that bank.
3. The minimum and maximum Active time (tRAS) must be satisfied.
4. The RAS# to CAS# Delay (tRCD) must occur before the command is given.
5. Address SDA10 is used to determine if the Auto Precharge function is activated.
6. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
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FIG. 5 SDRAM SINGLE BIT READ-WRITE-READ CYCLE (SAME PAGE) @
CAS LATENCY = 3, BURST LENGTH = 1
6
0
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
tCH
t
CL
tCC
tRCD
tRAS
SDCE#
t
SS
tSH
tRP
tRCD
tSH
tSS
SDRAS#
t
CCD
tSS
tSH
SDCAS#
ADDR
tSS
tSH
tSH
tSS
Cb
BS
Cc
Ra
Ca
Rb
BA0, 1
BS
Rb
BS
Ra
BS
BS
BS
[A12,A13
]
SDA10
tRAC
t
SS
SS
SS
t
SH
t
SAC
Qa
Db
Qc
DQ
t
SLZ
tOH
t
t
tSH
SDWE#
t
SH
BWE#
Read
Read
Write
Row Active
Row Active
DON’T CARE
Precharge
Contact factory for ordering information.
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FIG. 6 SDRAM POWER UP SEQUENCE
6
0
1
2
3
4
5
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
tRFC
tRFC
tRP
SDRAS#
SDCAS#
ADDR
Key
RAa
BA0,1
[A12,A13
]
RAa
SDA10
DQ
HIGH-Z
SDWE#
BWE#
High level is necessary
Auto Refresh
Mode Register Set
Precharge
(All Banks)
Auto Refresh
Row Active
(A-Bank)
DON’T CARE
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
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FIG. 7 SDRAM READ & WRITE CYCLE AT SAME BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
Note 1
tRC
tRCD
SDRAS#
SDCAS#
ADDR
Ra
Ca0
Rb
Cb0
BA0, 1
[A12,A13
]
Ra
Rb
SDA10
CL=2
t
SHZ Note 4
t
RAC
tRDL
tOH
Note 3
tSAC
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
tSHZ Note 4
t
RAC
DQ
tRDL
tOH
Note 3
tSAC
Qa3
Db0 Db1 Db2 Db3
Qa0 Qa1 Qa2
CL=3
SDWE#
BWE#
Row Active
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
NOTES:
1. Minimum row cycle times are required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. (CAS# Latency - 1) number of valid output data is available after Row precharge. Last valid output will be Hi-Z (tSHZ)
after the clock.
3. Access time from Row active command. tCC *(tRCD + CAS# Latency - 1) + tSAC.
4. Output will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
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FIG. 8 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
tRCD
SDRAS#
Note 2
SDCAS#
ADDR
Ra
Ca0
Cb0
Cc0
Cd0
BA0, 1
[A12,A13
]
Ra
SDA10
CL=2
tRDL
Qa0
Qa1
Qb1
Qb2
Dc0
Dc0
Dc1
Dd1
Qb0
Dd0
DQ
t
CDL
Qa3
Dc1
Dd0 Dd1
Qa0 Qa1 Qa2
CL=3
SDWE#
BWE#
Note 3
Note 1
Read
(A-Bank)
Read
(A-Bank)
Write
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Precharge
(A-Bank)
DON’T CARE
NOTES:
1. To write data before burst read ends. BWE# should be asserted three cycle prior to write command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
3. BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked
internally.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
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FIG. 9 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
Note 1
SDCE#
SDRAS#
SDCAS#
ADDR
Note 2
RAa
CAa RBb
CBb
CAc
CBd
CAe
BA0, 1
[A12,A13]
RAa
RBb
SDA10
QAa0 QAa1 QAa2
QBb3
QBb0 QBb1 QBb2
QAc0 QAc1
QBd0 QBd1 QAe0 QAe1
QAa3
CL=2
DQ
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 Qbb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
CL=3
SDWE#
BWE#
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Row Active
(B-Bank)
Precharge
(A-Bank)
DON’T CARE
Read
(A-Bank)
NOTES:
1. SDCE# can be “don’t care” when SDRAS#, SDCAS# and SDWE# are high at the clock going high edge.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
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FIG. 10 SDRAM PAGE WRITE CYCLE AT DIFFERENT BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
Note 2
SDCAS#
ADDR
RAa
CAa RBb
CBb
CAc
CBb
BA0, 1
[A12,A13
]
SDA10
DQ
RAa
RBb
tCDL
tRDL
DAa3
DBb1 DBb2 DBb3 DAc0 DAc1
DBd1
DAa0 DAa1 DAa2
DBb0
DBd0
SDWE#
BWE#
Note 1
Row Active
(A-Bank)
Write
(A-Bank)
Row Active
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Write
(B-Bank)
Write
(A-Bank)
DON’T CARE
NOTES:
1. To interrupt burst write by Row precharge, BWE# should be asserted to mask invalid input data.
2. To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
19
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WED9LC6816V
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FIG. 11 SDRAM READ & WRITE CYCLE AT DIFFERENT BANK @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
BA0, 1
RAa
CAa
RBb
CBb
RAc
CAc
[A12,A13
]
RAa
RBb
RAc
SDA10
CL=2
tCDL
Note 1
QAa0
DBb0 DBb1
DBb0 DBb1
DBb3
QAc0 QAc1 QAc2
QAc0 QAc1
QAa1 QAa2 QAa3
QAa0 QAa1 QAa2
DBb2
DBb2
DQ
CL=3
QAa3
DBb3
SDWE#
BWE#
Write
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
DON’T CARE
Row Active
(A-Bank)
Row Active
(A-Bank)
NOTES:
1. tCDL should be met to complete write.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
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FIG. 12 SDRAM READ & WRITE CYCLE WITH AUTO PRECHARGE @
BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
BA0, 1
Ra
Rb
Ca
Cb
[A12,A13
]
Ra
Rb
SDA10
CL=2
Qa0
Db0
Db0
Db1 Db2
Db3
Qa1 Qa2 Qa3
DQ
CL=3
Qa0 Qa1
Qa3
Db1
Db2
Db3
Qa2
SDWE#
BWE#
Row Active
(A-Bank)
Auto Precharge
Start Point
(B-Bank)
Write with
Auto Precharge
(B-Bank)
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
DON’T CARE
NOTES:
1. tCDL should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length = 1 & 2 and BRSW mode)
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
21
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED9LC6816V
White Electronic Designs
FIG. 13 SDRAM READ INTERRUPTED BY PRECHARGE COMMAND & READ
BURST STOP @ BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE
SDRAS#
SDCAS#
ADDR
RAa
CAa
CAb
BA0, 1
[A12,A13
]
RAa
SDA10
Note 2
1
1
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
QAa0 QAa1
QAa3 QAa4
QAa2
CL=2
CL=3
DQ
2
2
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
SDWE#
BWE#
Read
(A-Bank)
Precharge
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Burst Stop
DON’T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. About the valid DQs after burst stop, it is the same as the case of SDRAS# interrupt. Both cases are illustrated in the above timing diagram. See the label 1, 2 on each
of them. But at burst write, burst stop and SDRAS# interrupt should be compared carefully. Refer to the timing diagram of “Full page write burst stop cycle”.
3. Burst stop is valid at every burst length.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
22
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED9LC6816V
White Electronic Designs
FIG. 14 SDRAM WRITE INTERRUPTED BY PRECHARGE COMMAND &
WRITE BURST STOP @ BURST LENGTH = FULL PAGE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
RAa
CAa
CAb
BA0, 1
[A12,A13
]
RAa
SDA10
DQ
tBDL
tRDL
Note 2
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAB4 DAb5
SDWE#
BWE#
Write
(A-Bank)
Row Active
(A-Bank)
Burst Stop
Precharge
(A-Bank)
Write
(A-Bank)
DON’T CARE
NOTES:
1. At full page mode, burst is end at the end of burst. So auto precharge is possible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. BWE# at write interrupt by
precharge command is needed to prevent invalid write.BWE# should mask invalid input data on precharge command cycle when asserting precharge before end of
burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
23
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED9LC6816V
White Electronic Designs
FIG. 15 SDRAM BURST READ SINGLE BIT WRITE CYCLE @
BURST LENGTH = 2
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
SDCK
SDCE#
SDRAS#
SDCAS#
ADDR
RAa
CAa
RBb CAb
RAc
CBc
CAd
BA0, 1
]
[A12,A13
RAa
RBb
RAc
SDA10
CL=2
DAa0
DAa0
QAb0
DBc0
DBc0
QAd1
QAb1
QAd0
DQ
CL=3
QAd0 QAd1
QAa1 QAb1
SDWE#
BWE#
Row Active
(A-Bank)
Precharge
(Both Banks)
Row Active
(A-Bank)
Read
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Row Active
(B-Bank)
Read with
Write
Auto Precharge
(A-Bank)
(A-Bank)
DON’T CARE
NOTES:
1. BRSW modes enabled by setting A9 “High” at MRS (Mode Register Set).
At the BRSW Mode, the burst length at Write is fixed to “1” regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in
the case of BRSW write command, the next cycle starts the precharge.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
24
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED9LC6816V
White Electronic Designs
FIG. 16
SDRAM MODE REGISTER
SET CYLE
SDRAM AUTO REFRESH CYCLE
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
8
9
10
SDCK
HIGH
SDCE#
Note 2
tRFC
SDRAS#
Note 1
Note 3
SDCAS#
ADDR
Key
Ra
DQ
HI-Z
HI- Z
SDWE#
BWE#
MRS
New
Comman d
Auto Refres h
New Comman d
DON'T CARE
*Both banks precharge should be completed before Mode Register Set cycle and Auto refresh cycle.
NOTES:
MODE REGISTER SET CYCLE
1. SDCE#, SDRAS#, SDCAS# & SDWE# activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new SDRAS# activation.
3. Please refer to Mode Register Set Table.
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
25
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED9LC6816V
White Electronic Designs
PACKAGE DESCRIPTION: 153 LEAD BGA (17 X 9 BALL ARRAY)
JEDEC MP-163
3.50 (0.138)
MAX
14.00 (0.551)
BSC
A
B
C
D
E
F
PIN 1 INDEX
G
H
J
22.00 (0.866)
BSC
K
L
M
N
P
R
T
U
1.27 (0.050) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTE:
Ball attach pad for above BGA package is 480 microns in diameter. Pad is solder mask defined.
ORDERING INFORMATION
COMMERCIAL (0°C TA 70°C)
INDUSTRIAL (-40°C TA 85°C)
Part Number
SSRAM Access SDRAM Access
Part Number
SSRAM Access
200MHz
SDRAM Access
125MHz
WED9LC6816V2012BC
WED9LC6816V2010BC
WED9LC6816V1612BC
WED9LC6816V1610BC
WED9LC6816V1512BC
WED9LC6816V1510BC
WED9LC6816V1312BC
WED9LC6816V1310BC
200MHz
200MHz
166MHz
166MHz
150MHz
150MHz
133MHz
133MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
125MHz
100MHz
WED9LC6816V2012BI
WED9LC6816V2010BI
WED9LC6816V1612BI
WED9LC6816V1610BI
WED9LC6816V1512BI
WED9LC6816V1510BI
WED9LC6816V1312BI
WED9LC6816V1310BI
200MHz
100MHz
166MHz
125MHz
166MHz
100MHz
150MHz
125MHz
150MHz
100MHz
133MHz
125MHz
133MHz
100MHz
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
26
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED9LC6816V
White Electronic Designs
INTERFACING THE TEXAS INSTRUMENTS TMS 320C6x WITH THE
WED9LC6816V (256Kx32 SSRAM/4Mx32 SDRAM)
Address Bus
EDI9LC644V
EA2-21
EA2
A0
128K x 32 SSRAM
EA3
A1
1M x 32 SDRAM
A2
A3
A4
A5
A6
A7
A8
A9
A10
DQ0-7
Texas Instruments
A11
DQ8-15
A12
TMS320C6x
DQ16-23
DQ24-31
A13
DSP
A14
A15
A16
SSWE#
SSCE#
SSOE#
SSADC#
SSCK
SSWE#
CE2#
SSRAM
Control
SSOE#
SSADS#
SSCK
BWE0#
BWE1#
BWE2#
BWE3#
BE0#
BE1#
BE2#
BE3#
Shared
Controls
SDA10
SDA10
CE0#
SDCE#
SDRAS#
SDCAS#
SDWE#
SDCK
SDRAS#
SDCAS#
SDWE#
SDCK
SDRAM
Control
Data Bus
ED0-31
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
27
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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