WEDPN16M64VR-100BM [WEDC]
Synchronous DRAM Module, 16MX64, 6ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219;
| 型号： | WEDPN16M64VR-100BM |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Synchronous DRAM Module, 16MX64, 6ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219 动态存储器 |
| 文件： | 总15页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WEDPN16M64VR-XBX
White Electronic Designs
16MX64 REGISTERED SYNCHRONOUS DRAM*
GENERAL DESCRIPTION
FEATURES
The 128MByte (1Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 67,108,864-bit banks is organized as 8,192 rows
by 512 columns by 16 bits. The MCP also incorporates
two 16-bit universal bus drivers for input control signals
and addresses.
ꢀ
Registered for enhanced performance of bus
speeds
•
66, 100, 125, 133** MHz
ꢀ
Package:
•
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
ꢀ
ꢀ
Single 3.3V 0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
ꢀ
Internal pipelined operation; column address can be
changed every clock cycle
ꢀ
ꢀ
ꢀ
ꢀ
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
ꢀ
ꢀ
Organized as 16M x 64
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option.AnAUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
•
User configureable as 32M x 32
Weight: WEDPN16M64VR-XBX - 2.5 grams typical
BENEFITS
ꢀ
ꢀ
ꢀ
ꢀ
37% SPACE SAVINGS
The 1Gb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
17% I/O Reduction
Reduced part count
Reduced trace lengths for lower parasitic
capacitance
ꢀ
Glue-less connection to memory controller/PCI
Bridge
ꢀ
ꢀ
ꢀ
Suitable for hi-reliability applications
The 1Gb SDRAM is designed to operate in 3.3V, low-power
memory systems.An auto refresh mode is provided, along
with a power-saving, power-down mode.
Laminate interposer for optimum TCE match
Upgradeable to 32M x 64 density (contact factory
for information)
All inputs and outputs are LVTTLcompatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.
* This data sheet describes a product that is Not Recommended for New Designs, refer
to WEDPN16M64VR-XB2X for new designs.
** Available in commercial and industrial temperatures only.
April 2004
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDPN16M64VR-XBX
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FIGURE 1 – PIN CONFIGURATION
Top View
DQ
DQ
DQ
DQ
0
2
4
5
DQ14
DQ12
DQ10
DQ15
DQ13
DQ11
VSS
VSS
VCC
VCC
NC
VSS
VSS
VCC
VCC
NC
A
A
A
9
0
2
A
10
A
11
A
A
A
8
1
3
VCC
VCC
VSS
VSS
NC
VCC
VCC
VSS
VSS
NC
NC
NC
VCC
VCC
NC
NC
NC
NC
VCC
VSS
VSS
DQ16
DQ18
DQ20
DQ22
DQMB
OE#
DQ17
DQ19
DQ21
DQ23
VSS
DQ31
DQ29
DQ27
DQ26
NC
VSS
DQ
DQ
DQ
1
3
6
A
7
A
6
DQ30
DQ28
DQ25
DQ24
A
2
A
4
DQ
8
DQ9
A12
DNU
DNU
DNU
NC
DQ7
DQML
WE#
0
VCC
VCC
DQMB
1
NC
BA
0
BA
1
2
CAS#
CLK0
NC
VSS
DQMB
NC
3
CLK1
CS0
#
RAS#
VSS
VSS
NC
VCC
CKE
VCC
NC
CS1#
VSS
VSS
LE#
VCC
VSS
VSS
VCC
VSS
VSS
NC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
NC
VCC
NC
NC
VSS
NC
DNU
NC
NC
NC
VCC
NC
NC
CLK2
VSS
NC
DQ56
DQ57
DQ60
DQ62
VSS
DQMB
DQ58
DQ59
DQ61
DQ63
7
VCC
NC
DQMB
NC
6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
VSS
VSS
DQMB
DQ41
DQ43
DQ45
DQ47
5
VSS
DQMB
DQ37
DQ36
DQ34
DQ32
4
DQ39
DQ38
DQ35
DQ33
VCC
DQ55
DQ53
DQ51
DQ49
DQ54
DQ52
DQ50
DQ48
DQ40
DQ42
DQ44
DQ46
VSS
VCC
VCC
VSS
VCC
VCC
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
April 2004
Rev. 5
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FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
WE
B
#
RAS
CAS
B
#
B
#
WE# RAS# CAS#
A
0-12
BA0-1
CLK
CKE
CS0B
0
CLK
CKE
CS#
B
#
DQMB0B
DQMB1B
DQML
DQMH
WE# RAS# CAS#
A
0-12
BA0-1
CLK
CKE
CS1B
DQMB2B
DQMB3B
0
CLK
CKE
CS#
DQML
DQMH
B
CLK
OE#
2
#
OE#
LE#
DQMB0-7
WE#
CKE
RAS#
CAS#
DQMB0B-7B
WEB#
WE# RAS# CAS#
0-12
A
CKE
RAS
CAS
B
B
B
BA0-1
#
#
CLK
CKE
CS0B
1
CLK
CKE
CS#
B
CS0-1
#
CS0B-1B#
#
DQMB4B
DQMB5B
DQML
DQMH
OE#
LE#
WE# RAS# CAS#
A
0-12
BA0-1
CLK
CKE
CS1B
1
CLK
CKE
CS#
B
#
DQMB6B
DQMB7B
DQML
DQMH
April 2004
Rev. 5
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WEDPN16M64VR-XBX
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Figure 3. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-12 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4-M6
specify the CAS latency, M7 and M8 specify the operating
mode, M9 specifies the WRITE burst mode, and M10 and
M11 are reserved for future use. Address A12 (M12) is
undefined but should be driven LOW during loading of the
mode register.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
BURST LENGTH
INITIALIZATION
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Figure 3. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified
may result in undefined operation. Once power is applied
to VDD and VDDQ (simultaneously) and the clock is
stable (stable clock is defined as a signal cycling within
timing constraints specified for the clock pin), the SDRAM
requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100µs period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-8 when the burst length is set to two; by A2-8 when
the burst length is set to four; and by A3-8 when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power up
in an unknown state, it should be loaded prior to applying
any operational command.
BURST TYPE
REGISTER DEFINITION
MODE REGISTER
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selec-tion of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
April 2004
Rev. 5
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FIGURE 1 – MODE REGISTER DEFINITION
TABLE 1 – BURST DEFINITION
Order of Accesses Within a Burst
Starting Column
A12
A11
A
10
A9
A
8
A7
A
6
A5
A
4
A
3
A
2
A
1
A0
Address Bus
Burst
Length
Address
Type = Sequential Type = Interleaved
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
12 11 10
9
8
7
6
5
4
3
2
1
0
Mode Register (Mx)
2
4
0-1
1-0
0-1
1-0
Unused Reserved* WB Op Mode CAS Latency BT Burst Length
*Should program
M12, M11, M10 = 0, 0
to ensure compatibility
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
Burst Length
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
with future devices.
M2 M1 M0
M3 = 0
M3 = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
4
8
A2
0
0
0
0
1
1
1
1
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
Burst Type
M3
0
Sequential
Interleaved
1
CAS Latency
Reserved
Reserved
2
M6 M5 M4
n = A0-9/8/7
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Full
Page
(y)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Not Supported
(location 0-y)
Cn…
3
Reserved
Reserved
Reserved
Reserved
NOTES:
1.
2.
For full-page accesses: y = 512.
For a burst length of two, A1-8 select the block-of-two burst; A0 selects the
starting column within the block.
3.
4.
For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the
starting column within the block.
For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the
starting column within the block.
For a full-page burst, the full row is selected and A0-8 select the starting column.
Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
For a burst length of one, A0-8 select the unique column to be accessed, and
Mode Register bit M3 is ignored.
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
-
-
5.
6.
Write Burst Mode
M9
0
7.
Programmed Burst Length
Single Location Access
1
April 2004
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FIGURE 4 – CAS LATENCY
T0
T1
T2
T3
CLK
COMMAND
READ
NOP
tLZ
NOP
tOH
D
OUT
I/O
tAC
DON’T CARE
UNDEFINED
CAS Latency = 2
T1
T0
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
tLZ
NOP
tOH
D
OUT
I/O
tAC
CAS Latency = 3
programmed burst length applies to both READ and
WRITE bursts.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first piece of output data. The latency can be set to
two or three clocks.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n+m. The I/Os will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is programmed to two clocks, the I/Os will start driving
after T1 and the data will be valid by T2. Table 2 below
indicates the operating frequencies at which each CAS
latency setting can be used.
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
SPEED
-133
CAS LATENCY = 2
CAS LATENCY = 3
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
≤100
≤100
≤66
≤133
≤125
≤100
≤66
-125
-100
-66
OPERATING MODE
≤50
The normal operating mode is selected by setting M7and
M8 to zero; the other combinations of values for M7 and
M8 are reserved for future use and/or test modes. The
April 2004
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TRUTH TABLE — COMMANDS AND DQM OPERATION (NOTE 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
CS#
H
L
L
L
L
L
L
L
RAS#
CAS#
WE#
X
H
H
H
L
L
L
H
L
DQM
X
X
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
I/Os
X
X
X
X
Valid
Active
X
X
X
X
H
L
H
H
H
L
X
H
H
L
X
L/H 8
L/H 8
X
L
H
H
L
X
X
X
L
L
L
L
Op-Code
Write Enable/Output Enable (8)
Write Inhibit/Output High-Z (8)
–
–
–
–
–
–
–
–
L
H
–
–
Active
High-Z
NOTES:
1.
2.
3.
4.
CKE is HIGH for all commands shown except SELF REFRESH.
A0-11 define the op-code written to the Mode Register.
A0-11 provide row address, and BA0, BA1 determine which bank is made active.
A0-7 provide column address; A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
6.
7.
8.
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs
(two-clock delay).
5.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
REGISTER FUNCTION TABLE
INPUTS
OUTPUT
OE#
LE#
CLK
A
X
L
Y
Z
COMMAND INHIBIT
H
L
L
L
L
L
X
L
X
The COMMAND INHIBIT function prevents new commands
from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is
effectively deselected. Operations already in progress
are not affected.
X
L
L
X
H
L
H
H
H
H
I
L
I
H
X
H
L or H
Y0(1)
NO OPERATION (NOP)
NOTES: 1. Output level before the indicated steady-state input conditions were
established.
The NO OPERATION (NOP) command is used to perform
a NOP to an SDRAM which is selected (CS is LOW). This
prevents unwanted commands from being registered
during idle or wait states. Operations already in progress
are not affected.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Definition section. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
April 2004
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The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command is
issued. InputA10 determines whether one or all banks are
to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being
issued to that bank.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-A12 selects the row.
This row remains active (or open) for accesses until
a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening
a different row in the same bank.
AUTO PRECHARGE
READ
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, without requiring an explicit command. This is
accomplished by usingA10 to enableAUTO PRECHARGE
in conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except
in the full-page burst mode, where AUTO PRECHARGE
does not apply. AUTO PRECHARGE is nonpersistent in
that it is either enabled or disabled for each individual
READ or WRITE command.
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputsA0-8
selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the READ
burst; if AUTO PRECHARGE is not selected, the row will
remain open for subsequent accesses. Read data appears
on the I/Os subject to the logic level on the DQM inputs
two clocks earlier. If a given DQM signal was registered
HIGH, the corresponding I/Os will be High-Z two clocks
later; if the DQM signal was registered LOW, the I/Os will
provide valid data.
AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the
precharge time (tRP) is completed. This is determined as
if an explicit PRECHARGE command was issued at the
earliest possible time.
WRITE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputsA0-8
selects the starting column location. The value on input
A10 determines whether or not AUTO PRECHARGE is
used. If AUTO PRECHARGE is selected, the row being
accessed will be precharged at the end of the WRITE
burst; if AUTO PRECHARGE is not selected, the row
will remain open for subsequent accesses. Input data
appearing on the I/Os is written to the memory array
subject to the DQM input logic level appearing coincident
with the data. If a given DQM signal is registered LOW,
the corresponding data will be written to memory; if the
DQM signal is registered HIGH, the corresponding data
inputs will be ignored, and a WRITE will not be executed
to that byte/column location.
BURST TERMINATE
The BURST TERMINATE command is used to truncate
either fixed-length or full-page bursts. The most recently
registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
SDRAM and is analagous to CAS-BEFORE-RAS (CBR)
REFRESH in conventional DRAMs. This command is
nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. Each 256Mb SDRAM
requires 8,192 AUTO REFRESH cycles every refresh
period (tREF). Providing a distributed AUTO REFRESH
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
April 2004
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command will meet the refresh requirement and ensure
that each row is refreshed. Alternatively, 8,192 AUTO
REFRESH commands can be issued in a burst at the
minimum cycle rate (tRC), once every refresh period
(tREF).
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which
must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own
AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to tRAS and
may remain in self refresh mode for an indefinite period
beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock
is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for
t
XSR, because time is required for the completion of any
internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
* Self refresh available in commercial and industrial temperatures only.
April 2004
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ABSOLUTE MAXIMUM RATINGS
CAPACITANCE (NOTE 2)
Parameter
Unit
V
V
°C
°C
°C
Parameter
Input Capacitance: CLK
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/Os
Symbol Max
Unit
pF
pF
pF
pF
Voltage on VCC, VCCQSupply relative to VSS
Voltage on NC or I/O pins relative to VSS
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
NOTE:
-1 to 4.6
-1 to 4.6
-55 to +125
-40 to +85
-55 to +150
CI1
CA
20
8
CI2
CIO
10
10
BGA THERMAL RESISTANCE
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Description
Symbol Max
Unit Notes
Junction to Ambient (No Airflow)
Junction to Ball
θJA
θJB
θJC
14.7
10.7
4.0
°C/W
°C/W
°C/W
1
1
1
Junction to Case (Top)
NOTE: Refer to PBGA Thermal Resistance Correlation Application note at
www.wedc.com in the application notes section for modeling conditions.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
VCC = +3.3V 0.3V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Supply Voltage
Symbol
VCC
VIH
VIL
II
IOZ
VOH
VOL
Min
3
2
-0.3
-5
-5
Max
3.6
VCC + 0.3
0.8
5
5
–
0.4
Units
V
V
Input High Voltage: Logic 1; All inputs (21)
Input Low Voltage: Logic 0; All inputs (21)
Input Leakage Current: Any input 0V VIN VCC (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V VOUT VCC
Output High Voltage (IOUT = -4mA)
V
µA
µA
V
2.4
–
Output Low Voltage (IOUT = 4mA)
V
IDD SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13)
VCC = +3.3V 0.3V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
Max
Units
Operating Current: Active Mode;
Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19)
ICC1
700
mA
Standby Current: Active Mode; CKE = HIGH; CS# = HIGH;
All banks active after tRCD met; No accesses in progress (3, 12, 19)
ICC3
240
mA
Operating Current: Burst Mode; Continuous burst;
ICC4
ICC7
750
20
mA
mA
Read or Write; All banks active; CAS latency = 3 (3, 18, 19)
Self Refresh Current: CKE 0.2V (27, 28)
April 2004
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11, 29)
-133
-125
-100
-66
Parameter
Symbol
tAC
tAC
tAH
tAS
tCH
tCL
tCK
tCK
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ
tHZ
tLZ
Min
Max
5.4
6
Min
Max
5.8
6
Min
Max
6
6
Min
Max
7.5
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CL = 3
CL = 2
Access time from CLK (pos. edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
0.8
1.5
1
2
3
3
8
10
1
2
1
2
1
2
3
1
2
3
3
3
CL = 3
CL = 2
10
15
1
2
1
2
1
2
15
20
1
2
1
2
1
2
Clock cycle time (22)
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
1
2
Data-in setup time
CL = 3 (10)
CL = 2 (10)
5.4
6
5.8
6
6
6
7.5
9
Data-out high-impedance time (10)
Data-out low-impedance time
Data-out hold time (load)
1
3
1.8
44
66
20
1
3
1.8
50
70
20
1
3
1.8
50
70
20
2
3
1.8
60
70
30
tOH
Data-out hold time (no load) (26)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8,192 rows) – Commercial, Industrial
Refresh period (8,192 rows) – Military
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time (7)
tOH
N
tRAS
tRC
120,000
120,000
120,000
120,000 ns
ns
ns
tRCD
tREF
tREF
tRFC
tRP
64
16
64
16
64
16
64
16
ms
ms
ns
ns
ns
ns
—
66
20
15
70
20
20
70
20
20
90
30
20
tRRD
tT
0.3
1 CLK + 7ns
1.2
0.3
1 CLK + 7ns
1.2
0.3
1 CLK + 7ns
1.2
1
1.2
1 CLK + 7ns
(23)
(24)
WRITE recovery time
tWR
15
75
15
80
15
80
15
90
ns
ns
Exit SELF REFRESH to ACTIVE command
tXSR
April 2004
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AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11,29)
Parameter/Condition
Symbol
tCCD
tCKED
tPED
-133
1
-125
1
-100
1
-66
1
1
1
0
0
2
0
4
2
1
1
2
2
3
2
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
READ/WRITE command to READ/WRITE command (17)
CKE to clock disable or power-down entry mode (14)
CKE to clock enable or power-down exit setup mode (14)
DQM to input data delay (17)
1
1
1
1
1
1
tDQD
tDQM
tDQZ
tDWD
tDAL
0
0
0
DQM to data mask during WRITEs
0
0
0
DQM to data high-impedance during READs
WRITE command to input data delay (17)
Data-in to ACTIVE command (15)
2
2
2
0
0
0
5
5
4
Data-in to PRECHARGE command (16)
tDPL
2
2
2
Last data-in to burst STOP command (17)
Last data-in to new READ/WRITE command (17)
Last data-in to PRECHARGE command (16)
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)
tBDL
1
1
1
tCDL
1
1
1
tRDL
2
2
2
tMRD
tROH
tROH
2
2
2
CL = 3
Data-out to high-impedance from PRECHARGE command (17)
CL = 2
3
3
3
2
2
2
NOTES:
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
minimum cycle rate.
1.
2.
3.
All voltages referenced to VSS.
This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
16. Timing actually specified by tWR.
I
DD is dependent on output loading and cycle rates. Specified values are obtained
17. Required clocks are specified by JEDEC functionality and are not dependent on
any timing parameter.
18. The ICC current will decrease as the CAS latency is reduced. This is due to the
fact that the maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
with minimum cycle time and the outputs open.
Enables on-chip refresh and address counters.
4.
5.
The minimum specifications are used only to indicate cycle time at which proper
operation over the full temperature range is ensured.
An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC must
be powered up simultaneously.) The two AUTO REFRESH command wake-ups
should be repeated any time the tREF refresh requirement is exceeded.
AC characteristics assume tT = 1ns.
In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
Outputs measured at 1.5V with equivalent load:
6.
21.
VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V
for a pulse width -3ns.
7.
8.
22. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
9.
23. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns after
the first clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
28. OE# high.
29. All AC timings do not count extra clock cycle needed on control signals to be
registered.
10. tHZ defines the time at which the output achieves the open circuit condition; it is
not a reference to VOH or VOL. The last valid data element will meet tOH before
going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to
1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are otherwise at valid VIH or VIL levels.
13.
ICC specifications are tested after the device is properly initialized.
14. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
April 2004
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WEDPN16M64VR-XBX
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PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA)
BOTTOM View
32.1 (1.264) MAX
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
25.1
(0.988)
MAX
19.05
(0.750)
NOM
F
E
D
C
B
A
1.27
(0.050)
NOM
0.61
(0.024)
NOM
219 x
Ø
0.762 (0.030) NOM
2.03 (0.080)
MAX
19.05 (0.750) NOM
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
April 2004
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ORDERING INFORMATION
WED P N 16M64 V R - XXX B X
DEVICE GRADE:
M = Military
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
I = Industrial
C = Commercial
PACKAGE:
B = 219 Plastic Ball Grid Array (PBGA)
FREQUENCY (MHz)
133 = 133MHz*
125 = 125MHz
100 = 100MHz
66 = 66MHz
IMPROVEMENT MARK
R = Registered
3.3V Power Supply
CONFIGURATION, 16 M x 64
SDRAM
PLASTIC
WHITE ELECTRONIC DESIGNS CORP.
*133 MHz available in Commercial and Industrial Temperatures Only
April 2004
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Document Title
16M x 64 Registered Synchronous DRAM
Revision History
Rev #
Rev 0
Rev 1
History
Release Date
July 2001
Status
Initial Release
Advanced
Advanced
Changes (Pg. 1, 3, 9, 10, 11)
September 2001
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Change speed to 66MHz-133MHz for commercial and industrial temperature.
Change speed to 66MHz-125MHz for Military temperature.
Add 125 MHz and 133 MHz AC characteristics
Correct typo on Pg. 3 Block Diagram, U4 and U5
Remove Input Leakage Address Current from DC Characteristics
Change Icc4 to 750mA
Change Icc7 to 20mA
Remove Self Refresh Current for Industrial Temperatures
Update AC Characteristics Pg. 10 and 11
1.10 Add notes 28 and 29 on Pg. 11
Changes (Pg. 1)
Rev 2
Rev 3
1.1
Change status to Preliminary
January 2002
June 2003
Preliminary
Final
Changes (Pg. 1)
1.1
1.2
Change Status to Final
Add Thermal Resistance Table
Rev 4
Rev 5
Changes (Pg. 1, 12, 13)
November 2003
April 2004
Final
1.1
Change mechanical drawing to new style
Changes (Pg. 1, 12, 13)
NRND
1.1
Change status to Not Recommened for New Designs
April 2004
Rev. 5
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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