WEDPN8M64V-125BC [WEDC]
Synchronous DRAM Module, 8MX64, 6ns, CMOS, PBGA219, 25 X 25 MM, PLASTIC, BGA-219;
| 型号： | WEDPN8M64V-125BC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Synchronous DRAM Module, 8MX64, 6ns, CMOS, PBGA219, 25 X 25 MM, PLASTIC, BGA-219 动态存储器 |
| 文件： | 总13页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WEDPN8M64V-XBX
White Electronic Designs
8Mx64 Synchronous DRAM*
GENERAL DESCRIPTION
FEATURES
ꢀ
ꢀ
High Frequency = 100, 125, 133**MHz
Package:
The 64MByte (512Mb) SDRAM is a high-speed CMOS,
dynamic random-access memory using 4 chips containing
134,217,728 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 33,554,432-bit banks is organized as 4,096 rows
by 512 columns by 16 bits.
• 219 Plastic Ball Grid Array (PBGA), 25 x 25mm
Single 3.3V 0.3V power supply
Unbuffered
Fully synchronous; all signals registered on positive
edge of system clock cycle
ꢀ
ꢀ
ꢀ
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with theACTIVE command are used to select the bank and
row to be accessed (BA0, BA1 select the bank;A0-11 select
the row). The address bits registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option.AnAUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 512Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
ꢀ
Internal pipelined operation; column address can be
changed every clock cycle
ꢀ
ꢀ
ꢀ
ꢀ
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4,096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
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Organized as 8M x 64
• User Configurable as 2 x 8M x 32 or 4 x 8M x 16
Weight: WEDPN8M64V-XBX - 2.5 grams typical
BENEFITS
ꢀ
ꢀ
ꢀ
ꢀ
41% SPACE SAVINGS
Reduced part count
Low Profile: 2.20 mm (0.087) Max
Reduced trace lengths for lower parasitic
capacitance
ꢀ
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Laminate interposer for optimum TCE match
Suitable for hi-reliability applications
Upgradeable to 16M x 64 density
(WEDPN16M64V-XB2X)
The 512Mb SDRAM is designed to operate in 3.3V, low-
power memory systems.An auto refresh mode is provided,
along with a power-saving, power-down mode.
* This product is Not Recommended for New Designs, refer to WEDPN8M64V-XB2X for
new designs.
** 133MHz available at commercial (0oC to + 70oC) temperature only.
Discrete Approach
ACTUAL SIZE
S
A
V
I
N
G
S
11.9
25
22.3
WEDPN8M64V-XBX
25
2
2
2
Area
4 x 265mm = 1061mm
625mm
41%
April 2004
Rev. 14
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WEDPN8M64V-XBX
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FIGURE 1 – PIN CONFIGURATION
Top View
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
DQ0
DQ2
DQ4
DQ5
DQ14
DQ12
DQ10
DQ8
VCC
DQ15
DQ13
DQ11
DQ9
VSS
VSS
VCC
VCC
Vss
Vss
Vss
VSS
VSS
Vss
VSS
VSS
VCC
VCC
Vss
A9
A10
A11
A8
VCC
VCC
VSS
VSS
Vss
VCC
VCC
VSS
VSS
Vss
DQ16
DQ18
DQ20
DQ22
DQ17
DQ19
DQ21
DQ23
VSS
DQ31
DQ29
DQ27
DQ26
Vss
VSS
DQ30
DQ28
DQ25
DQ24
CLK1
CKE1
VCC
A
B
C
D
E
F
DQ1
DQ3
DQ6
DQ7
A0
A2
A7
A6
A1
A5
A4
A3
DNU
NC
DNU
BA0
DNU
BA1
DNU
NC
DQML0
DQMH
0
DQML1
CAS0# WE0#
CS0# RAS0#
VCC
CLK0
CKE0
VCC
RAS1# WE1#
CAS1# CS1#
VSS
DQMH1
VCC
VSS
Vcc
VCC
VCC
G
H
J
VSS
VSS
VSS
VSS
VCC
VCC
VCC
Vcc
Vcc
Vss
Vss
VCC
VSS
VSS
VSS
VSS
Vss
VCC
VCC
VSS
VCC
Vss
CKE3
CLK3
VCC
CS3#
CKE2
CLK2
VSS
RAS2# CS2#
WE2# CAS2#
K
L
Vss
VCC
CAS3# RAS3#
VSS
DQ56
DQ57
DQ60
DQ62
Vss
DQMH
3
VCC
WE3#
DQ54
DQ52
DQ50
DQ48
DQML3
Vcc
Vcc
VSS
VCC
VCC
Vcc
Vcc
Vcc
Vss
Vss
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
Vss
Vcc
Vcc
Vss
Vss
Vss
Vcc
Vcc
Vss
Vss
VCC
VSS
VSS
DQMH
2
VSS
DQML2
DQ39
DQ38
DQ35
DQ33
VCC
M
N
P
R
T
DQ58
DQ59
DQ61
DQ63
DQ55
DQ53
DQ51
DQ49
Vcc
VSS
VCC
VCC
DQ41
DQ43
DQ45
DQ47
DQ40
DQ42
DQ44
DQ46
DQ37
DQ36
DQ34
DQ32
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
April 2004
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FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
WE0#
RAS
0
#
#
CAS
0
WE# RAS# CAS#
A
0-11
A0-11
DQ
•
0
DQ
•
0
BA0-1
BA0-1
8M x 16
U0
•
•
CLK
CKE
0
0
CLK
CKE
CS#
DQML
DQMH
•
•
•
•
CS
0
#
•
•
DQML
DQMH
0
•
•
DQ15
DQ15
0
WE1#
RAS
1
#
#
CAS
1
WE# RAS# CAS#
A0-11
DQ
0
DQ16
BA0-1
•
•
•
•
•
•
•
8M x 16
U1
•
CLK
CKE
1
1
CLK
CKE
CS#
DQML
DQMH
•
•
CS
1
#
•
•
DQML
DQMH
1
DQ15
DQ31
1
WE2#
RAS
2
#
#
CAS
2
WE# RAS# CAS#
A0-11
DQ
0
DQ32
BA0-1
•
•
•
•
•
•
•
8M x 16
U2
•
CLK
CKE
2
2
CLK
CKE
CS#
DQML
DQMH
•
•
CS
2
#
•
•
DQML
DQMH
2
DQ15
DQ47
2
WE3#
RAS
3
#
#
CAS
3
WE# RAS# CAS#
A0-11
DQ
0
DQ48
BA0-1
•
•
•
•
•
•
•
8M x 16
U3
•
CLK
CKE
3
3
CLK
CKE
CS#
DQML
DQMH
•
•
CS
3
#
•
•
DQML
DQMH
3
DQ15
DQ63
3
April 2004
Rev. 14
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All inputs and outputs are LVTTLcompatible. SDRAMs offer
REGISTER DEFINITION
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.
MODE REGISTER
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selec-tion of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
Figure 3. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-11 select the row). The address bits (A0-8) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the WRITE burst mode, and
M10 and M11 are reserved for future use.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Figure 3. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified
may result in undefined operation. Once power is applied
to VDD and VDDQ (simultaneously) and the clock is
stable (stable clock is defined as a signal cycling within
timing constraints specified for the clock pin), the SDRAM
requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100µs period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-8 when the burst length is set to two; by A2-8 when
the burst length is set to four; and by A3-8 when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page if
the boundary is reached.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for Mode Register
programming. Because the Mode Register will power up
in an unknown state, it should be loaded prior to applying
any operational command.
April 2004
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FIGURE 3 – MODE REGISTER DEFINITION
TABLE 1 – BURST DEFINITION
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Burst
Length
Starting Column
Address
A0
0
1
A0
0
1
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A0
Address Bus
2
4
0-1
1-0
0-1
1-0
Mode Register (Mx)
A1
0
0
1
Reserved* WB Op Mode CAS Latency BT
Burst Length
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
0
1
Burst Length
1
M2 M1M0
M3 = 0
M3 = 1
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
A0
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
1
2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
4
8
Reserved
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
8
1
Burst Type
M3
0
n = A0-9/8/7
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Sequential
Interleaved
Full
Page
(y)
1
Not Supported
(location 0-y)
Cn…
CAS Latency
M6 M5M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NOTES:
1.
2.
For full-page accesses: y = 512.
For a burst length of two, A1-8 select the block-of-two burst; A0 selects the
3
starting column within the block.
Reserved
Reserved
Reserved
Reserved
3.
4.
For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the
starting column within the block.
For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the
starting column within the block.
5.
6.
For a full-page burst, the full row is selected and A0-8 select the starting column.
Whenever a boundary of the block is reached within a given sequence above, the
M8
0
M7
0
M6-M0
Defined
-
Operating Mode
following access wraps within the block.
Standard Operation
7.
For a burst length of one, A0-8 select the unique column to be accessed, and
Mode Register bit M3 is ignored.
-
-
All other states reserved
Write Burst Mode
M9
0
BURST TYPE
Programmed Burst Length
Single Location Access
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
1
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.CAS Latency
The CAS latency is the delay, in clock cycles, between
the registration of a READ command and the availability
April 2004
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FIGURE 4 – CAS LATENCY
T0
T1
T2
T3
CLK
COMMAND
READ
NOP
tLZ
NOP
tOH
D
OUT
I/O
tAC
DON’T CARE
UNDEFINED
CAS Latency = 2
T1
T0
T2
T3
T4
CLK
COMMAND
READ
NOP
NOP
tLZ
NOP
tOH
D
OUT
I/O
tAC
CAS Latency = 3
of the first piece of output data. The latency can be set to
two or three clocks.
WRITE BURST MODE
When M9 = 0, the burst length programmed via M0-M2
applies to both READ and WRITE bursts; when M9 = 1,
the programmed burst length applies to READ bursts, but
write accesses are single-location (nonburst) accesses.
If a READ command is registered at clock edge n, and
the latency is m clocks, the data will be available by clock
edge n+m. The I/Os will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the
relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency
is programmed to two clocks, the I/Os will start driving
after T1 and the data will be valid by T2. Table 2 below
indicates the operating frequencies at which each CAS
latency setting can be used.
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
SPEED
-100
CAS LATENCY = 2
CAS LATENCY = 3
≤75
≤100
≤100
≤100
≤125
≤133
-125
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
-133
OPERATING MODE
COMMANDS
The normal operating mode is selected by setting M7and M8
to zero; the other combinations of values for M7 and M8 are
reserved for future use and/or test modes. The programmed
burst length applies to both READ and WRITE bursts.
The Truth Table provides a quick reference of available
commands. This is followed by a written description of each
command. Three additional Truth Tables appear following
the Operation section; these tables provide current state/
next state information.
Test modes and reserved states should not be used
because unknown operation or incompatibility with future
versions may result.
April 2004
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TRUTH TABLE — COMMANDS AND DQM OPERATION (NOTE 1)
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
CS#
H
L
L
L
L
L
L
L
RAS#
CAS#
WE#
X
H
H
H
L
L
L
H
L
DQM
X
X
ADDR
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
I/Os
X
X
X
X
Valid
Active
X
X
X
X
H
L
H
H
H
L
X
H
H
L
X
L/H 8
L/H 8
X
L
H
H
L
X
X
X
L
L
L
L
Op-Code
Write Enable/Output Enable (8)
Write Inhibit/Output High-Z (8)
–
–
–
–
–
–
–
–
L
H
–
–
Active
High-Z
NOTES:
1.
2.
3.
4.
CKE is HIGH for all commands shown except SELF REFRESH.
A0-11 define the op-code written to the Mode Register.
A0-12 provide row address, and BA0, BA1 determine which bank is made active.
A0-8 provide column address; A10 HIGH enables the auto precharge feature
(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which bank is being read from or written to.
6.
7.
8.
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
Activates or deactivates the I/Os during WRITEs (zero-clock delay) and READs
(two-clock delay).
5.
A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
COMMAND INHIBIT
The COMMAND INHIBITfunction prevents new commands
from being executed by the SDRAM, regardless of whether
the CLK signal is enabled. The SDRAM is effectively
deselected. Operations already in progress are not
affected.
address provided on inputsA0-11 selects the row. This row
remains active (or open) for accesses until a PRECHARGE
command is issued to that bank. A PRECHARGE
command must be issued before opening a different row
in the same bank.
NO OPERATION (NOP)
READ
The NO OPERATION (NOP) command is used to perform
a NOP to an SDRAM which is selected (CS# is LOW). This
prevents unwanted commands from being registered during
idle or wait states. Operations already in progress are not
affected.
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-8
selects the starting column location. The value on inputA10
determines whether or notAUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses. Read data appears on the I/Os
subject to the logic level on the DQM inputs two clocks
earlier. If a given DQM signal was registered HIGH, the
corresponding I/Os will be High-Z two clocks later; if the
DQM signal was registered LOW, the I/Os will provide
valid data.
LOAD MODE REGISTER
The Mode Register is loaded via inputs A0-11. See Mode
Register heading in the Register Definition section. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
April 2004
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WRITE
BURST TERMINATE
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-8
selects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the WRITE burst; if AUTO
PRECHARGE is not selected, the row will remain open for
subsequent accesses. Input data appearing on the I/Os is
written to the memory array subject to the DQM input logic
level appearing coincident with the data. If a given DQM
signal is registered LOW, the corresponding data will be
written to memory; if the DQM signal is registered HIGH,
the corresponding data inputs will be ignored, and a WRITE
will not be executed to that byte/column location.
The BURST TERMINATE command is used to truncate
either fixed-length or full-page bursts. The most recently
registered READ or WRITE command prior to the BURST
TERMINATE command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analagous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care” during
an AUTO REFRESH command. Each 128Mb SDRAM
requires 4,096 AUTO REFRESH cycles every refresh
period (tREF). Providing a distributed AUTO REFRESH
command will meet the refresh requirement and ensure that
each row is refreshed.Alternatively, 4,096AUTO REFRESH
commands can be issued in a burst at the minimum cycle
rate (tRC), once every refresh period (tREF).
PRECHARGE
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command is
issued. InputA10 determines whether one or all banks are
to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands being
issued to that bank.
SELF REFRESH*
The SELF REFRESH command can be used to retain data
in the SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the SDRAM retains
data without external clocking. The SELF REFRESH
command is initiated like an AUTO REFRESH command
except CKE is disabled (LOW). Once the SELF REFRESH
command is registered, all the inputs to the SDRAM
become “Don’t Care,” with the exception of CKE, which
must remain LOW.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A10 to enableAUTO PRECHARGE in conjunction
with a specific READ or WRITE command. Aprecharge of
the bank/row that is addressed with the READ or WRITE
command is automatically performed upon completion of
the READ or WRITE burst, except in the full-page burst
mode, where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled or
disabled for each individual READ or WRITE command.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain
in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock
is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands issued (a minimum of two clocks) for tXSR,
because time is required for the completion of any internal
refresh in progress.
AUTO PRECHARGE ensures that the precharge is initiated
at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the
precharge time (tRP) is completed. This is determined as
if an explicit PRECHARGE command was issued at the
earliest possible time.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
*Self Refresh available in commercial and industrial temperatures only.
April 2004
Rev. 14
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDPN8M64V-XBX
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE (NOTE 2)
Parameter
Unit
V
V
°C
°C
°C
Parameter
Input Capacitance: CLK
Addresses, BA0-1 Input Capacitance
Input Capacitance: All other input-only pins
Input/Output Capacitance: I/Os
Symbol Max
Unit
pF
pF
pF
pF
Voltage on VCC, VCCQSupply relative to VSS
Voltage on NC or I/O pins relative to VSS
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
NOTE:
-1 to 4.6
-1 to 4.6
-55 to +125
-40 to +85
-55 to +150
CI1
CA
CI2
CIO
8
30
8
12
BGA THERMAL RESISTANCE
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
Description
Symbol Max
Unit Notes
Junction to Ambient (No Airflow)
Junction to Ball
θJA
θJB
θJC
14.8
10.0
4.8
°C/W
°C/W
°C/W
1
1
1
Junction to Case (Top)
NOTE 1: Refer to BGA Thermal Resistance Correlation application note at www.
whiteedc.com in the application notes section for modeling conditions.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
VCC = +3.3V 0.3V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Supply Voltage
Input High Voltage: Logic 1; All inputs (21)
Input Low Voltage: Logic 0; All inputs (21)
Input Leakage Current: Any input 0V VIN VCC (All other pins not under test = 0V)
Input Leakage Address Current: Any input 0V VIN VCC (All other pins not under test = 0V)
Output Leakage Current: I/Os are disabled; 0V VOUT VCC
Output Levels:
Output High Voltage (IOUT = -4mA)
Output Low Voltage (IOUT = 4mA)
Symbol
VCC
VIH
VIL
II
II
IOZ
VOH
Min
3
2
-0.3
-5
-20
-5
Max
3.6
VCC + 0.3
0.8
5
Units
V
V
V
µA
µA
µA
V
20
5
–
2.4
VOL
–
0.4
V
IDD SPECIFICATIONS AND CONDITIONS (NOTES 1,6,11,13)
VCC = +3.3V 0.3V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
Max
Units
Operating Current: Active Mode;
Burst = 2; Read or Write; tRC = tRC (min); CAS latency = 3 (3, 18, 19)
ICC1
650
mA
Standby Current: Active Mode; CKE = HIGH; CS = HIGH;
All banks active after tRCD met; No accesses in progress (3, 12, 19)
ICC3
200
mA
Operating Current: Burst Mode; Continuous burst;
ICC4
ICC7
650
10
mA
mA
Read or Write; All banks active; CAS latency = 3 (3, 18, 19)
Self Refresh Current: CKE 0.2V (27)
April 2004
Rev. 14
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDPN8M64V-XBX
White Electronic Designs
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 5, 6, 8, 9, 11)
-100
-125
-133
Parameter
Symbol
tAC
tAC
tAH
tAS
tCH
tCL
tCK
tCK
tCKH
tCKS
tCMH
tCMS
tDH
tDS
tHZ
tHZ
tLZ
Min
Max
7
7
Min
Max
6
6
Min
Max
5.5
5.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
CL = 3
CL = 2
Access time from CLK (pos.
edge)
Address hold time
Address setup time
CLK high-level width
CLK low-level width
1
2
3
1
2
3
3
8
10
1
2
1
2
0.8
1.5
2.5
2.5
7.5
10
0.8
1.5
0.8
1.5
0.8
1.5
3
CL = 3
CL = 2
10
13
1
2
1
2
1
2
Clock cycle time (22)
CKE hold time
CKE setup time
CS#, RAS#, CAS#, WE#, DQM hold time
CS#, RAS#, CAS#, WE#, DQM setup time
Data-in hold time
1
2
Data-in setup time
CL = 3 (10)
CL = 2 (10)
7
7
6
6
5.5
5.5
Data-out high-impedance
time
Data-out low-impedance time
Data-out hold time (load)
Data-out hold time (no load) (26)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (8,192 rows) – Commercial,
Industrial
Refresh period (8,192 rows) – Military
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time (7)
1
3
1.8
50
70
20
1
3
1.8
45
68
20
1
3
1.8
44
66
20
tOH
tOH
N
tRAS
tRC
tRCD
tREF
120,000
120,000
120,000
64
16
64
16
64
–
tREF
tRFC
tRP
tRRD
tT
ms
ns
ns
ns
ns
—
ns
ns
70
20
15
0.3
70
20
16
0.3
70
20
15
0.3
1.2
1.2
(23)
1 CLK + 7ns
1 CLK + 7ns
1 CLK + 7.5ns
WRITE recovery time
(24)
Exit SELF REFRESH to ACTIVE command
tWR
15
80
15
78
15
75
tXSR
April 2004
Rev. 14
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDPN8M64V-XBX
White Electronic Designs
AC FUNCTIONAL CHARACTERISTICS (NOTES 5,6,7,8,9,11)
Parameter/Condition
Symbol
tCCD
tCKED
tPED
-100
1
-125
1
-133
1
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
READ/WRITE command to READ/WRITE command (17)
CKE to clock disable or power-down entry mode (14)
CKE to clock enable or power-down exit setup mode (14)
DQM to input data delay (17)
1
1
1
1
1
1
tDQD
tDQM
tDQZ
tDWD
tDAL
0
0
0
DQM to data mask during WRITEs
0
0
0
DQM to data high-impedance during READs
WRITE command to input data delay (17)
Data-in to ACTIVE command (15)
2
2
2
0
0
0
4
5
5
Data-in to PRECHARGE command (16)
tDPL
2
2
2
Last data-in to burst STOP command (17)
Last data-in to new READ/WRITE command (17)
Last data-in to PRECHARGE command (16)
LOAD MODE REGISTER command to ACTIVE or REFRESH command (25)
tBDL
1
1
1
tCDL
1
1
1
tRDL
2
2
2
tMRD
tROH
tROH
2
2
2
CL = 3
CL = 2
3
3
3
Data-out to high-impedance from PRECHARGE command (17)
2
2
2
NOTES:
14. Timing actually specified by tCKS; clock(s) specified as a reference only at
minimum cycle rate.
1.
2.
3.
All voltages referenced to VSS.
This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at
IDD is dependent on output loading and cycle rates. Specified values are obtained
minimum cycle rate.
with minimum cycle time and the outputs open.
16. Timing actually specified by tWR.
4.
5.
Enables on-chip refresh and address counters.
17. Required clocks are specified by JEDEC functionality and are not dependent on
The minimum specifications are used only to indicate cycle time at which proper
any timing parameter.
operation over the full temperature range is ensured.
18. The ICC current will decrease as the CAS latency is reduced. This is due to the
fact that the maximum cycle rate is slower as the CAS latency is reduced.
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
6.
An initial pause of 100µs is required after power-up, followed by two AUTO
REFRESH commands, before proper device operation is ensured. (VCC must
be powered up simultaneously.) The two AUTO REFRESH command wake-ups
should be repeated any time the tREF refresh requirement is exceeded.
7.
8.
AC characteristics assume tT = 1ns.
21. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width 3ns, and the pulse width
cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V
for a pulse width 3ns.
In addition to meeting the transition rate specification, the clock and CKE must
transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.
22. The clock frequency must remain constant (stable clock is defined as a signal
cycling within timing constraints specified for the clock pin) during access or
precharge states (READ, WRITE, including tWR, and PRECHARGE commands).
CKE may be used to reduce the data rate.
9.
Outputs measured at 1.5V with equivalent load:
23. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns
after the first clock delay, after the last WRITE is executed.
24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26. Parameter guaranteed by design.
27. Self refresh available in commercial and industrial temperatures only.
10. tHZ defines the time at which the output achieves the open circuit condition; it is
not a reference to VOH or VOL. The last valid data element will meet tOH before
going High-Z.
11.
AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to
1.5V crossover point.
12. Other input signals are allowed to transition no more than once every two clocks
and are otherwise at valid VIH or VIL levels.
13. ICC specifications are tested after the device is properly initialized.
April 2004
Rev. 14
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDPN8M64V-XBX
White Electronic Designs
PACKAGE 740: 219 PLASTIC BALL GRID ARRAY (PBGA)
Bottom View
25.1 (0.988) SQ. MAX
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
19.05 (0.750)
NOM
F
E
D
C
B
A
1.27
(0.050)
NOM
0.61
(0.024)
NOM
219 x
Ø
0.762 (0.030) NOM
2.03 (0.080)
MAX
19.05 (0.750) NOM
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
Note: This product is Not Recommended for New Designs, refer to WEDPN8M64V-XB2X for new designs.
April 2004
Rev. 14
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDPN8M64V-XBX
White Electronic Designs
ORDERING INFORMATION
WED P N 8M 64 V - XXX B X
DEVICE GRADE:
M = Military
I = Industrial
-55°C to +125°C
-40°C to +85°C
C = Commercial 0°C to +70°C
PACKAGE:
B = 219 Plastic Ball Grid Array (PBGA)
FREQUENCY (MHz)
100 = 100MHz
125 = 125MHz
133 = 133MHz*
3.3V Power Supply
CONFIGURATION, 8M x 64
SDRAM
PLASTIC
WHITE ELECTRONIC DESIGNS CORP.
* 133MHz available in commercial temperature only.
Note: This product is Not Recommended for New Designs, refer to WEDPN8M64V-XB2X for new designs.
April 2004
Rev. 14
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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