WEDPND16M72S-250BI [WEDC]
DDR DRAM, 16MX72, 0.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219;
| 型号： | WEDPND16M72S-250BI |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | DDR DRAM, 16MX72, 0.8ns, CMOS, PBGA219, 32 X 25 MM, PLASTIC, BGA-219 动态存储器 双倍数据速率 内存集成电路 |
| 文件： | 总16页 (文件大小：441K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WEDPND16M72S-XBX
White Electronic Designs
16Mx72 DDR SDRAM Preliminary*
FEATURES
BENEFITS
n
High Frequency = 200, 250, 266MHz
n
n
n
40% SPACE SAVINGS
n
Package:
Reduced part count
• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm
2.5V 0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Reduced I/O count
n
n
n
n
n
• 34% I/O Reduction
n
n
n
n
Reduced trace lengths for lower parasitic capacitance
Suitable for hi-reliability applications
Laminate interposer for optimum TCE match
Differential clock inputs (CLK and CLK)
Commands entered on each positive CLK edge
Internal pipelined double-data-rate (DDR) architecture;
two data accesses per clock cycle
Upgradeable to 32M x 72 density (contact factory for
information)
* This data sheet describes a product that is not fully qualified or characterized
and is subject to change without notice.
n
n
Programmable Burst length: 2,4 or 8
Bidirectional data strobe (DQS) transmitted/received
with data, i.e., source-synchronous data capture (one
per byte)
GENERAL DESCRIPTION
The 128MByte (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 5 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM. Each of the chip’s 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits.
n
DQS edge-aligned with data for READs; center-aligned
with data for WRITEs
n
n
n
n
n
n
n
n
n
DLL to align DQ and DQS transitions with CLK
Four internal banks for concurrent operation
Two data mask (DM) pins for masking write data
Programmable IOL/IOH option
The 128 MB DDR SDRAM uses a double data rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock
cycle at the I/O pins. A single read or write access for the
128MB DDR SDRAM effectively consists of a single 2n-bit
wide, one-clock-cycle data tansfer at the internal DRAM core
and two corresponding n-bit wide, one-half-clock-cycle
data transfers at the I/O pins.
Auto precharge option
Auto Refresh and Self Refresh Modes
Commercial, Industrial and Military Temperature Ranges
Organized as 16M x 72
Weight: WEDPND16M72S-XBX - 2.5 grams typical
A bidirectional data strobe (DQS) is transmitted externally, along
with data, for use in data capture at the receiver. DQS is a
Actual Size
WEDPND16M72S-XBX
Monolithic Solution
S
11.9
11.9
11.9
11.9
11.9
A
V
I
25
66
TSOP
66
TSOP
66
TSOP
66
TSOP
66
TSOP
White Electronic Designs
22.3
WEDPND16M72S-XBX
N
G
32
S
2
2
2
40%
Area
5 x 265mm = 1328mm
800mm
I/O
Count
5 x 66 pins = 330 pins
219 Balls
34%
May 2003 Revꢀ 4
1
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WEDPND16M72S-XBX
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FIGꢀ 1 PIN CONFIGURATION
TOP VIEW
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
DQ
DQ
DQ
DQ
0
DQ14 DQ15
DQ12 DQ13
DQ10 DQ11
V
SS
V
SS
A
A
A
9
A
10
A
11
A
A
A
8
1
3
V
CC
Q
V
CC
Q
DQ16 DQ17 DQ31
VSS
A
B
C
D
E
F
DQ
DQ
DQ
DQ
1
3
6
7
2
4
5
V
SS
V
SS
0
2
A
7
A
6
V
CC
V
CC
DQ18 DQ19 DQ29 DQ30
DQ20 DQ21 DQ27 DQ28
DQ22 DQ23 DQ26 DQ25
VCC
VCC
A
5
A
4
V
V
SS
V
V
SS
DQ
8
DQ
9
V
CC
Q
VCCQ
A12
DNU DNU DNU
SS
SS
DQSH0
DQML0
V
V
V
V
V
V
V
V
CC
DQMH0 DQSH3 DQSL0
BA
0
BA
1
DQSL1 DQSH1 VREF DQML1
RAS1 WE1
V
V
V
SS
SS
SS
NC
DQ24
CAS0 WE0
CC
CLK
0
DQSL3
DQMH1 CLK1
CS
0
RAS0
CC
CC
CC
CC
CC
CC
CKE0 CLK0
CAS1
CS
1
CLK1 CKE1
G
H
J
V
V
SS
V
V
SS
SS
V
V
CC
CC
Q
Q
V
V
SS
SS
V
CC
CC
V
V
SS
Vss
V
V
CC
CC
Q
Q
V
CC
CC
SS
V
SS
V
V
V
V
SS
SS
SS
SS
V
CLK3 CKE3
CS3 DQSL4
CLK2 CKE2
RAS2 CS2
WE2 CAS2
K
L
NC
CLK3
CAS3 RAS3
DQSL2 CLK2
DQMH4
DQ73
DQ75
DQ77
DQ79
DQ56 DQMH3
WE3 DQML3 CKE4
CLK4 CAS4 WE4 RAS4 CS4
DQMH2
DQML2
DQ39
M
N
P
R
T
DQ57 DQ58 DQ55 DQ54 DQSH4 CLK4
DQ72 DQ71 DQ70 DQML4 DQSH2 DQ41 DQ40 DQ37 DQ38
DQ60 DQ59 DQ53 DQ52
DQ62 DQ61 DQ51 DQ50
Vss DQ63 DQ49 DQ48
V
SS
V
SS
DQ74 DQ69 DQ68
V
CC
V
CC
DQ43 DQ42 DQ36 DQ35
DQ45 DQ44 DQ34 DQ33
VCC
VCC
DQ76 DQ67 DQ66 Vss
V
V
SS
SS
V
CC
Q
V
CC
Q
DQ78 DQ65 DQ64
V
SS
DQ47 DQ46 DQ32
VCC
NOTE: DNU = Do Not Use; to be left unconnected for future upgrades.
NC = Not Connected Internally.
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WE
0
RAS
CAS
0
0
FIGꢀ 2 FUNCTIONAL BLOCK DIAGRAM
WE RAS CAS
V
REF
0-12
BA0-1
V
REF
A
0-12
A
DQ
0
DQ
0
BA0-1
CLK
=
Y
=
Y
CLK
0
=
Y
=
Y
CLK
0
0
0
0
0
0
0
CLK
=
Y
=
Y
U0
CKE
CKE
=
Y
=
Y
CS
CS
=
Y
=
Y
=
Y
=
Y
DQML
DQMH
DQSL
DQSH
DQML
DQMH
DQSL
DQSH
DQ15
DQ15
WE
1
RAS
CAS
1
1
WE RAS
CAS
V
REF
A0-12
DQ
0
DQ16
BA0-1
CLK
CLK
=
Y
=
Y
CLK
1
=
Y
=
Y
CLK
1
1
1
1
1
1
1
=
Y
=
Y
U1
CKE
CKE
=
Y
=
Y
=
Y
CS
CS
=
Y
=
Y
=
Y
DQML
DQMH
DQSL
DQSH
DQML
DQMH
DQSL
DQSH
DQ15
DQ31
WE
2
RAS
CAS
2
2
WE RAS
CAS
VREF
A0-12
DQ
0
DQ32
BA0-1
CLK
=
Y
=
Y
CLK
2
2
=
Y
=
Y
CLK
CLK
=
Y
=
Y
U2
CKE
2
2
2
2
CKE
=
Y
=
Y
=
Y
CS
CS
=
Y
=
Y
=
Y
DQML
DQMH
DQML
DQMH
DQSL
DQSH
DQ15
DQ47
DQSL
DQSH
2
2
WE
3
RAS
CAS
3
3
WE RAS
CAS
VREF
A0-12
DQ
0
DQ48
BA0-1
CLK
CLK
=
Y
=
Y
CLK
3
=
Y
=
Y
CLK
3
3
3
3
3
3
3
=
Y
=
Y
U3
=
Y
CKE
CKE
=
Y
=
Y
=
Y
CS
CS
=
Y
=
Y
DQML
DQMH
DQSL
DQSH
DQML
DQMH
DQSL
DQSH
DQ15
DQ63
WE
4
RAS
CAS
4
4
WE RAS
CAS
VREF
A0-12
DQ
0
DQ64
BA0-1
CLK
=
Y
=
Y
CLK
4
=
Y
=
Y
CLK4
CKE4
CS4
CLK
=
Y
=
Y
U4
CKE
=
Y
=
Y
=
Y
=
Y
CS
=
Y
=
Y
DQML
DQMH
4
4
DQML
DQMH
DQ15
DQ79
DQSL
DQSH
4
4
DQSL
DQSH
3
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strobe transmitted by the DDR SDRAM during READs and by
the memory contoller during WRITEs. DQS is edge-aligned
with data for READs and center-aligned with data for WRITEs.
Each chip has two data strobes, one for the lower byte and
one for the upper byte.
ing device initialization, register definition, command de-
scriptions and device operation.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a pre-
defined manner. Operational procedures other than those
specified may result in undefined operation. Power must
first be applied to VCC and VCCQ simultaneously, and then to
VREF (and to the system VTT). VTT must be applied after VCCQ
to avoid device latch-up, which may cause permanent dam-
age to the device. VREF can be applied any time after VCCQ
but is expected to be nominally coincident with VTT. Except
for CKE, inputs are not recognized as valid until after VREF is
applied. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after VCC is applied. Maintaining an LVCMOS LOW
level on CKE during power-up is required to ensure that the
DQ and DQS outputs will be in the High-Z state, where they
will remain until driven in normal operation (by a read ac-
cess). After all power supply and reference voltages are
stable, and the clock is stable, the DDR SDRAM requires a
200ms delay prior to applying an executable command.
The 128MB DDR SDRAM operates from a differential clock (CLK and
CLK); the crossing of CLK going HIGH and CLK going LOW will be
referred to as the positive edge of CLK. Commands (address and
control signals) are registered at every positive edge of CLK. Input
data is registered on both edges of DQS, and output data is refer-
enced to both edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed. The address bits registered coincident with
the READ or WRITE command are used to select the bank
and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE
burst lengths of 2, 4, or 8 locations. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst access.
Once the 200ms delay has been satisfied, a DESELECT or
NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a PRECHARGE
ALL command should be applied. Next a LOAD MODE REG-
ISTER command should be issued for the extended mode
register (BA1 LOW and BA0 HIGH) to enable the DLL, fol-
lowed by another LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL and to
program the operating parameters. Two-hundred clock
cycles are required between the DLL reset and any READ
command. A PRECHARGE ALL command should then be
applied, placing the device in the all banks idle state.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-
saving power-down mode.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command which is then followed by a READ or WRITE
command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to
be accessed (BA0 and BA1 select the bank, A0-12 select
the row). The address bits registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.
Once in the idle state, two AUTO REFRESH cycles must be
performed (tRFC must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with the
reset DLL bit deactivated (i.e., to program operating param-
eters without resetting the DLL) is required. Following these
requirements, the DDR SDRAM is ready for normal operation.
REGISTER DEFINITION
MODE REGISTER
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information cover-
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
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BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
selection of a burst length, a burst type, a CAS latency, and
an operating mode, as shown in Figure 3. The Mode Regis-
ter is programmed via the MODE REGISTER SET command
(with BA0 = 0 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses
power. (Except for bit A8 which is self clearing).
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are idle
and no bursts are in progress, and the controller must wait
the specified time before initiating the subsequent opera-
tion. Violating either of these requirements will result in un-
specified operation.
READ LATENCY
The READ latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the first
bit of output data. The latency can be set to 2 or 2.5 clocks.
Mode register bits A0-A2 specify the burst length, A3 speci-
fies the type of burst (sequential or interleaved), A4-A6 specify
the CAS latency, and A7-A12 specify the operating mode.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
BURST LENGTH
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
Read and write accesses to the DDR SDRAM are burst ori-
ented, with the burst length being programmable, as shown
in Figure 3. The burst length determines the maximum num-
ber of column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 2, 4 or 8 loca-
tions are available for both the sequential and the inter-
leaved burst types.
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
CAS
SPEED
-200
LATENCY = 2
LATENCY = 2ꢀ5
£ 75
£ 100
£ 100
£ 100
£ 125
£ 133
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
-250
-266
When a READ or WRITE command is issued, a block of col-
umns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, meaning
that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai when the
burst length is set to two; by A2-Ai when the burst length is
set to four (where Ai is the most significant column address
for a given configuration); and by A3-Ai when the burst
length is set to eight. The remaining (least significant) ad-
dress bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to both
READ and WRITE bursts.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to zero,
and bits A0-A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command with
bits A7 and A9-A12 each set to zero, bit A8 set to one, and
bits A0-A6 set to the desired values. Although not required,
JEDEC specifications recommend when a LOAD MODE REG-
ISTER command is issued to reset the DLL, it should always
be followed by a LOAD MODE REGISTER command to se-
lect normal operating mode.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
5
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FIGꢀ 3 MODE REGISTER DEFINITION
TABLE 1 - BURST DEFINITION
Burst Starting Column
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
Length
Address
A0
0
A10
A9
A8
A7
A
6
A5
A4
A
3
A
2
A
1
A0
BA1
BA0
A12
A11
Address Bus
2
0-1
1-0
0-1
1-0
1
Mode Register (Mx)
A1
0
A0
0
0*
0*
Operating Mode
CAS Latency BT
Burst Length
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
*
M14 and M13
(BA0 and BA1 must be
"0, 0" to select
4
0
1
1
0
Burst Length
the base mode register
(vs. the extended
mode register).
1
1
M2 M1 M0
M3 = 0
M3 = 1
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
A2
0
A1
0
A0
0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
4
4
0
0
1
8
8
0
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8
0
1
1
1
0
0
1
0
1
1
1
0
Burst Type
M3
1
1
1
0
1
Sequential
Interleaved
NOTES:
CAS Latency
1. For a burst length of two, A1-Ai select two-data-element block; A0 selects
the starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1 select
the starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block; A0-2
select the starting column within the block.
4. Whenever a boundary of the block is reached within a given sequence
above, the following access wraps within the block.
M6 M5 M4
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
Reserved
Reserved
2.5
Reserved
M11
0
M10
0
M9
0
M8
0
M7
0
M6-M0
Valid
Operating Mode
M12
0
EXTENDED MODE REGISTER
Normal Operation
0
0
0
1
0
0
Valid
Normal Operation/Reset DLL
All other states reserved
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength, and
QFC. These functions are controlled via the bits shown in
Figure 5. The extended mode register is programmed via
the LOAD MODE REGISTER command to the mode register
(with BA0 = 1 and BA1 = 0) and will retain the stored
information until it is programmed again or the device loses
power. The enabling of the DLL should always be followed
by a LOAD MODE REGISTER command to the mode register
(BA0/BA1 both LOW) to reset the DLL.
-
-
-
-
-
-
-
The extended mode register must be loaded when all banks
are idle and no bursts are in progress, and the controller
must wait the specified time before initiating any subse-
quent operation. Violating either of these requirements
could result in unspecified operation.
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FIGꢀ 5 EXTENDED MODE REGISTER DEFINITION
FIGꢀ 4 CAS LATENCY
T0
T1
T2
T2n
T3
T3n
A
10
A9
A8
A7
A6
A
5
A
4
A
3
A
2
A
1
A0
BA1
BA0
A12
A
11
Address Bus
CLK
CLK
COMMAND
READ
NOP
NOP
NOP
Extended Mode
Register (Ex)
1
1
1
0
QFC DS DLL
Operating Mode
CL = 2
DQS
DQ
E0
DLL
0
1
Enable
Disable
T0
T1
T2
T2n
T3
T3n
CLK
CLK
E1
0
Drive Strength
Normal
COMMAND
READ
NOP
NOP
NOP
1
Reduced
CL = 2.5
2
E2
0
QFC Function
Disabled
DQS
DQ
-
Reserved
E2, E1, E0
Operating Mode
Reserved
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3
Valid
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
0
-
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
Reserved
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFE function is not supported.
DATA
DON'T CARE
TRANSITIONING DATA
OUTPUT DRIVE STRENGTH
DESELECT
The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM supports an option for
reduced drive. This option is intended for the support of
the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
The DESELECT function (CS HiGH) prevents new commands
from being executed by the DDR SDRAM. The SDRAM is
effectively deselected. Operations already in progress are
not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to perform a
NOP to the selected DDR SDRAM (CS is LOW). This prevents
unwanted commands from being registered during idle or
wait states. Operations already in progress are not affected.
DLL ENABLE/DISABLE
The DLL must be enabled for normal operation. DLL enable
is required during power-up initialization and upon return-
ing to normal operation after having disabled the DLL for the
purpose of debug or evaluation. (When the device exits
self refresh mode, the DLL is enabled automatically.) Any
time the DLL is enabled, 200 clock cycles must occur be-
fore a READ command can be issued.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The LOAD
MODE REGISTER command can only be issued when all
banks are idle, and a subsequent executable command
cannot be issued until tMRD is met.
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
7
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TRUTH TABLE - COMMANDS (NOTE 1)
NAME (FUNCTION)
CS
H
L
RAS
CAS
WE
X
ADDR
X
DESELECT(NOP)(9)
X
H
L
X
H
H
L
NO OPERATION (NOP) (9)
H
H
H
L
X
ACTIVE (Select bank and activate row) ( 3)
READ (Select bank and column, and start READ burst) (4)
WRITE (Select bank and column, and start WRITE burst) (4)
BURST TERMINATE (8)
L
Bank/Row
Bank/Col
Bank/Col
X
L
H
H
H
L
L
L
L
H
H
L
L
PRECHARGE (Deactivate row in bank or banks) ( 5)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
LOAD MODE REGISTER (2)
L
L
Code
X
L
L
H
L
L
L
L
Op-Code
TRUTH TABLE - DM OPERATION
NAME (FUNCTION)
WRITE ENABLE (10)
WRITE INHIBIT (10)
DM
L
DQs
Valid
X
H
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1 select either the mode register (0, 0) or the extended mode register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-8 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for
WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
ACTIVE
PRECHARGE is not selected, the row will remain open for
subsequent accesses.
The ACTIVE command is used to open (or activate) a row in
a particular bank for a subsequent access. The value on the
BA0, BA1 inputs selects the bank, and the address pro-
vided on inputs A0-12 selects the row. This row remains
active (or open) for accesses until a PRECHARGE command
is issued to that bank. A PRECHARGE command must be
issued before opening a different row in the same bank.
WRITE
The WRITE command is used to initiate a burst write access to
an active row. The value on the BA0, BA1 inputs selects the
bank, and the address provided on inputs A0-8 selects the
starting column location. The value on input A10 determines
whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE
is selected, the row being accessed will be precharged at the
end of the WRITE burst; if AUTO PRECHARGE is not selected,
the row will remain open for subsequent accesses. Input data
appearing on the D/Qs is written to the memory array subject
to the DQM input logic level appearing coincident with the
data. If a given DQM signal is registered LOW, the correspond-
ing data will be written to memory; if the DQM signal is regis-
tered HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column location.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-8 se-
lects the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed will
be precharged at the end of the READ burst; if AUTO
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PRECHARGE
AUTO REFRESH
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is is-
sued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer in
the current bank and does not violate any other timing pa-
rameters. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank is to
be precharged, inputs BA0, BA1 select the bank. Otherwise
BA0, BA1 are treated as “Don’t Care.” Once a bank has been
precharged, it is in the idle state and must be activated prior
to any READ or WRITE commands being issued to that bank.
A PRECHARGE command will be treated as a NOP if there is
no open row in that bank (idle state), or if the previously
open row is already in the process of precharging.
AUTO REFRESH is used during normal operation of the DDR
SDRAM and is analogous to CAS-BEFORE-RAS (CBR) RE-
FRESH in conventional DRAMs. This command is nonpersis-
tent, so it must be issued each time a refresh is required.
The addressing is generated by the internal refresh control-
ler. This makes the address bits “Don’t Care” during an AUTO
REFRESH command. Each DDR SDRAM requires AUTO RE-
FRESH cycles at an average interval of 7.8125ms (maximum).
To allow for improved efficiency in scheduling and switch-
ing between tasks, some flexibility in the absolute refresh
interval is provided. A maximum of eight AUTO REFRESH
commands can be posted to any given DDR SDRAM, mean-
ing that the maximum absolute interval between any AUTO
REFRESH command and the next AUTO REFRESH command
is 9 x 7.8125ms (70.3ms). This maximum absolute interval is
to allow future support for DLL updates internal to the DDR
SDRAM to be restricted to AUTO REFRESH cycles, without
allowing excessive drift in tAC between updates.
AUTO PRECHARGE
Although not a JEDEC requirement, to provide for future func-
tionality features, CKE must be active (High) during the AUTO
REFRESH period. The AUTO REFRESH period begins when the
AUTO REFRESH command is registered and ends tRFC later.
AUTO PRECHARGE is a feature which performs the same indi-
vidual-bank PRECHARGE function described above, but without
requiring an explicit command. This is accomplished by using
A10 to enable AUTO PRECHARGE in conjunction with a specific
READ or WRITE command. A precharge of the bank/row that is
addressed with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE burst. AUTO
PRECHARGE is nonpersistent in that it is either enabled or dis-
abled for each individual READ or WRITE command. The device
supports concurrent auto precharge if the command to the other
bank does not interrupt the data transfer to the current bank.
SELF REFRESH*
The SELF REFRESH command can be used to retain data in
the DDR SDRAM, even if the rest of the system is powered
down. When in the self refresh mode, the DDR SDRAM re-
tains data without external clocking. The SELF REFRESH com-
mand is initiated like an AUTO REFRESH command except
CKE is disabled (LOW). The DLL is automatically disabled
upon entering SELF REFRESH and is automatically enabled
upon exiting SELF REFRESH (200 clock cycles must then
occur before a READ command can be issued). Input sig-
nals except CKE are “Don’t Care” during SELF REFRESH.
AUTO PRECHARGE ensures that the precharge is initiated at the
earliest valid stage within a burst. This “earliest valid stage” is
determined as if an explicit precharge command was is-
sued at the earliest possible time, without violating tRAS
(MIN).The user must not issue another command to the same
bank until the precharge time (tRP) is completed. This is deter-
mined as if an explicit PRECHARGE command was issued at
the earliest possible time, without violating tRAS (MIN).
The procedure for exiting self refresh requires a sequence of
commands. First, CLK must be stable prior to CKE going back
HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP
commands issued for tXSNR, because time is required for the
completion of any internal refresh in progress.
BURST TERMINATE
A simple algorithm for meeting both refresh and DLL re-
quirements is to apply NOPs for 200 clock cycles before
applying any other command.
The BURST TERMINATE command is used to truncate READ
bursts (with auto precharge disabled). The most recently
registered READ command prior to the BURST TERMINATE
command will be truncated. The open page which the READ
burst was terminated from remains open.
* Self refresh available in commercial and industrial temperatures only.
9
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ABSOLUTE MAXIMUM RATINGS
CAPACITANCE (NOTE 13)
Parameter
Symbol Max
Unit
Parameter
Unit
V
Input Capacitance: CLK
CI1
CA
CI2
CIO
8
30
9
pF
Voltage on VCC, VCCQ Supply relative to Vss
Voltage on I/O pins relative to Vss
Operating Temperature TA (Mil)
Operating Temperature TA (Ind)
Storage Temperature, Plastic
-1 to 3.6
-1 to 3.6
V
Addresses, BA0-1 Input Capacitance
InputCapacitance:Allotherinput-onlypins
Input/OutputCapacitance:I/Os
pF
pF
pF
-55 to +125
-40 to +85
-55 to +150
°C
°C
12
°C
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
BGATHERMAL RESISTANCE
Description
Symbol Max Units Notes
Junction to Ambient
(No Airflow)
Theta JA 13.3 °C/W
1
Junction to Ball
Theta JB 9.9 °C/W
1
1
Junction to Case (Top) Theta JC 3.8 °C/W
Note 1: Refer to AN #0001 at www.whiteedc.com in
the application notes section for modeling conditions.
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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 6)
(VCC = +2ꢀ5V ±0ꢀ2V; TA = -55°C TO +125°C)
Parameter/Condition
Symbol
Units
Min
Max
SupplyVoltage
VCC
VCCQ
VIH
VIL
II
2.3
2.7
V
V
I/OSupplyVoltage
2.3
VREF - 0.04
-0.3
2.7
InputHighVoltage:Logic1;Allinputs(21)
InputLowVoltage:Logic0;Allinputs(21)
VREF + 0.04
V
VREF - 0.15
V
InputLeakageCurrent:Anyinput0V £ VIN £ VCC(Allotherpinsnotundertest=0V)
InputLeakageAddressCurrent(Allotherpinsnotundertest=0V)
OutputLeakageCurrent:I/Osaredisabled;0V£ VOUT £ VCC
-2
2
10
5
µA
µA
µA
II
-10
IOZ
-5
OutputLevels:Fulldriveoption-x4, x8, x16
High Current (VOUT =VCCQ -0.373V, minimumVREF, minimumVTT)
LowCurrent(VOUT =0.373V, maximumVREF, maximumVTT)
IOH
IOL
-16.8
16.8
-
-
mA
mA
OutputLevels:Reduceddriveoption-x16only
High Current (VOUT =VCCQ -0.763V, minimumVREF, minimumVTT)
LowCurrent(VOUT =0.763V, maximumVREF, maximumVTT)
IOHR
IOLR
-9
9
-
-
mA
mA
I/OReferenceVoltage
I/OTerminationVoltage
VREF
0.49 x VCCQ
VREF - 0.04
0.51 x VCCQ
VREF + 0.04
V
V
VTT
ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14)
(VCC = +2ꢀ5V ±0ꢀ2V; TA = -55°C TO +125°C)
MAX
250MHz
Parameter/Condition
Symbol 266MHz 200MHz Units
OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs
changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22, 48)
OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
IOUT = 0mA; Address and control inputs changing once per clock cycle (22, 48)
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN);
CKE = LOW; (23, 32, 50)
IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control
inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (51)
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN);
CKE = LOW (23, 32, 50)
ICC0
600
825
20
575
775
20
mA
mA
mA
mA
mA
mA
ICC1
ICC2P
ICC2F
ICC3P
ICC3N
200
150
225
200
125
200
ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control
inputs changing once per clock cycle (22)
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 48)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs
changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle (22)
ICC4R
1250
1250
1075
950
mA
mA
ICC4W
AUTO REFRESH CURRENT
tRC = tRC (MIN) (27, 50)
tRC = 7.8125µs (27, 50)
Standard (11)
ICC5
ICC5A
ICC6
1225
30
20
1075
30
20
mA
mA
mA
mA
SELF REFRESH CURRENT: CKE £ 0.2V
OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN);
Address and control inputs change only during Active READ or WRITE commands. (22, 49)
ICC7
2000
1875
11
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(NOTES 1-5, 14-17, 33)
266 MHz CL 2ꢀ5
200 CL 2
250 MHz CL2ꢀ5
200 MHz CL2
200 MHz CL2ꢀ5
150 MHz CL2
Parameter
Symbol
tAC
Min
-0.75
0.45
0.45
7.5
Max
+0.75
0.55
0.55
13
Min
-0.8
0.45
0.45
8
Max
+0.8
0.55
0.55
13
Min
-0.8
0.45
0.45
10
Max
+0.8
0.55
0.55
13
Units
ns
tCK
tCK
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
ns
tCK
ns
tCK
ns
µs
µs
ns
ns
tCK
Access window of DQs from CLK/CLK
CLK high-level width (30)
CLK low-level width (30)
Clock cycle time
tCH
tCL
CL = 2.5 (45, 52)
CL = 2 (45, 52)
tCK (2.5)
tCK (2)
tDH
10
13
10
13
13
15
DQ and DM input hold time relative to DQS (26, 31)
DQ and DM input setup time relative to DQS (26, 31)
DQ and DM input pulse width (for each input) (31)
Access window of DQS from CLK/CLK
DQS input high pulse width
0.5
0.6
0.6
2
0.6
tDS
0.5
0.6
tDIPW
tDQSCK
tDQSH
tDQSL
tDQSQ
tDQSS
tDSS
1.75
-0.75
0.35
0.35
2
+0.75
-0.8
0.35
0.35
+0.8
-0.8
0.35
0.35
+0.8
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26)
Write command to first DQS latching transition
DQS falling edge to CLK rising - setup time
DQS falling edge from CLK rising - hold time
Half clock period (34)
0.5
0.6
0.6
0.75
0.2
1.25
0.75
0.2
1.25
0.75
0.2
1.25
tDSH
tHP
0.2
0.2
0.2
tCH,tCL
tCH,tCL
tCH,tCL
Data-out high-impedance window from CLK/CLK (18, 42)
Data-out low-impedance window from CLK/CLK (18, 43)
Address and control input hold time (fast slew rate) (14)
Address and control input setup time (fast slew rate) (14)
Address and control input hold time (slow slew rate) (14)
Address and control input setup time (slow slew rate) (14)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access (25, 26)
Data hold skew factor
tHZ
+0.75
+0.8
+0.8
tLZ
-0.75
.90
.90
1
-0.8
1.1
1.1
1.1
1.1
16
-0.8
1.1
1.1
1.1
1.1
16
tIHF
tISF
tIHS
tISS
1
tMRD
tQH
15
tHP-tQHS
tHP-tQHS
tHP-tQHS
tQHS
tRAS
tRAP
tRC
0.75
1
1
ACTIVE to PRECHARGE command (35)
ACTIVE to READ with Auto precharge command (46)
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period (50)
ACTIVE to READ or WRITE delay
40
20
65
75
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
40
20
70
80
20
20
0.9
0.4
15
0.25
0
120,000
tRFC
tRCD
tRP
PRECHARGE command period
DQS read preamble (42)
tRPRE
tRPST
tRRD
1.1
0.6
1.1
0.6
1.1
0.6
DQS read postamble
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
tWPRE
tWPRES
tWPST
tWR
DQS write preamble setup time (20, 21)
DQS write postamble (19)
0.4
15
1
0.6
0.4
15
1
0.6
0.4
15
1
0.6
Write recovery time
Internal WRITE to READ command delay
Data valid output window (25)
tWTR
na
tQH - tDQSQ
tQH - tDQSQ
tQH - tDQSQ
REFRESH to REFRESH command interval (23)
Average periodic refresh interval (23)
Terminating voltage delay to VDD
tREFC
tREFI
70.3
7.8
70.3
7.8
70.3
7.8
tVTD
tXSNR
tXSRD
0
0
0
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
75
80
80
200
200
200
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NOTES:
14. Command/Address input slew rate = 0.5V/ns. For 266 MHz with slew rates
1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/
ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns
reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains
constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
15. TheCLK/CLK input reference level (for timing referenced to CLK/CLK) is the point at
which CLK and CLK cross; the input reference level for signals other than CLK/CLK is VREF.
16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the
period before VREF stabilizes, CKE £ 0.3 x VCCQ is recognized as LOW.
17. The output timing reference level, as measured at the timing reference point
indicated in Note 3, is VTT.
18. tHZ and tLZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
19. The maximum limit for this parameter is not a device limit. The device will
operate with a greater value for this parameter, but system performance (bus
turnaround) will degrade accordingly.
20. This is not a device limit. The device will operate with a negative value, but
system performance could be degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies
when no WRITEs were previously in progress on the bus. If a previous WRITE was
in progress, DQS could be HIGH during this time, depending on tDQSS.
22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter. tRAS (MAX) for ICC
measurements is the largest multiple of tCK that meets the maximum absolute
value for tRAS.
23. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs.
However, an AUTO REFRESH command must be asserted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more
than this maximum amount for any given device.
25. The valid data window is derived by achieving other specifications - tHP
(tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly
porportional with the clock duty cycle and a practical data valid window can
be derived. The clock is allowed a maximum duty cycle variation of 45/55.
Functionality is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging between
50/50 and 45/55.
1. All voltages referenced to VSS.
2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage
range specified.
3. Outputs measured with equivalent load:
V
TT
50Ω
Reference
Point
Output
(VOUT
)
30pF
4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CLK/CLK), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VCCQ/2 of the transmitting device and to track
variations in the DC level of the same. Peak-to-peak noise (noncommon
mode) on VREF may not exceed 2 percent of the DC value. Thus, from VCCQ/2,
VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This
measurement is to be taken at the nearest VREF by-pass capacitor.
7. VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. VID is the magnitude of the difference between the input level on CLK and the
input level on CLK.
9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting
device and must track variations in the DC level of the same.
10. ICC is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle time with the outputs open.
11. Enables on-chip refresh and address counters.
12. ICC specifications are tested after the device is properly initialized, and is
averaged at the defined cycle rate.
13. This parameter is not tested but guaranteed by design. tA = 25°C, F = 1 MHz
26. Referenced to each output group: LDQS with DQ0-DQ7; and UDQS with
DQ8-DQ15 of each chip.
27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby).
FIGꢀ A PULL-DOWN CHARACTERISTICS
FIGꢀ B PULL-UP CHARACTERISTICS
0
160
-20
Maximum
140
Minimum
-40
120
-60
-80
Nominal low
Nominal high
100
-100
-120
-140
-160
-180
-200
80
Nominal low
Nominal high
60
Minimum
40
20
0
Maximum
0.0
0.5
1.0
CCQ
1.5
- VOUT (V)
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
V
VOUT (V)
13
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WEDPND16M72S-XBX
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28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the target
AC level, VIL(AC) or VIH(AC).
b) The variation in driver pull-down current within nominal limits of voltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure C.
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target
DC level, VIL(DC) or VIH(DC).
c) The full variation in driver pull-up current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of
the V-I curve of Figure D.
29. The Input capacitance per pin group will not differ by more than this
maximum amount for any given device.
d)The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure D.
30. CLK and CLK input slew rate must be ³ 1V/ns (³2V/ns differentially).
31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If
the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must
be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate
exceeds 4V/ns, functionality is uncertain.
32. VCC must not vary more than 4% if CKE is not active while any bank is active.
33. The clock is allowed up to 150ps of jitter. Each timing parameter is
allowed to vary by the same amount.
34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the
device CLK and CLK inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until
tRAS(MIN) can be satisfied prior to the internal precharge command being issued.
36. Any positive glitch must be less than 1/3 of the clock and not more than
+400mV or 2.9 volts, whichever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is
more positive.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-
down current should be between .71 and 1.4, for device drain-to-source
voltages from 0.1V to 1.0 V, and at the same voltage and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current
should be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 V.
39. The voltage levels used are derived from a minimum VCC level and the
referenced test load. In practice, the voltage levels obtained from a properly
terminated bus will provide significantly different voltage values.
40. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width £ 3ns and
the pulse width can not be greater than 1/3 of the cycle rate.
41. VCC and VCCQ must track each other.
42. This maximum value is derived from the referenced test load. In practice, the
values obtained in a typical terminated design may reflect up to 310ps less for
tHZ(MAX) and the last DVW. tHZ(MAX) will prevail over tDQSCK(MAX) + tRPST(MAX)
condition. tLZ(MIN) will prevail over tDQSCK(MIN) + tRPRE(MAX) condition.
43. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier.
44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC +
0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/
VCCQ are 0 volts, provided a minimum of 42 ohms of series resistance is used
between the VTT supply and the input pin.
37. Normal Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of
the V-I curve of Figure A.
b) The variation in driver pull-down current within nominal limits of voltage
and temperature is expected, but not guaranteed, to lie within the inner
bounding lines of the V-I curve of Figure A.
45. The current part operates below the slowest JEDEC operating frequency of
83 MHz. As such, future die may not reflect this option.
c) The full variation in driver pull-up current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of
the V-I curve of Figure B.
46. Reserved for future use.
47. Reserved for future use.
48. Random addressing changing 50% of data changing at every transfer.
49. Random addressing changing 100% of data changing at every transfer.
50. CKE must be active (high) during the entire time a refresh command is
executed. That is, from the time the AUTO REFRESH command is registered, CKE
must be active at each rising clock edge, until tRFC has been satisfied.
51. ICC2N specifies the DQ, DQS, and DM to be driven to a valid high or low
logic level. ICC2Q is similar to ICC2F except ICC2Q specifies the address and
control inputs to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar,
ICC2F is “worst case.”
d)The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-
down current should be between .71 and 1.4, for device drain-to-source
voltages from 0.1V to 1.0 Volt, and at the same voltage and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should
be unity 10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.
38. Reduced Output Drive Curves:
52. Whenever the operating frequency is altered, not including jitter, the DLL is
required to be reset. This is followed by 200 clock cycles before any READ
command.
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of
the V-I curve of Figure C.
FIGꢀ D PULL-UP CHARACTERISTICS
FIGꢀ C PULL-DOWN CHARACTERISTICS
0
80
Maximum
-10
70
Minimum
-20
60
Nominal high
-30
Nominal low
50
-40
-50
40
Nominal low
30
Minimum
Nominal high
-60
20
-70
10
0
Maximum
-80
0.0
0.5
1.0
CCQ
1.5
- VOUT (V)
2.0
2.5
0.0
0.5
1.0
1.5
2.0
2.5
V
VOUT (V)
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
14
WEDPND16M72S-XBX
White Electronic Designs
PACKAGE DIMENSION: 219 PLASITC BALL GRID ARRAY (PBGA)
BOTTOM VIEW
32.32 (1.272) MAX
1
2
3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
1.27/2
19.05 (0.750)
K
J
25.25 (0.994)
MAX
H
G
F
NOM
E
D
C
B
A
0.60 (0.024)
0.10 (0.004)
1.27/2
1.27 (0.050)
BSC
219 X ∅ 0.835
2.20 (0.087)
MAX
19.05 (0.750) NOM
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
WED P ND 16M 72 S - XXX B X
WHITE ELECTRONIC DESIGNS CORPꢀ
PLASTIC
DDR SDRAM
CONFIGURATION, 16M x 72
2ꢀ5V Power Supply
FREQUENCY (MHz)
200=200MHz
250=250MHz
266=266MHz
PACKAGE:
B=219PlasticBallGridArray(PBGA)
DEVICE GRADE:
M = Military
-55°Cto+125°C
-40°Cto+85°C
0°Cto+70°C
I
= Industrial
C
= Commercial
15
White Electronic Designs Corporation (602) 437-1520 wwwꢀwhiteedcꢀcom
WEDPND16M72S-XBX
White Electronic Designs
Document Title
16M x 72 DDR SDRAM Multi-Chip Package
Revision History
Rev #
Rev 0
Rev 1
History
Release Date
April 2002
Status
Initial Release
Advanced
Advanced
Changes (Pg" 1, 10)
September 2002
1"1
Add Currents to data sheet in place of TBD
Rev 2
Rev 3
Changes (Pg" 1, 15)
November 2002
December 2002
Preliminary
Preliminary
1"1
Change product status from Advanced to Preliminary
Changes (Pg" 1, 10, 14, 15, 16)
1"1
1"2
1"3
1"4
1"5
1"6
1"7
1"8
1"9
Change ICCI to 825 mA @ 250/266 MHz
Change ICC1 to 775 mA @ 200 MHz
Change ICC4R to 1250 mA @ 250/266 MHz
Change ICC4R to 1075 mA @ 200 MHz
Change ICC4W to 1250 mA @ 250/266 MHz
Change ICC4W to 1075 mA @ 200 MHz
Change ICC6A to ICC6
Change ICC8 to ICC7
Change ICC7 to 2000 mA @ 250/266 MHz
1"10 Change ICC7 to 1875 mA @ 200 MHz
1"11 Add Thermal Resistance Table
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
16
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