WF256K16-70CC5A [WEDC]
Flash Module, 256KX16, 70ns, CDIP40, 0.600 INCH, SINGLE-CAVITY, SIDE BRAZED, CERAMIC, DIP-40;
| 型号： | WF256K16-70CC5A |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Flash Module, 256KX16, 70ns, CDIP40, 0.600 INCH, SINGLE-CAVITY, SIDE BRAZED, CERAMIC, DIP-40 CD |
| 文件： | 总11页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WF128K16-XCX5
WF256K16-XCX5
PRELIMINARY*
White Electronic Designs
5V FLASH MODULE
FEATURES
ꢀ
ꢀ
ꢀ
ꢀ
Access Times of 50, 60, 70, 90, 120 and 150ns
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
5 Volt Programming; 5V 10ꢀ Supply
40 pin Ceramic DIP (Package 303)
Organized as 128Kx16 and 256Kx16
Sector Architecture
Low Power CMOS
Embedded Erase and Program Algorithms
TTL Compatible Inputs and CMOS Outputs
• 8 equal size sectors of 16KBytes each per chip
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
• Any combination of sectors can be concurrently
erased.
ꢀ
Page Program Operation and Internal Program
Control Time
• Also supports full chip erase
* This product is under development, is not qualified or characterized and is subject to
change without notice.
ꢀ
100,000 Erase/Program Cycles Minimum (0°C to
70°C)
Note: Programming information available upon request.
ꢀ
ꢀ
Data Retention, 10 Years at 125°C
Commercial, Industrial and Military Temperature
Ranges
FIGURE 1 – PIN CONFIGURATION AND BLOCK DIAGRAM
TOP VIEW
PIN DESCRIPTION
V
CC
CS2#*/NC
CS#1
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
1
40
A0-16
Address Inputs
WE#
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
2
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
3
4
5
6
7
8
9
I/O0-15 Data Input/Output
CS1-2
OE
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
WE
I/O8
GND
I/O7
10
11
12
13
14
15
16
17
18
19
20
VCC
GND
I/O6
I/O5
* CS2# for 256Kx16
and NC for 128Kx16
I/O4
I/O3
I/O2
I/O1
I/O0
OE#
BLOCK DIAGRAM
A4
A3
A2
A1
FOR WF256K16-XCX5
I/O0-7
I/O8-15
A0
WE#
OE#
A
0-16
BLOCK DIAGRAM
FOR WF128K16-XCX5
128K x 8
128K x 8
128K x 8
128K x 8
I/O0-7
I/O8-15
WE#
OE#
A0-16
(1)
(1)
CS
CS
1
2
#
#
128K x 8
128K x 8
NOTE: 1. CS1# and CS2# are used to select the lower and upper
128Kx16 of the device. CS1# and CS2# must not be
enabled at the same time.
CS1#
October 1998
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS (1)
Parameter
CAPACITANCE
TA = 25°C
Symbol
Unit
°C
V
Test
Conditions
Max Unit
50 pF
50 pF
30 pF
Operating Temperature
-55 to +125
-2.0 to +7.0
-2.0 to +7.0
-65 to +150
+300
OE capacitance
WE capacitance
CS capacitance
I/O0-7 capacitance
Address capacitance
COE
CWE
CCS
CI/O
CAD
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
VIN = 0 V, f = 1.0 MHz
Supply Voltage Range (VCC
)
Signal voltage range (any pin except A9) (2)
Storage Temperature Range
V
°C
°C
VI/O = 0 V, f = 1.0 MHz 30 pF
VIN = 0 V, f = 1.0 MHz 50 pF
Lead Temperature (soldering, 10 seconds)
Data Retention Mil Temp
10 years
This parameter is guaranteed by design but not tested.
Endurance (write/erase cycles) Mil Temp
A9 Voltage for sector protect (VID) (3)
NOTES:
10,000 cycles min.
-2.0 to +14.0
V
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC
VIH
Min
4.5
Max
5.5
Unit
V
1. Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
2. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs
may overshoot VSS to -2.0 V for periods of up to 20ns. Maximum DC voltage
on output and I/O pins is VCC + 0.5V. During voltage transitions, outputs may
overshoot to Vcc + 2.0 V for periods of up to 20ns.
3. Minimum DC input voltage on A9 pin is -0.5V. During voltage transitions, A9 may
overshoot Vss to -2V for periods of up to 20ns. Maximum DC input voltage on A9 is
+13.5V which may overshoot to 14.0 V for periods up to 20ns.
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
A9 Voltage for Sector Protect
2.0
VCC + 0.3
+0.8
V
VIL
-0.5
-55
-40
11.5
V
TA
+125
+85
°C
°C
V
TA
VID
12.5
DC CHARACTERISTICS — CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
128K x 16
256K x 16
Parameter
Symbol Conditions
Unit
Min
Max
10
Min
Max
10
Input Leakage Current
Output Leakage Current
ILI
VCC = 5.5, VIN = GND to VCC
mA
mA
mA
mA
ILO
VCC = 5.5, VIN = GND to VCC
CS# = VIL, OE# = VIH
10
10
80
VCC Active Current for Read (1)
ICC1
ICC2
ICC3
VOL
VOH1
VOH2
VLKO
70
VCC Active Current for Program or Erase (2)
VCC Standby Current
Output Low Voltage
CS# = VIL, OE# = VIH
100
6
110
8 mA
0.45
VCC = 5.5, CS# = VIH, f = 5MHz
IOL = 12.0 mA, VCC = 4.5
IOH = -2.5 mA, VCC = 4.5
IOH = -100 mA, VCC = 4.5
0.45
V
V
V
V
Output High Voltage
0.85xVcc
VCC -0.4
3.2
0.85xVcc
VCC -0.4
3.2
Output High Voltage
Low VCC Lock Out Voltage
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
The frequency component typically is less than 2 mA/MHz, with OE# at VIH
.
2.
ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
October 1998
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
WRITE
PRINCIPLES OF OPERATION
Device erasure and programming are accomplished via
the command register. The contents of the register serve
as input to the internal state machine. The state machine
outputs dictate the function of the device.
The following principles of operation of the WF128K16-
XCX5 and WF256K16-XCX5 are applicable to each
128K x 8 memory chip inside the MCM. Programming
of the device is accomplished by executing the program
command sequence. The program algorithm, which is an
internal algorithm, automatically times the program pulse
widths and verifies proper cell margin. Sectors can be
programmed and verified in less than 0.3 seconds. Erase is
accomplished by executing the erase command sequence.
The erase algorithm, which is internal, automatically
preprograms the array if it is not already programmed
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin. The entire memory is
typically erased and verified in three seconds (including
pre-programming).
The command register itself does not occupy an
addressable memory location. The register is a latch
used to store the commands, along with address and
data information needed to execute the command. The
command register is written by bringing Write-Enable to
a logic-low level (VIL), while Chip-Select is low and OE#
is at VIH. Addresses are latched on the falling edge of the
Write-Enable while data is latched on the rising edge of
the WE# pulse. Standard microprocessor write timings
are used. Refer to AC Program characteristics, Figures
4 and 7.
BUS OPERATIONS
READ
The device has two control functions, both of which must be
logically active, to obtain data at the outputs. Chip-Select
(CS#) is the power control and should be used for device
selection. Output-Enable (OE#) is the output control and
should be used to gate data to the output pins. Figure 3
illustrates read timing waveforms.
OUTPUT DISABLE
With Output-Enable at a logic-high level (VIH), output from
the device is disabled. Output pins are placed in a high
impedance state.
STANDBY MODE
The device has two standby modes, a CMOS standby
mode (CS# input held at VCC + 0.5V), and a TTL standby
mode (CS# is held VIH). In the standby mode the outputs
are in a high impedance state, independent of the OE#
input.
TABLE 1 – BUS OPERATIONS
If the device is deselected during erasure or programming,
the device will draw active current until the operation is
completed.
Operation
CS# OE# WE# A0 A1 A9
I/O
Read
L
H
L
L
L
L
L
X
H
X
H
L
A0 A1 A9 DOUT
Standby
X
X
X
X
X
X
HIGH Z
HIGH Z
DIN
Output Disable
Write
H
H
A0 A1 A9
Enable Sector Protect
Verify Sector Protect
VID
L
L
X
L
X
H
VID
X
H
VID Code
October 1998
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, WE# CONTROLLED
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
-50
-60
-70
-90
-120
-150
Parameter
Symbol
tAVAV
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Write Cycle Time
tWC
tCS
tWP
tAS
50
0
60
0
70
0
90
0
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
tELWL
tWLWH
tAVWL
25
0
30
0
35
0
45
0
50
0
50
0
Data Setup Time
tDVWH
tWHDX
tWLAX
tDS
25
0
30
0
30
0
45
0
50
0
50
0
Data Hold Time
tDH
tAH
tCH
tWPH
Address Hold Time
40
0
45
0
45
0
45
0
50
0
50
0
Chip Select Hold Time
tWHEH
tWHWL
tWHWH1
tWHWH2
tGHWL
Write Enable Pulse Width High
Duration of Byte Programming Operation (min)
Chip and Sector Erase Time
Read Recovery Time Before Write
VCC Setup Time
20
14
20
14
20
14
20
14
20
14
20
14
2.2 60 2.2 60 2.2 60 2.2 60 2.2 60 2.2 60 sec
0
0
0
0
0
0
ns
tVCS
50
50
50
50
50
50
µs
12.5 sec
ns
Chip Programming Time
Output Enable Setup Time
Output Enable Hold Time (1)
1. For Toggle and Data# Polling.
12.5
12.5
12.5
12.5
12.5
tOES
tOEH
0
0
0
0
0
0
10
10
10
10
10
10
ns
AC CHARACTERISTICS – READ ONLY OPERATIONS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
-50
-60
-70
-90
-120
-150
Parameter
Symbol
tAVAV
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Read Cycle Time
tRC
tACC
tCE
tOE
tDF
50
60
70
90
120
150
ns
150 ns
150 ns
55 ns
35 ns
35 ns
ns
Address Access Time
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
50
50
25
20
20
60
60
30
20
20
70
70
35
20
20
90
90
40
25
25
120
120
50
Chip Select Access Time
OE# to Output Valid
Chip Select to Output High Z (1)
OE# High to Output High Z (1)
30
tDF
30
Output Hold from Address, CS# or OE# Change,
whichever is first
tOH
0
0
0
0
0
0
1. Guaranteed by design, not tested.
October 1998
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, CS CONTROLLED
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
-50
-60
-70
-90
-120
-150
Parameter
Symbol
tAVAV
tWLEL
tELEH
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Write Cycle Time
tWC
tWS
tCP
50
0
60
0
70
0
90
0
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
WE Setup Time
CS Pulse Width
25
0
30
0
35
0
45
0
50
0
50
0
Address Setup Time
Data Setup Time
tAVEL
tAS
tDVEH
tEHDX
tELAX
tDS
25
0
30
0
30
0
45
0
50
0
50
0
Data Hold Time
tDH
tAH
tWH
tCPH
Address Hold Time
40
0
45
0
45
0
45
0
50
0
50
0
WE Hold from WE High
CS Pulse Width High
Duration of Programming Operation
Duration of Erase Operation
Read Recovery before Write
Chip Programming Time
tEHWH
tEHEL
20
14
20
14
20
14
20
14
20
14
20
14
tWHWH1
tWHWH2
tGHEL
2.2 60 2.2 60 2.2 60 2.2 60 2.2 60 2.2 60 sec
0
0
0
0
0
0
ns
12.5
12.5
12.5
12.5
12.5
12.5 sec
FIGURE 2 – AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
IOL
Input Pulse Levels
VIL = 0, VIH = 3.0
V
ns
V
Current Source
Input Rise and Fall
5
Input and Output Reference Level
Output Timing Reference Level
NOTES:
Z is programmable from -2V to +7V.
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
1.5
1.5
D.U.T.
VZ
≈ 1.5V
V
(Bipolar Supply)
Ceff = 50 pf
V
I
IOH
V
I
.
Current Source
October 1998
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
FIGURE 3 – AC WAVEFORMS FOR READ OPERATIONS
October 1998
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
FIGURE 4 – AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, WE# CONTROLLED
NOTES:
1. PA is the address of the memory location
to be programmed.
2. PD is the data to be programmed.
3. D7# is the output of the complement of
the data written (for each chip).
4. DOUT is the output of the data written to
the device.
5. Figure indicates last two bus cycles of
four bus cycle sequence.
October 1998
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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
FIGURE 5 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
NOTES:
1. SA is the sector address
for Sector Erase.
October 1998
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
FIGURE 6 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM OPERATIONS
October 1998
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WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
FIGURE 7 – AC WAVEFORMS FOR WRITE/ERASE/PROGRAM OPERATIONS, CS# CONTROLLED
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device (for each chip).
4.
DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
October 1998
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF128K16-XCX5
WF256K16-XCX5
White Electronic Designs
PACKAGE 303 – 40 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
51.3 (2.020) 0.5 (0.020)
15.1 (0.595)
0.25 (0.010)
7.2 (0.285)
0.8 (0.030)
PIN 1 IDENTIFIER
3.2 (0.125) MIN
0.25 (0.010)
0.05 (0.002)
0.94 (0.037)
0.25 (0.010)
15.25 (0.600)
0.25 (0.010)
2.5 (0.100)
TYP
1.27 (0.050)
0.1 (0.005)
0.5 (0.018)
0.05 (0.002)
ORDERING INFORMATION
W F XXXK16 - XXX C X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5 = 5V
DEVICE GRADE:
Q = Compliant
M = Military Screened -55°C to 125°C
I = Industrial -40°C to +85°C
C = Commercial 0 to +70°C
PACKAGE TYPE:
C = 40 Pin Ceramic 0.600” DIP (Package 303)
ACCESS TIME (ns)
ORGANIZATION, 128K x 16 or 256K x 16
Flash PROM
WHITE MICROELECTRONICS
October 1998
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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