WF2M32-090G2UQ5 [WEDC]
2Mx32 5V Flash Module; 2Mx32 5V闪存模块
| 型号： | WF2M32-090G2UQ5 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 2Mx32 5V Flash Module |
| 文件： | 总15页 (文件大小：750K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WF2M32-XXX5
White Electronic Designs
2Mx32 5V Flash Module
FEATURES
ꢀ
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Access Time of 90, 120, 150ns
ꢀ
ꢀ
Organized as 2Mx32
Commercial, Industrial, and Military
Temperature Ranges
5 Volt Read and Write. 5V 10ꢀ Supply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
RESET# pin resets internal state machine to the
read mode.
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation, Separate Power and
Ground Planes to improve noise immunity
Packaging:
• 66 pin, PGA Type, 1.185" square, Hermetic
Ceramic HIP (Package 401).
ꢀ
ꢀ
ꢀ
• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880")
square (Package 510) 3.56mm (0.140") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (FIGURE 3)
ꢀ
ꢀ
ꢀ
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Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8
chip
• Any combination of sectors can be erased. Also
supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
* This product is subject to change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
FIGURE 1 – PIN CONFIGURATION FOR WF2M32-XHX5
Top View
Pin Description
I/O0-31
A0-20
WE1-4#
CS1-4#
OE#
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
1
12
23
34
45
56
I/O8
I/O9
I/O10
A14
A16
A11
A0
WE2#
CS2#
GND
I/O11
A10
I/O15
I/O24
I/O25
I/O26
A7
VCC
CS4#
WE4#
I/O27
A4
I/O31
I/O30
I/O29
I/O28
A1
I/O14
I/O13
I/O12
OE#
A17
VCC
GND
A12
Block Diagram
WE1# CS1#
WE2# CS2#
WE3# CS3#
WE4# CS4#
2M x 8
A9
A20
A5
A2
OE#
A0-20
A15
WE1#
I/O7
A13
A6
A3
2M x 8
2M x 8
2M x 8
A18
I/O0
I/O1
I/O2
VCC
CS1#
A19
A8
WE3#
CS3#
GND
I/O19
I/O23
I/O22
I/O21
I/O20
I/O6
I/O16
I/O17
I/O18
8
8
8
8
I/O5
I/O16-23
I/O24-31
I/O0-7
I/O8-15
I/O3
I/O4
RESET# internally tied to VCC in the HIP package for this pin con-
figuration. See Alternate Pin Configuration with RESET# tied to pin
12 for system control of reset (FIGURE 10, page 11).
11
22
33
44
55
66
October 2004
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF2M32-XXX5
White Electronic Designs
FIGURE 2 – PIN CONFIGURATION FOR WF2M32-XG2UX5
Top View
Pin Description
I/O0-31
A0-20
WE1-4#
CS1-4#
OE#
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VCC
GND
RESET# Reset
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
Block Diagram
WE1# CS1#
WE2# CS2#
WE3# CS3#
WE4# CS4#
RESET#
OE#
A
0-20
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2M x 8
2M x 8
2M x 8
2M x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
The WEDC 68 lead G2U CQFP fills the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead
inspection advantage of the CQFP form.
0.940"
October 2004
Rev. 5
2
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WF2M32-XXX5
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
CAPACITANCE
TA = +25°C, f = 1.0MHz
Parameter
Symbol
VT
Ratings
-2.0 to +7.0
8
Unit
V
Parameter
OE# capacitance
WE1-4# capacitance
HIP (PGA)
HIP (Alternate pinout)
CQFP G4T
CQFP G2U
Symbol
COE
Max
Unit
Voltage on Any Pin Relative to VSS
Power Dissipation
50
pF
PT
W
Storage Temperature
Short Circuit Output Current
Tstg
-65 to +125
100
°C
CWE
CWE
CWE
CWE
CWE
CCS
CI/O
CAD
20
50
50
20
50
20
20
50
pF
pF
pF
pF
pF
pF
pF
pF
IOS
mA
cycles
Endurance – Write/Erase Cycles
(Extended Temp)
100,000 min
G2U (Alternate pinout)
CS1-4# capacitance
Data I/O capacitance
Address input capacitance
Data Retention
20
years
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Symbol Min Typ
Max
5.5
Unit
V
Supply Voltage
VCC
VSS
VIH
VIL
TA
4.5
0
5.0
Ground
0
-
0
V
Input High Voltage
Input Low Voltage
Operating Temperature (Mil.)
Operating Temperature (Ind.)
2.0
-0.5
-55
-40
VCC + 0.5
+0.8
+125
+85
V
-
V
-
°C
°C
TA
-
DC CHARACTERISTICS – CMOS COMPATIBLE
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol Conditions
Min
Max
10
10
160
240
8.0
Unit
µA
µA
mA
mA
mA
V
Input Leakage Current
Output Leakage Current
VCC Active Current for Read (1)
ILI
VCC = 5.5, VIN = GND to VCC
VCC = 5.5, VIN = GND to VCC
CS# = VIL, OE# = VIH, f = 5MHz
CS# = VIL, OE# = VIH
ILOx32
ICC1
ICC2
ICC3
VOL
VCC Active Current for Program or Erase (2)
CC Standby Current
V
VCC = 5.5, CS# = VIH, f = 5MHz, RESET# = VCC 0.3V
IOL = 12.0 mA, VCC = 4.5
Output Low Voltage
0.45
Output High Voltage
Low VCC Lock-Out Voltage
VOH
VLKO
IOH = -2.5 mA, VCC = 4.5
0.85xVCC
3.2
V
V
4.2
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency
dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE# at VIH
.
2.
ICC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions VIL = 0.3V, VIH = VCC - 0.3V
October 2004
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF2M32-XXX5
White Electronic Designs
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-90
-120
-150
Unit
Min
90
0
45
0
Max
Min
120
0
50
0
Max
Min
150
0
50
0
Max
Write Cycle Time
tAVAV
tWC
tCS
tWP
tAS
ns
ns
ns
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
tELWL
tWLWH
tAVWL
ns
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWHWH2
tGHWL
tVCS
tDS
tDH
tAH
45
0
45
20
50
0
50
20
50
0
50
20
ns
ns
ns
ns
µs
sec
µs
µs
sec
sec
ns
tWPH
300
15
300
15
300
15
Read Recovery Time before Write
0
50
0
50
0
50
VCC Setup Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
RESET# Pulse Width (5)
44
256
44
256
44
256
tOEH
tRP
10
500
10
500
10
500
ns
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
5. RESET# internally tied to VCC for the default pin configuration in the HIP package.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-90
-120
-150
Unit
Min
90
Max
Min
120
Max
Min
150
Max
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Addresses, CS# or OE#
Change, whichever is First
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tRC
tACC
tCE
tOE
tDF
ns
ns
ns
ns
ns
ns
ns
90
90
40
20
20
120
120
50
30
30
150
150
55
35
35
tDF
tOH
0
0
0
RST Low to Read Mode (1,2)
tReady
20
20
20
µs
NOTES:
1. Guaranteed by design, not tested.
2. RESET# internally tied to VCC for the default pin configuration in the HIP package.
October 2004
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF2M32-XXX5
White Electronic Designs
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-90
-120
-150
Unit
Min
90
0
45
0
Max
Min
120
0
50
0
Max
Min
150
0
50
0
Max
Write Cycle Time
tAVAV
tWLEL
tELEH
tWC
tWS
tCP
ns
ns
ns
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
tAVEL
tAS
ns
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
tDVEH
tEHDX
tELAX
tDS
tDH
tAH
45
0
45
20
50
0
50
20
50
0
50
20
ns
ns
ns
ns
µs
sec
µs
sec
sec
ns
tEHEL
tCPH
tWHWH1
tWHWH2
tGHEL
300
15
300
15
300
15
0
0
0
44
256
44
256
44
256
Output Enable Hold Time (4)
tOEH
10
10
10
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
FIGURE 3 – AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
V
I
OL
Input Pulse Levels
Input Rise and Fall
VIL = 0, VIH = 3.0
Current Source
5
ns
V
Input and Output Reference Level
1.5
1.5
Output Timing Reference Level
V
V
Z
≈
1.5V
D.U.T.
Notes:
(Bipolar Supply)
C
eff = 50 pf
V
Z is programmable from -2V to +7V.
I
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ý.
VZ is typically the midpoint of VOH and VOL
I
.
IOH
OL & IOH are adjusted to simulate a typical resistive load circuit.
Current Source
ATE tester includes jig capacitance.
FIGURE 4 – RESET TIMING DIAGRAM
RESET#
tRP
tReady
October 2004
Rev. 5
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF2M32-XXX5
White Electronic Designs
FIGURE 5 – AC WAVEFORMS FOR READ OPERATIONS
October 2004
Rev. 5
6
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WF2M32-XXX5
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FIGURE 6 – WRITE/ERASE/PROGRAM OPERATION, WE# CONTROLLED
NOTES:
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to each chip.
October 2004
Rev. 5
7
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WF2M32-XXX5
White Electronic Designs
FIGURE 7 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS
NOTE:
1. SA is the sector address for Sector Erase.
October 2004
Rev. 5
8
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FIGURE 8 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM
OPERATIONS
October 2004
Rev. 5
9
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WF2M32-XXX5
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FIGURE 9 – ALTERNATE CS# CONTROLLED PROGRAMMING OPERATION TIMINGS
Notes:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to each chip.
4.
DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
October 2004
Rev. 5
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF2M32-XXX5
White Electronic Designs
FIGURE 10 – ALTERNATE PIN CONFIGURATION FOR WF2M32I-XHX5
TOP VIEW
PIN DESCRIPTION
1
12
23
34
45
56
I/O0-31
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
A0-20
WE#
CS1-4
OE#
VCC
I/O8
I/O9
I/O10
A14
A16
A11
A0
RESET#
CS2#
GND
I/O11
A10
I/O15
I/O24
I/O25
I/O26
A7
VCC
CS4#
NC
I/O31
I/O30
I/O29
I/O28
A1
I/O14
I/O13
I/O12
OE#
A17
#
I/O27
A4
GND
RESET#
Reset
A12
A9
NC
A5
A2
BLOCK DIAGRAM
A15
WE#
I/O7
I/O6
I/O5
I/O4
A13
A6
A3
CS1#
CS2#
CS3#
CS4#
RESET#
WE#
OE#
A0-20
A18
I/O0
I/O1
I/O2
VCC
A8
A20
I/O23
I/O22
I/O21
I/O20
CS1#
A19
I/O16
I/O17
I/O18
CS3#
GND
I/O19
2M x 8
2M x 8
2M x 8
2M x 8
8
8
8
8
I/O3
I/O16-23
I/O24-31
I/O0-7
I/O8-15
11
22
33
44
55
66
FIGURE 11 – ALTERNATE PIN CONFIGURATION FOR WF2M32U-XG2UX5
TOP VIEW
PIN DESCRIPTION
I/O0-31
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Select
Output Enable
Power Supply
Ground
A0-20
WE#
CS#
OE#
VCC
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
0.940"
GND
The WEDC 68 lead G2U CQFP fills the
same fit and function as the JEDEC 68 lead
CQFJ or 68 PLCC. But the G2U has the
TCE and lead inspection advantage of the
CQFP form.
RESET# Reset
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
BLOCK DIAGRAM
RESET#
CS#
WE#
OE#
0-20
A
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2M x 8
2M x 8
2M x 8
2M x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
October 2004
Rev. 5
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF2M32-XXX5
White Electronic Designs
FIGURE 12 – PIN CONFIGURATION FOR WF2M32I-XG2UX5
TOP VIEW
PIN DESCRIPTION
I/O0-31
A0-20
WE#
Data Inputs/Outputs
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
CS1-4
OE#
#
VCC
GND
RESET#
Reset
I/O9
BLOCK DIAGRAM
CS1#
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
CS2#
CS3#
CS4#
RESET#
WE#
OE#
A0-20
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2M x 8
2M x 8
2M x 8
2M x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
The WEDC 68 lead G2U CQFP fills the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead
inspection advantage of the CQFP form.
0.940"
October 2004
Rev. 5
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF2M32-XXX5
White Electronic Designs
PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)
30.1 (1.185) 0.38 (0.015) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
6.22 (0.245)
MAX
3.81 (0.150)
0.1 (0.005)
1.27 (0.050) 0.1 (0.005)
0.76 (0.030) 0.1 (0.005)
2.54 (0.100)
TYP
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
0.46 (0.018) 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
October 2004
Rev. 5
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WF2M32-XXX5
White Electronic Designs
PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
The WEDC 68 lead G2U CQFP fills the same
fit and function as the JEDEC 68 lead CQFJ or
68 PLCC. But the G2U has the TCE and lead
inspection advantage of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
October 2004
Rev. 5
14
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WF2M32-XXX5
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ORDERING INFORMATION
W F 2M32 X - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMING VOLTAGE
5 = 5 V
DEVICE GRADE:
Q
M
I
=
=
=
=
Compliant
Military
Industrial
Commercial
-55°C to +125°C
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C
PACKAGE TYPE:
= Ceramic Hex In line Package, HIP (Package 401)
H
G2U = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 510)
ACCESS TIME (ns)
IMPROVEMENT MARK
• For HIP Package
Blank = 4CS# and 4WE#
I = 4CS# and 1WE#, RESET#
• For G2U Package
Blank = 4CS# and 4WE#
U = 1CS# and 1WE#
I = 4CS# and 1WE#, RESET#
ORGANIZATION, 2M x 32
User configurable as 4M x 16 or 8M x 8
(Except WF2M32U-XG2UX which is 32 bit wide only.)
Flash
WHITE ELECTRONIC DESIGNS CORP.
October 2004
Rev. 5
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
WF2M32-090G2UQ5A
2Mx32 5V Flash ModuleWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
WEDC
WF2M32-090HC5
2Mx32 5V Flash ModuleWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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WF2M32-090HC5A
2Mx32 5V Flash ModuleWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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WEDC
WF2M32-090HI5
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WEDC
WF2M32-090HI5A
2Mx32 5V Flash ModuleWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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WEDC
WF2M32-090HM5
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WEDC
WF2M32-090HM5A
2Mx32 5V Flash ModuleWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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WEDC
WF2M32-090HQ5
2Mx32 5V Flash ModuleWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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WEDC
WF2M32-090HQ5A
2Mx32 5V Flash ModuleWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Flash Module, 8MX8, 100ns,Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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x32 Flash EEPROM ModuleWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Flash Module, 8MX8, 100ns, CPGA66, 1.385 X 1.385 INCH, HERMETIC SEALED, CERAMIC, HIP-66Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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