WF2M32U-90G2UE5A [WEDC]
Flash Module, 2MX32, 90ns, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMATIC SEALED, CERAMIC, QFP-68;
| 型号： | WF2M32U-90G2UE5A |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Flash Module, 2MX32, 90ns, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMATIC SEALED, CERAMIC, QFP-68 内存集成电路 |
| 文件： | 总14页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WF2M32-XXX5
White Electronic Designs
PRELIMINARY*
2Mx32 5V Flash Module
FEATURES
■ Commercial, Industrial, and Extended Tempera-
■ Access Time of 90, 120, 150ns
ture Ranges
■ Packaging:
■ 5 Volt Read and Write( 5V ± 10% Supply(
■ Low Power CMOS
66 pin, PGA Type, 1(185" square, Hermetic
Ceramic HIP ꢀPackage 401)(
■ Data Polling and Toggle Bit feature for detection
68 lead, Hermetic CQFP ꢀG2U), 22(4mm
ꢀ0(880") square ꢀPackage 510) 3(56mm
ꢀ0(140") height( Designed to fit JEDEC 68 lead
0(990" CQFJ footprint ꢀFig( 3)
of program or erase cycle completion(
■ Supports reading or programming data to a
sector not being erased(
■ Sector Architecture
■ RESET pin resets internal state machine to the
read mode(
32 equal size sectors of 64KBytes per each
2Mx8 chip
■ Built in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation, Separate Power
and Ground Planes to improve noise immunity
Any combination of sectors can be erased(
Also supports full chip erase(
* This data sheet describes a product under development, not fully characterized,
and is subject to change without noticeꢀ
Note:
For programming information refer to Flash Programming 16M5 Application
Note#
■ Minimum 100,000 Write/Erase Cycles Minimum
■ Organized as 2Mx32
FIGꢀ 1 PIN CONFIGURATION FOR WF2M32-XHX5
PINDESCRIPTION
TOP VIEW
I/O0-31 Data Inputs/Outputs
A0-20
WE1-4
CS1-4
OE
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
1
12
23
34
45
56
I/O
I/O
8
9
WE
CS
2
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
2
CS
4
4
VCC
GND
I/O10
GND
I/O11
WE
A
A
A
A
A
14
16
11
0
A
7
I/O27
A
A
A
V
10
A12
A20
A13
A
A
4
5
6
3
3
A1
A2
A3
BLOCKDIAGRAM
WE3 CS3
WE4 CS4
WE1 CS1
WE2 CS2
9
A17
OE
A0-20
15
CC
WE
1
A
18
I/O
I/O
I/O
I/O
7
A
8
WE
CS
I/O23
I/O22
I/O21
I/O20
2M x 8
2M x 8
2M x 8
2M x 8
I/O
I/O
I/O
0
1
2
CS1
6
I/O16
I/O17
I/O18
8
8
8
8
A19
5
4
GND
I/O19
I/O
3
I/O16-23
I/O24-31
I/O0-7
I/O8-15
11
22
33
44
55
66
RESET internally tied to Vcc in the HIP package for this pin
configurationꢀ See Alternate Pin Configuration with RESET tied
to pin 12 for system control of reset (Figꢀ 10, page 11)ꢀ
December2003 Rev#4
1
WhiteElectronicDesignsCorporation(602)437-1520
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FIGꢀ 2 PIN CONFIGURATION FOR WF2M32-XG2UX5
TOP VIEW
PINDESCRIPTION
I/O0-31
A0-20
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
WE1-4
CS1-4
OE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VCC
GND
RESET
Reset
GND
I/O
I/O
8
9
BLOCKDIAGRAM
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
WE
WE
WE
4 CS4
2 CS 2
WE3
1 CS 1
CS3
RESET
OE
A
0-20
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2M x 8
2M x 8
2M x 8
2M x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
The WEDC 68 lead G2U CQFP fills the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCCꢀ But the G2U has the TCE and lead
inspection advantage of the CQFP formꢀ
0.940"
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WF2M32-XXX5
White Electronic Designs
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE
ꢀTA = +25°C, F = 1(0MHz)
Parameter
Symbol
VT
Ratings
-2#0to+7#0
8
Unit
V
Parameter
Symbol
Max
Unit
VoltageonAnyPinRelativetoVSS
PowerDissipation
OEcapacitance
WE1-4capacitance
HIP (PGA)
COE
50
pF
PT
W
StorageTemperature
ShortCircuitOutputCurrent
Tstg
IOS
-65to+125
°C
CWE
CWE
CWE
CWE
CWE
CCS
CI/O
CAD
20
50
50
20
50
20
20
50
pF
pF
pF
pF
pF
pF
pF
pF
100
mA
HIP(Alternatepinout)
Endurance-Write/EraseCycles
(ExtendedTemp)
100,000min
cycles
CQFP G4T
CQFP G2U
DataRetention(ExtendedTemp)
20
years
G2U(Alternatepinout)
CS1-4capacitance
DataI/Ocapacitance
RECOMMENDEDDCOPERATINGCONDITIONS
Addressinputcapacitance
Parameter
Symbol
VCC
VSS
VIH
VIL
Min
4#5
0
Typ
Max
Unit
Thisparameterisguaranteedbydesignbutnottested#
SupplyVoltage
5#0
0
-
5#5
V
Ground
0
V
InputHighVoltage
InputLowVoltage
OperatingTemperature(Ext#)(4)
OperatingTemperature(Ind#)
2#0
-0#5
-55
-40
VCC + 0#5
+0#8
+100
+85
V
-
V
TA
-
°C
°C
TA
-
DCCHARACTERISTICS-CMOSCOMPATIBLE
ꢀVCC = 5(0V, VSS = 0V, TA = -55°C to +125°C) ꢀNote 4)
Parameter
Symbol
ILI
Conditions
VCC = 5#5, VIN = GND to VCC
Min
Max
10
Unit
InputLeakageCurrent
µA
µA
mA
mA
mA
V
OutputLeakageCurrent
VCC ActiveCurrentforRead(1)
VCC Active Current for Program or Erase (2)
VCCStandbyCurrent
ILOx32
ICC1
VCC = 5#5, VIN = GND to VCC
CS = VIL, OE = VIH, f = 5MHz
CS = VIL, OE = VIH
10
160
240
8#0
ICC2
ICC3
VCC = 5#5, CS = VIH, f = 5MHz, RESET = VCC ± 0#3V
IOL = 12#0 mA, VCC = 4#5
OutputLowVoltage
VOL
0#45
OutputHighVoltage
VOH
VLKO
IOH = -2#5 mA, VCC = 4#5
0#85xVCC
3#2
V
LowVCC Lock-OutVoltage
4#2
V
NOTES:
1ꢀ The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5MHz)ꢀ The frequency component typically is less than 2mA/
MHz, with OE at VIH
ꢀ
2ꢀ ICC active while Embedded Algorithm (program or erase) is in progressꢀ
3ꢀ DC test conditions VIL = 0ꢀ3V, VIH = VCC - 0ꢀ3V
4ꢀ Extended temperature devices are fully operational from -55°C to +100°Cꢀ Operation above 100°C to 125°C is limited to read-only operationꢀ
3
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ACCHARACTERISTICSWRITE/ERASE/PROGRAMOPERATIONS-WECONTROLLED
ꢀVCC = 5(0V, TA = -55°C to +125°C) ꢀNote 6)
Parameter
Symbol
-90
-120
-150
Unit
Min
Max
Min
Max
Min
Max
WriteCycleTime
tAVAV
tWC
tCS
tWP
tAS
tDS
tDH
tAH
90
120
150
ns
ns
ChipSelectSetupTime
WriteEnablePulseWidth
AddressSetupTime
tELWL
0
45
0
0
50
0
0
50
0
tWLWH
tAVWL
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWHWH2
tGHWL
tVCS
ns
ns
DataSetupTime
45
0
50
0
50
0
ns
Data Hold Time
ns
Address Hold Time
45
20
50
20
50
20
ns
WriteEnablePulseWidthHigh
DurationofByteProgrammingOperation(1)
SectorErase(2)
tWPH
ns
300
15
300
15
300
15
µs
sec
µs
µs
sec
sec
ns
ReadRecoveryTimebeforeWrite
VCCSetupTime
0
0
0
50
50
50
ChipProgrammingTime
Chip Erase Time (3)
44
44
44
256
256
256
OutputEnableHoldTime(4)
RESETPulseWidth(5)
tOEH
tRP
10
10
10
500
500
500
ns
NOTES:
1ꢀ Typical value for tWHWH1 is 7µsꢀ
2ꢀ Typical value for tWHWH2 is 1secꢀ
3ꢀ Typical value for Chip Erase Time is 32secꢀ
4ꢀ For Toggle and Data Pollingꢀ
5ꢀ RESET internally tied to Vcc for the default pin configuration in the HIP packageꢀ
6ꢀ Extended temperature devices are fully operational from -55°C to +100°Cꢀ Operation above 100°C to 125°C is limited to read-only operationꢀ
ACCHARACTERISTICSREAD-ONLYOPERATIONS
ꢀVCC = 5(0V, TA = -55°C to +125°C) ꢀNote 3)
Parameter
Symbol
-90
-120
-150
Unit
Min
Max
Min
Max
Min
Max
ReadCycleTime
tAVAV
tRC
tACC
tCE
tOE
tDF
tDF
tOH
90
120
150
ns
ns
ns
ns
ns
ns
ns
AddressAccessTime
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
90
90
40
20
20
120
120
50
150
150
55
Chip Select Access Time
OutputEnabletoOutputValid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
30
35
30
35
OutputHoldfromAddresses, CSorOEChange,
whichever is First
0
0
0
RST Low to Read Mode (1,2)
tReady
20
20
20
µs
1ꢀ Guaranteedbydesign, nottestedꢀ
2ꢀ RESET internally tied to Vcc for the default pin configuration in the HIP packageꢀ
3ꢀ Extended temperature devices are fully operational from -55°C to +100°Cꢀ Operation above 100°C to 125°C is limited to read-only operationꢀ
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ACCHARACTERISTICSWRITE/ERASE/PROGRAMOPERATIONS,CSCONTROLLED
ꢀVCC = 5(0V, VSS = 0V, TA = -55°C to +125°C) ꢀNote 5)
Parameter
Symbol
-90
-120
-150
Unit
Min
90
0
Max
Min
120
0
Max
Min
150
0
Max
WriteCycleTime
tAVAV
tWLEL
tELEH
tWC
tWS
tCP
tAS
tDS
tDH
ns
ns
WriteEnableSetupTime
ChipSelectPulseWidth
AddressSetupTime
45
0
50
0
50
0
ns
tAVEL
ns
DataSetupTime
tDVEH
tEHDX
tELAX
45
0
50
0
50
0
ns
DataHoldTime
ns
AddressHoldTime
tAH
tCPH
45
20
50
20
50
20
ns
ChipSelectPulseWidthHigh
DurationofByteProgrammingOperation(1)
Sector Erase Time (2)
ReadRecoveryTime
tEHEL
ns
tWHWH1
tWHWH2
tGHEL
300
15
300
15
300
15
µs
sec
µs
sec
sec
ns
0
0
0
ChipProgrammingTime
Chip Erase Time (3)
44
44
44
256
256
256
OutputEnableHoldTime(4)
tOEH
10
10
10
NOTES:
1ꢀ Typical value for tWHWH1 is 7µsꢀ
2ꢀ Typical value for tWHWH2 is 1secꢀ
3ꢀ Typical value for Chip Erase Time is 32secꢀ
4ꢀ For Toggle and Data Pollingꢀ
5ꢀ Extended temperature devices are fully operational from -55°C to +100°Cꢀ Operation above 100°C to 125°C is limited to read-only operationꢀ
ACTESTCONDITIONS
FIGꢀ 3
ACTESTCIRCUIT
Parameter
Typ
Unit
InputPulseLevels
VIL = 0, VIH = 3#0
V
ns
V
InputRiseandFall
5
IOL
InputandOutputReferenceLevel
OutputTimingReferenceLevel
1#5
1#5
Current Source
V
Notes:
VZ is programmable from -2V to +7Vꢀ
IOL & IOH programmablefrom0to16mAꢀ
Tester Impedance Z0 = 75 ýꢀ
D.U.T.
VZ ≈ 1.5V
(Bipolar Supply)
Ceff = 50 pf
VZ is typically the midpoint of VOH and VOL
ꢀ
IOL & IOH are adjusted to simulate a typical resistive load circuitꢀ
ATE tester includes jig capacitanceꢀ
IOH
Current Source
FIGꢀ 4
RESETTIMINGDIAGRAM
RESET
tRP
tReady
5
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FIGꢀ 5
ACWAVEFORMSFORREADOPERATIONS
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FIGꢀ 6
WRITE/ERASE/PROGRAM
OPERATION,WECONTROLLED
NOTES:
1ꢀ PA is the address of the memory location to be programmedꢀ
2ꢀ PD is the data to be programmed at byte addressꢀ
3ꢀ D7 is the output of the complement of the data written to each chipꢀ
4ꢀ DOUT is the output of the data written to the deviceꢀ
5ꢀ Figure indicates last two bus cycles of four bus cycle sequenceꢀ
7
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FIGꢀ 7
ACWAVEFORMSCHIP/SECTOR
ERASEOPERATIONS
NOTE:
1ꢀ SA is the sector address for Sector Eraseꢀ
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FIGꢀ 8
ACWAVEFORMSFORDATAPOLLING
DURINGEMBEDDEDALGORITHMOPERATIONS
9
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FIGꢀ 9
ALTERNATECSCONTROLLED
PROGRAMMINGOPERATIONTIMINGS
Notes:
1ꢀ PArepresentstheaddressofthememorylocationtobeprogrammedꢀ
2ꢀ PD represents the data to be programmed at byte addressꢀ
3ꢀ D7 is the output of the complement of the data written to each chipꢀ
4ꢀ DOUT is the output of the data written to the deviceꢀ
5ꢀ Figure indicates the last two bus cycles of a four bus cycle sequenceꢀ
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FIGꢀ 10 ALTERNATE PIN CONFIGURATION FOR WF2M32I-XHX5
PINDESCRIPTION
TOP VIEW
I/O0-31
DataInputs/Outputs
1
12
23
34
45
56
A0-20
WE
AddressInputs
WriteEnable
ChipSelects
OutputEnable
PowerSupply
Ground
I/O
I/O
8
9
RESET
CS
I/O15
I/O14
I/O13
I/O12
OE
I/O24
I/O25
I/O26
V
CC
I/O31
I/O30
I/O29
I/O28
CS1-4
OE
2
CS4
I/O10
GND
I/O11
NC
VCC
GND
A
A
A
A
A
14
16
11
0
A
7
I/O27
RESET
Reset
A
A
A
V
10
9
A
12
NC
13
A
A
A
4
5
6
A
A
A
1
2
3
A
17
BLOCKDIAGRAM
15
CC
WE
A
CS3
CS4
CS1
CS2
RESET
WE
OE
A0-20
18
I/O
I/O
I/O
I/O
7
A
8
I/O16
I/O17
I/O18
A
20
I/O23
I/O22
I/O21
I/O20
I/O
I/O
I/O
0
1
2
CS
1
6
5
4
CS
3
2M x 8
2M x 8
2M x 8
2M x 8
A
19
GND
I/O19
8
8
8
8
I/O
3
11
22
33
44
55
66
I/O16-23
I/O24-31
I/O0-7
I/O8-15
FIGꢀ 11 ALTERNATE PIN CONFIGURATION FOR WF2M32U-XG2UX5
TOP VIEW
PINDESCRIPTION
I/O0-31
A0-20
DataInputs/Outputs
AddressInputs
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
WE
CS
WriteEnable
ChipSelect
OutputEnable
PowerSupply
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
OE
VCC
GND
0.940"
The WEDC 68 lead G2U CQFP fills the
same fit and function as the JEDEC 68
lead CQFJ or 68 PLCC# But the G2U has
the TCE and lead inspection advantage of
the CQFP form#
GND
RESET
Reset
I/O
I/O
8
9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
BLOCKDIAGRAM
RESET
CS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
WE
OE
A
0-20
2M x 8
2M x 8
2M x 8
2M x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
11
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PACKAGE 401: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H)
30.1 (1.185) ± 0.38 (0.015) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
6.22 (0.245)
MAX
3.81 (0.150)
± 0.1 (0.005)
1.27 (0.050) ± 0.1 (0.005)
0.76 (0.030) ± 0.1 (0.005)
2.54 (0.100)
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
TYP
0.46 (0.018) ± 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
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PACKAGE 510: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2U)
The WEDC 68 lead G2U
CQFP fills the same fit
and function as the
JEDEC 68 lead CQFJ or
68 PLCC( But the G2U
has the TCE and lead
inspection advantage of
the CQFP form(
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
13
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ORDERINGINFORMATION
W F 2M32 X - XXX X X 5 X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
VPP PROGRAMMINGVOLTAGE
5 = 5 V
DEVICE GRADE:
QE = Compliant
-55°C to +100°C (Note 1)
E
I
C
=
=
=
Extended
Industrial
Commercial
-55°C to +100°C (Note 1)
-40°C to +85°C
0°C to +70°C
PACKAGETYPE:
= Ceramic Hex In line Package, HIP (Package 401)
H
G2U = 22ꢀ4mm Ceramic Quad Flat Pack, CQFP (Package 510)
ACCESS TIME (ns)
IMPROVEMENTMARK
For HIP Package
Blank = 4CS and 4WE
I = 4CS and 1WE, RESET
For G2U Package
Blank = 4CS and 4WE
U = 1CS and 1WE
ORGANIZATION, 2M x 32
User configurable as 4M x 16 or 8M x 8
(Except WF2M32U-XG2UX which is 32 bit wide onlyꢀ)
Flash
WHITE ELECTRONIC DESIGNS CORP#
Note:
1ꢀ Extended temperature devices are fully operational from -55°C to +100°Cꢀ Operation above 100°C to 125°C is limited to read-only operationꢀ
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相关型号：
WF2M32U-90G2UI5
Flash Module, 2MX32, 90ns, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
WEDC
WF2M32U-90G2UM5
Flash Module, 2MX32, 90ns, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WF2M32U-90G2UM5
Flash Module, 2MX32, 90ns, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
WEDC
WF2M32U-90G2UM5A
Flash Module, 2MX32, 90ns, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
MICROSEMI
WF2M32U-90G2UQ5
Flash Module, 2MX32, 90ns, CQFP68, 22.40 X 22.40 MM, 3.56 MM HEIGHT, HERMETIC SEALED, CERAMIC, QFP-68
WEDC
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