WS1M8-17DJMA [WEDC]
2x512Kx8 DUALITHICTM SRAM; 2x512Kx8 DUALITHICTM SRAM型号: | WS1M8-17DJMA |
厂家: | WHITE ELECTRONIC DESIGNS CORPORATION |
描述: | 2x512Kx8 DUALITHICTM SRAM |
文件: | 总6页 (文件大小:362K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
WS1M8-XXX
White Electronic Designs
2x512Kx8 DUALITHIC™ SRAM
FEATURES
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Access Times 17, 20, 25, 35, 45, 55ns
Revolutionary, Center Power/Ground Pinout
Packaging:
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Organized as two banks of 512Kx8
Commercial, Industrial and Military Temperature Ranges
5 Volt Power Supply
Low Power CMOS
TTL Compatible Inputs and Outputs
• 32 pin, Hermetic Ceramic DIP (Package 300)
• 36 lead Ceramic SOJ (Package 100)
• 36 lead Ceramic Flatpack (Package 226)
PIN CONFIGURATION FOR WS1M8-XDJX
AND WS1M8-XFX
PIN CONFIGURATION FOR WS1M8-XCX
36 CSOJ
32 DIP
TOP VIEW
36 FLATPACK
TOP VIEW
A18
A16
A14
A12
A7
1
2
3
4
5
6
32
VCC
A0
A1
A2
A3
A4
CS1#
I/O0
I/O1
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
31 A15
30 A17
29 WE#
28 A13
27 A8
A18
A17
A16
A15
OE#
I/O7
I/O6
GND
A6
A5
7
26 A9
A4
A3
A2
A1
8
9
25 A11
24 CS2#
23 A10
22 CS1#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
V
CC
9
GND
I/O2
I/O3
WE#
A5
A6
A7
A8
A9
10
11
12
13
14
15
16
17
18
VCC
10
11
12
13
14
15
16
I/O5
I/O4
A14
A13
A12
A11
A0
I/O0
I/O1
I/O2
GND
A10
CS2#
Pin Description
Pin Description
A0-18
I/O0-7
CS1-2#
OE#
Address Inputs
A0-18
I/O0-7
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0V Power
Ground
Data Input/Output
CS1-2#
WE#
VCC
Chip Selects
Write Enable
+5.0V Power
Ground
WE#
VCC
GND
GND
Block Diagram
Block Diagram
I/O0-7
I/O0-7
WE#
OE#
A0-18
WE#
A0-18
512K x 8
512K x 8
512K x 8
512K x 8
CS1# (1)
CS2# (1)
CS1# (1)
CS2# (1)
NOTE:
1. CS1# and CS2# are used to select the lower and upper 512Kx8 of the device. CS1# and CS2# must not be enabled at the same time.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WS1M8-XXX
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Symbol
TA
TSTG
VG
TJ
Min
-55
-65
-0.5
Max
+125
+150
VCC +0.5
150
Unit
°C
°C
V
°C
V
CS#
H
L
L
L
OE# WE#
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
X
L
X
H
X
H
L
H
VCC
-0.5
7.0
NOTE: OE# is internally tied to the GND and not accessible on the WS1M8-XCXX.
RECOMMENDED OPERATING CONDITIONS
CAPACITANCE
TA = +25°C
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Symbol
VCC
VIH
Min
4.5
2.2
Max
5.5
VCC + 0.3
+0.8
Unit
V
V
Parameter
Input capacitance
Output capicitance
Symbol
CIN
COUT
Condition
VIN = 0V, f = 1.0MHz
VOUT = 0V, f = 1.0MHz
Max
20
Unit
pF
20
pF
VIL
TA
-0.3
-55
V
°C
+125
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Sym
Conditions
Min
Max
10
10
180
40
0.4
Units
µA
µA
mA
mA
V
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
ILI
ILO
ICC
ISB
VCC = 5.5, VIN = GND to VCC
CS# = VIH, OE# = VIH, VOUT = GND to VCC
CS# = VIL, OE# = VIH, f = 5MHz, VCC = 5.5
CS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
IOL = 6mA
1
1
1
VOL
VOH
IOH = -4.0mA
2.4
V
NOTE: DC test conditions: VIH = VCC -0.3V , VIL = 0.3V
1. OE# is internally tied to the GND and not accessible on the WS1M8-XCXX.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 5
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WS1M8-XXX
White Electronic Designs
AC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
-17
-20
-25
-35
-45
-55
Parameter
Read Cycle
Symbol
Units
Min Max Min Max Min Max Min Max Min Max Min Max
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
tRC
tAA
tOH
17
0
20
0
25
0
35
0
45
0
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
17
20
25
35
45
55
tACS
17
9
20
10
25
12
35
25
45
25
55
25
2
tOE
1
tCLZ
2
0
2
0
2
0
4
0
4
0
4
0
2
tOLZ
tCHZ
tOHZ
1
9
9
10
10
12
12
15
15
20
20
20
20
2
1. This parameter is guaranteed by design but not tested.
2. OE# is internally tied to the GND and not accessible on the WS1M8-XCXX.
AC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
-17 -20 -25
Parameter
Write Cycle
Symbol
-35
-45
-55
Units
Write Cycle Time
tWC
tCW
tAW
tDW
tWP
tAS
17
14
14
9
14
0
20
14
14
10
14
0
25
15
15
10
15
0
35
25
25
20
25
0
45
35
35
25
35
0
55
50
50
25
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
tAH
0
2
0
3
0
4
0
4
5
5
5
5
1
tOW
1
tWHZ
tDH
9
9
10
15
15
25
0
0
0
0
0
0
1. This parameter is guaranteed by design but not tested.
AC TEST CIRCUIT
AC TEST CONDITIONS
Parameter
Typ
Unit
V
ns
V
Input Pulse Levels
VIL = 0, VIH = 3.0
IOL
Input Rise and Fall
5
Current Source
Input and Output Reference Level
Output Timing Reference Level
1.5
1.5
V
Notes:
D.U.T.
VZ
≈ 1.5V
VZ is programmable from -2V to +7V.
(Bipolar Supply)
Ceff = 50 pf
I
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
V
I
.
IOH
Current Source
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WS1M8-XXX
White Electronic Designs
TIMING WAVEFORM – READ CYCLE
tRC
ADDRESS
CS#
tRC
tAA
tAA
ADDRESS
DATA I/O
tCHZ
tACS
tCLZ
tOH
OE#
PREVIOUS DATA VALID
DATA VALID
tOE
tOLZ
tOHZ
READ CYCLE 1 (CS# = OE# = V , WE# = V
)
IL IH
DATA I/O
DATA VALID
HIGH IMPEDANCE
READ CYCLE 2 (WE# = V
IH
)
NOTE: OE# is internally tied to the GND and not accessible on the WS1M8-XCXX.
WRITE CYCLE – WE# CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
CS#
tAS
tWP
WE#
tOW
tDH
tDW
DATA VALID
WRITE CYCLE 1, WE# CONTROLLED
tWHZ
DATA I/O
WRITE CYCLE – CS# CONTROLLED
tWC
ADDRESS
CS#
tAW
tAH
tAS
tCW
tWP
WE#
tDW
tDH
DATA I/O
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WS1M8-XXX
White Electronic Designs
PACKAGE 100: 36 LEAD, CERAMIC SOJ
23.37 (0.920) 0.25 (0.010)
4.76 (0.184) MAX
0.89 (0.035)
Radius TYP
0.20 (0.008)
0.05 (0.002)
11.3 (0.446)
0.2 (0.009)
9.55 (0.376) 0.25 (0.010)
1.27 (0.050) 0.25 (0.010)
PIN 1 IDENTIFIER
1.27 (0.050) TYP
21.59 (0.850) TYP
0.43 (0.017)
0.05 (0.002)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 226: 36 LEAD, CERAMIC FLAT PACK
23.37 (0.920)
0.25 (0.010)
PIN 1
IDENTIFIER
3.18 (0.125)
MAX
12.95 (0.510)
0.13 (0.005)
12.7 (0.500)
0.5 (0.020)
5.1 (0.200)
0.25 (0.010)
0.43 (0.017)
0.05 (0.002)
1.27 (0.050) TYP
21.59 (0.850) TYP
0.127 (0.005)
0.05 (0.002)
3.8 (0.150)
TYP
32.64 (1.285) TYP
38.1 (1.50) 0.4 (0.015)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 5
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WS1M8-XXX
White Electronic Designs
PACKAGE 300: 32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
42.4 (1.670) 0.4 (0.016)
15.04 (0.592)
0.3 (0.012)
4.34 (0.171) 0.79 (0.031)
PIN 1 IDENTIFIER
0.84 (0.033)
0.4 (0.014)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
W S 1M8 X - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A
= Solder dip leads
DEVICE GRADE:
M = Military Screened -55°C to +125°C
I
C
=
=
Industrial
Commercial
-40°C to +85°C
0°C to +70°C
PACKAGE:
32 pin Ceramic 0.600" DIP (Package 300)
DJ = 36 Lead Ceramic SOJ (Package 100)
36 Lead Ceramic Flatpack (Package 226)
C
=
F
=
ACCESS TIME (ns)
IMPROVEMENT MARK:
Blank = Standard Power
ORGANIZATION, two banks of 512K x 8
SRAM
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2004
Rev. 5
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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