WSF41632-22G2TC [WEDC]
128KX32 SRAM & 512Kx32 FLASH MIXED MODULE; 128KX32 SRAM和FLASH 512Kx32混合模块
| 型号： | WSF41632-22G2TC |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 128KX32 SRAM & 512Kx32 FLASH MIXED MODULE |
| 文件： | 总14页 (文件大小：526K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WSF41632-22XX
White Electronic Designs
PRELIMINARY*
128KX32 SRAM & 512Kx32 FLASH MIXED MODULE
ꢀ
Built-in decoupling caps and multiple ground pins
FEATURES
for low noise operation
ꢀ
Access times of 25ns (SRAM) and 120ns (FLASH)
ꢀ
Weight - 13 grams typical
ꢀ
Packaging
• 66 pin, PGA Type, 1.385" square HIP, hermetic
ceramic HIP (Package 402)
FLASH MEMORY FEATURES
ꢀ
100,000 erase/program cycles minimum
Sector architecture
• 68 lead, hermetic CQFP (G2T), 22.4mm (0.880")
square (Package 509) 4.57mm (0.180") height
Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (FIGURE 2). Package to be developed.
ꢀ
• 8 equal size sectors of 64KBytes each
• Any combination of sectors can be concurrently
erased. Also supports full chip erase
ꢀ
ꢀ
ꢀ
128Kx32 SRAM
ꢀ
ꢀ
ꢀ
ꢀ
5V programming; 5V 10ꢀ supply
Embedded erase and program algorithms
Hardware write protection
512Kx32 5V Flash
Organized as 128Kx32 of SRAM and 512Kx32 of
Flash Memory with common data bus
ꢀ
ꢀ
Low power CMOS
Page program operation and internal program
control time.
Commercial, industrial and military temperature
ranges
Note: For programming information refer to flash programming 4M5 application note.
ꢀ
TTL compatible inputs and outputs
* This product is under development, is not qualified or characterized and is subject to
change without notice.
PIN CONFIGURATION FOR WSF41632-22H2X
Top View
Pin Description
D0-31
A0-18
Data Inputs/Outputs
Address Inputs
SWE#1-4 SRAM Write Enables
1
12
23
34
45
56
SCS#
OE#
VCC
GND
NC
SRAM Chip Select
Output Enable
Power Supply
Ground
I/O8
I/O9
I/O10
A14
A16
A11
FWE2#
SWE2#
GND
I/O11
A10
I/O15
I/O14
I/O13
I/O12
OE#
A17
I/O24
I/O25
I/O26
A7
VCC
SWE4#
FWE4#
I/O27
A4
I/O31
I/O30
I/O29
I/O28
A1
Not Connected
FWE#1-4 Flash Write Enables
FCS Flash Chip Select
A12
A9
SWE1#
A13
A5
A2
Block Diagram
A0
A15
FWE1#
I/O7
A6
A3
FWE
1
#
SWE
1
#
FWE
2
#
SWE
2
#
FWE
3
#
SWE
3
#
FWE
4
#
4
SWE #
OE#
A0-18
A18
I/O0
I/O1
I/O2
VCC
A8
FWE3#
SWE3#
GND
I/O19
I/O23
I/O22
I/O21
I/O20
SCS#
FCS#
FCS#
SCS#
I/O3
I/O6
I/O16
I/O17
I/O18
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
I/O5
I/O4
11
22
33
44
55
66
I/O0-7
I/O8-15
I/O16-23
I/O24-31
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
FIGURE 2 – PIN CONFIGURATION FOR WSF41632-22G2TX
Top View
Pin Description
D0-31
A0-18
Data Inputs/Outputs
Address Inputs
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
SWE#1-4 SRAM Write Enables
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
16
17
18
19
20
21
22
23
SCS#
OE#
VCC
GND
NC
SRAM Chip Select
Output Enable
Power Supply
Ground
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
Not Connected
FWE#1-4 Flash Write Enables
GND
GND
I/O
I/O
8
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
FCS
Flash Chip Select
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Block Diagram
FWE
1
#
SWE
1
#
FWE
2
#
SWE
2
#
FWE
3
#
SWE
3
#
FWE
4
#
4
SWE #
OE#
A
0-18
SCS#
FCS#
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
128K x 8 Flash
128K x 8 SRAM
I/O0-7
I/O8-15
I/O16-23
I/O24-31
0.940"
The WEDC 68 lead G2T CQFP fills the same fit and function
as the JEDEC 68 lead CQFJ or 68 PLCC. But the G2T has
the TCE and lead inspection advantage of the CQFP form.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
SRAM TRUTH TABLE
Parameter
Symbol
TA
TSTG
VG
TJ
VCC
Min
-55
-65
-0.5
Max
+125
+150
7.0
150
7.0
Unit
°C
°C
V
°C
V
SCS#
OE#
X
L
H
X
SWE#
Mode
Standby
Read
Read
Write
Data I/O
High Z
Data Out
High Z
Power
Standby
Active
Active
Active
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
H
L
L
L
X
H
H
L
Data In
-0.5
NOTE:
1. FCS# must remain high when SCS# is low.
Parameter
Flash Data Retention
20 years
100,000 min
CAPACITANCE
Flash Endurance (write/erase cycles)
NOTE:
1. Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and
affect reliability.
Ta = +25°C
Parameter
Symbol
Conditions
Max Unit
OE# capacitance
F/S WE1-4# capacitance
F/S CS# capacitance
COE
CWE
CCS
CI/O
CAD
VIN = 0 V, f = 1.0 MHz 80 pF
VIN = 0 V, f = 1.0 MHz 30 pF
VIN = 0 V, f = 1.0 MHz 50 pF
VIN = 0 V, f = 1.0 MHz 30 pF
VIN = 0 V, f = 1.0 MHz 80 pF
D0-31 capacitance
RECOMMENDED OPERATING CONDITIONS
A0-16 capacitance
Parameter
Symbol
VCC
VIH
Min
4.5
2.2
Max
5.5
VCC + 0.3
+0.8
Unit
V
V
This parameter is guaranteed by design but not tested.
Supply Voltage
Input High Voltage
Input Low Voltage
VIL
-0.5
V
DC CHARACTERISTICS
VCC = 5.0V, VSS = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
SRAM Operating Supply Current x 32 Mode
Standby Current
SRAM Output Low Voltage
SRAM Output High Voltage
Flash VCC Active Current for Read (1)
Flash VCC Active Current for Program or Erase (2)
Flash Output Low Voltage
Symbol Conditions
Min
Max
10
10
620
80
0.4
Unit
µA
µA
mA
mA
V
ILI
ILO
ICCx32
ISB
VOL
VOH
ICC1
ICC2
VOL
VOH1
VOH2
VLKO
VCC = 5.5, VIN = GND to VCC
SCS# = VIH, OE# = VIH, VOUT = GND to VCC
SCS# = VIL, OE# = FCS# = VIH, f = 5MHz, VCC = 5.5
FCS# = SCS# = VIH, OE# = VIH, f = 5MHz, VCC = 5.5
IOL = 8mA, VCC = 4.5
IOH = -4.0mA, VCC = 4.5
2.4
V
FCS# = VIL, OE# = SCS# = VIH
FCS# = VIL, OE# = SCS# = VIH
IOL = 8.0mA, VCC = 4.5
260
300
0.45
mA
mA
V
V
V
Flash Output High Voltage
Flash Output High Voltage
Flash Low VCC Lock Out Voltage
IOH = -2.5 mA, VCC = 4.5
0.85 x VCC
VCC -0.4
3.2
IOH = -100 µA, VCC = 4.5
4.2
V
NOTES:
1. The ICC current listed includes both the DC operating current and the frequency dependent component (@ 5 MHz).
The frequency component typically is less than 2mA/MHz, with OE# at VIH
CC active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions: VIL = 0.3V, VIH = VCC - 0.3V
.
2.
I
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
SRAM AC CHARACTERISTICS
SRAM AC CHARACTERISTICS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Read Cycle
Symbol
-25
Units
Parameter
Write Cycle
Symbol
Min
-25
Units
Min
Max
Max
Read Cycle Time
Address Access Time
tRC
tAA
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
tWC
tCW
tAW
tDW
tWP
tAS
25
20
20
15
20
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold from Write Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
tOH
tACS
tOE
0
25
15
1
tCLZ
3
0
1
tOLZ
tCHZ
tOHZ
tAH
0
3
1
1
12
12
tOW
tWHZ
tDH
1
1
15
0
1. This parameter is guaranteed by design but not tested.
1. This parameter is guaranteed by design but not tested.
FIGURE 2 – AC TEST CIRCUIT
AC Test Conditions
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
IL = 0, VIH = 3.0
Unit
IOL
V
V
ns
V
Current Source
5
1.5
1.5
V
D.U.T.
VZ ≈ 1.5V
(Bipolar Supply)
Notes:
Ceff = 50 pf
V
Z is programmable from -2V to +7V.
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
I
V
I
.
IOH
Current Source
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
FIGURE 3 – SRAM TIMING WAVEFORM - READ CYCLE
tRC
ADDRESS
SCS#
tAA
tRC
tAA
ADDRESS
DATA I/O
tCHZ
tACS
tCLZ
SOE#
tOH
tOE
tOLZ
tOHZ
PREVIOUS DATA VALID
DATA VALID
DATA I/O
DATA VALID
HIGH IMPEDANCE
READ CYCLE 1, (SCS# = OE# = VIL, SWE# = FCS# = VIH
)
READ CYCLE 2, (SWE# = FCS# = VIH)
FIGURE 4 – SRAM WRITE CYCLE - SWE# CONTROLLED
tWC
ADDRESS
tAW
tAH
tCW
SCS#
tAS
tWP
SWE#
tOW
tWHZ
tDW
tDH
DATA I/O
DATA VALID
WRITE CYCLE 1, SWE# CONTROLLED (FCS# = VIH
)
FIGURE 5 – SRAM WRITE CYCLE - SCS# CONTROLLED
tWC
ADDRESS
tAW
tAH
tAS
tCW
SCS#
tWP
SWE#
tDW
tDH
DATA I/O
DATA VALID
WRITE CYCLE 2, SCS# CONTROLLED (FCS# = VIH
)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FWE# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-120
Unit
Min
120
0
50
0
Max
Write Cycle Time
tAVAV
tELWL
tWLWH
tAVWL
tWC
tCS
tWP
tAS
ns
ns
ns
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
ns
Data Setup Time
Data Hold Time
Address Hold Time
tDVWH
tWHDX
tWLAX
tWHWL
tWHWH1
tWHWH2
tGHWL
tDS
tDH
tAH
50
0
50
20
ns
ns
ns
ns
µs
sec
µs
µs
sec
ns
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Chip and Sector Erase Time (2)
Read Recovery Time Before Write
VCC Set-up Time
Chip Programming Time
Output Enable Setup Time
Output Enable Hold Time (4)
Chip Erase Time (3)
tWPH
300
15
0
50
tVCS
11
64
tOES
tOEH
0
10
ns
sec
NOTES:
1. Typical value for tWHWH1 is 7ns.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
4. For Toggle and Data# Polling.
FLASH AC CHARACTERISTICS – READ ONLY OPERATIONS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-120
Unit
Min
Max
Read Cycle Time
tAVAV
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tRC
tACC
tCE
tOE
tDF
120
ns
ns
ns
ns
ns
ns
ns
Address Access Time
120
120
50
Chip Select Access Time
OE# to Output Valid
Chip Select to Output High Z (1)
OE# High to Output High Z (1)
Output Hold from Address, FCS# or OE# Change, whichever is first
1. Guaranteed by design, not tested.
30
tDF
30
tOH
0
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
FLASH AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS, FCS# CONTROLLED
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-120
Unit
Min
120
0
Max
Write Cycle Time
tAVAV
tWLEL
tELEH
tWC
tWS
tCP
ns
ns
FWE# Setup Time
FCS# Pulse Width
50
0
ns
Address Setup Time
Data Setup Time
tAVEL
tAS
ns
tDVEH
tEHDX
tELAX
tDS
50
0
ns
Data Hold Time
tDH
tAH
ns
Address Hold Time
50
20
ns
FCS# Pulse Width High
Duration of Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
tEHEL
tCPH
ns
tWHWH1
tWHWH2
tGHEL
300
15
µs
sec
ns
0
11
64
sec
sec
NOTES:
1. Typical value for tWHWH1 is 7ns.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 8sec.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
FIGURE 6 – AC WAVEFORMS FOR FLASH MEMORY READ OPERATIONS
tRC
Addresses
Addresses Stable
tACC
FCS#
OE#
tDF
tOE
FWE#
tCE
tOH
High Z
High Z
Outputs
Output Valid
NOTE: SCS# = VIH
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
FIGURE 7 – WRITE/ERASE/PROGRAM OPERATION, FLASH MEMORY FWE# CONTROLLED
Data# Polling
Addresses
FCS#
5555H
tWC
PA
PA
tAH
tRC
tAS
tGHWL
OE#
tWP
tWHWH1
FWE#
tWPH
tDH
tCS
tDF
tOH
tOE
A0H
PD
DOUT
D7#
Data
tDS
5.0 V
tCE
NOTES:
1. PA is the address of the memory location to be programmed.
2. PD is the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles of four bus cycle sequence.
6. SCS# = VIH
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
FIGURE 8 – AC WAVEFORMS CHIP/SECTOR ERASE OPERATIONS FOR FLASH MEMORY
tAH
tAS
Addresses
FCS#
5555H
2AAAH
5555H
5555H
2AAAH
SA
tGHWL
OE#
tWP
FWE#
tWPH
tCS
tDH
Data
VCC
AAH
55H
80H
AAH
55H
10H/30H
tDS
tVCS
Notes:
1. SA is the sector address for Sector Erase.
2. SCS# = VIH
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
FIGURE 9 – AC WAVEFORMS FOR DATA# POLLING DURING EMBEDDED ALGORITHM
OPERATIONS FOR FLASH MEMORY
tCH
FCS#
tDF
tOE
OE#
tOEH
FWE#
tCE
tOH
High Z
D7 =
Valid Data
D7#
D7
tWHWH 1 or 2
D0-D7
D0-D6 = Invalid
D7
D0-D6
D7
Valid Data
tOE
High Z
D7
Valid Data
tWHWH 1 or 2
Note: SCS# = VIH
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
FIGURE 10 – WRITE/ERASE/PROGRAM OPERATION FOR FLASH MEMORY, CS# CONTROLLED
Data# Polling
Addresses
FWE#
5555H
PA
PA
tWC
tAH
tAS
tGHEL
OE#
tCP
tWHWH1
FCS#
tCPH
tWS
tDH
D7#
A0H
PD
DOUT
Data
tDS
5.0 V
NOTES:
1. PA represents the address of the memory location to be programmed.
2. PD represents the data to be programmed at byte address.
3. D7# is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates the last two bus cycles of a four bus cycle sequence.
6. SCS# = VIH
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
25.15 (0.990) 0.26 (0.010) SQ
4.57 (0.180) MAX
22.36 (0.880) 0.26 (0.010) SQ
0.27 (0.011) 0.04 (0.002)
Pin 1
0.25 (0.010) REF
R 0.25
(0.010)
24.03 (0.946)
0.26 (0.010)
0.19 (0.007)
0.06 (0.002)
1° / 7°
1.0 (0.040)
0.127 (0.005)
23.87
(0.940) REF
DETAIL A
1.27 (0.050) TYP
SEE DETAIL "A"
0.38 (0.015) 0.05 (0.002)
20.3 (0.800) REF
The WEDC 68 lead G2T CQFP
fills the same fit and function
as the JEDEC 68 lead CQFJ
or 68 PLCC. But the G2T has
the TCE and lead inspection
advantage of the CQFP form.
0.940"
TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WSF41632-22XX
White Electronic Designs
PRELIMINARY
PACKAGE 402: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H2)
35.2 (1.385) 0.38 (0.015) SQ
PIN 1 IDENTIFIER
SQUARE PAD
ON BOTTOM
25.4 (1.0) TYP
5.7 (0.223)
MAX
3.81 (0.150)
0.1 (0.005)
1.27 (0.050) 0.1 (0.005)
0.76 (0.030) 0.1 (0.005)
2.54 (0.100)
1.27 (0.050) TYP DIA
15.24 (0.600) TYP
25.4 (1.0) TYP
TYP
0.46 (0.018) 0.05 (0.002) DIA
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
W S F 41632 - 22 X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened
I = Industrial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
C = Commercial
PACKAGE TYPE:
H2 = Ceramic Hex In-line Package, HIP (Package 402)
G2T = 22.4mm Ceramic Quad Flat Pack, CQFP (Package 509)
ACCESS TIME (ns)
22 = 25ns SRAM and 120ns FLASH
ORGANIZATION, 128K x 32
Flash PROM
SRAM
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October, 2002
Rev. 4
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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