WV3EG216M64STSU-D4 [WEDC]
256MB - 2x16Mx64 DDR SDRAM UNBUFFERED; 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED
| 型号： | WV3EG216M64STSU-D4 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 256MB - 2x16Mx64 DDR SDRAM UNBUFFERED |
| 文件： | 总11页 (文件大小：264K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
256MB – 2x16Mx64 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
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Double-data-rate architecture
The WV3EG216M64STSU is a 2x16Mx64 Double
Data Rate SDRAM memory module based on 256Mb
DDR SDRAM components. The module consists of
eight 16Mx16 DDR SDRAMs in 66 pin TSOP package
mounted on a 200 Pin FR4 substrate.
PC2700@CL=2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2,5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power Supply: VCC/VCCQ: 2.5V 0.20V
Dual Rank
Synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges and Burst Lenths allow the
same device to be useful for a variety of high bandwidth,
high performance memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
Standard 200 pin SO-DIMM package
• Package height options:
D4: 31.75mm (1.25")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR333@CL=2.5
166MHz
Clock Speed
CL-tRCD-tRP
2.5-3-3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
PIN CONFIGURATIONS
PIN NAMES
Pin
1
Symbol
VREF
VREF
VSS
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Symbol
VSS
Pin
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Symbol
A9
Pin
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Symbol
DQ42
DQ46
DQ43
DQ47
VCC
A0 – A12
BA0-BA1
DQ0-DQ63
DQS0-DQS7
CK0, CK1
CK0#, CK1#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
DM0-DM7
VCC
VCCQ
VSS
VREF
VCCSPD
SDA
SCL
SA0-SA2
NC
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Data Strobe Input/Output
Clock Input
2
VSS
A8
3
DQ19
DQ23
DQ24
DQ28
VCC
VSS
4
VSS
VSS
5
DQ0
DQ4
DQ1
DQ5
VCC
A7
Clock Input
6
A6
VCC
Clock Enable Input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
7
A5
VCC
8
VCC
A4
CK1#
VSS
9
DQ25
DQ29
DQS3
DM3
VSS
A3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VCC
A2
CK1
DQS0
DM0
DQ2
DQ6
VSS
A1
VSS
A0
VSS
Data-In Mask
Power Supply
VCC
DQ48
DQ52
DQ49
DQ53
VCC
VSS
VCC
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
Serial clock
Address in EEPROM
No Connect
DQ26
DQ30
DQ27
DQ31
VCC
A10
VSS
BA1
BA0
RAS#
WE#
CAS#
CS0#
CS1#
NC
DQ3
DQ7
DQ8
DQ12
VCC
VCC
DQS6
DM6
DQ50
DQ54
VSS
VCC
NC
VCC
NC
DQ9
DQ13
DQS1
DM1
VSS
NC
NC
NC
VSS
VSS
VSS
DQ51
DQ55
DQ56
DQ60
VCC
VSS
VSS
NC
DQ32
DQ36
DQ33
DQ37
VCC
VSS
NC
DQ10
DQ14
DQ11
DQ15
VCC
NC
NC
VCC
VCC
DQ57
DQ61
DQS7
DM7
VSS
VCC
VCC
NC
DQS4
DM4
DQ34
DQ38
VSS
VCC
NC
CK0
VCC
NC
NC
VSS
CK0#
VSS
VSS
DQ58
DQ62
DQ59
DQ63
VCC
VSS
VSS
VSS
NC
DQ35
DQ39
DQ40
DQ44
VCC
VSS
VSS
DQ16
DQ20
DQ17
DQ21
VCC
NC
VCC
VCC
VCC
SDA
SA0
VCC
VCC
CKE1
CKE0
NC
DQ41
DQ45
DQS5
DM5
VSS
SCL
VCC
SA1
DQS2
DM2
DQ18
DQ22
VCCSPD
SA2
NC
A12
A11
NC
VSS
NC
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
CS#
CS#
DQS0
DM0
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
DQS4
DM4
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
CS#
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQS1
DM1
DQS5
DM5
UDQS
UDM
UDQS
UDM
UDQS
UDM
UDQS
UDM
DQ8
DQ9
I/O 8
I/O 8
DQ8
DQ9
I/O 8
I/O 8
I/O 9
I/O 9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
DQ10
DQ11
DQ12
DQ13
DQ14
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
CS#
CS#
DQS2
DM2
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
DQS6
DM6
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
CS#
CS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQS3
DM3
DQS7
DM7
UDQS
UDM
UDQS
UDM
UDQS
UDM
UDQS
UDM
DQ8
DQ9
I/O 8
I/O 8
DQ8
DQ9
I/O 8
I/O 8
I/O 9
I/O 9
I/O 9
I/O 9
DQ10
DQ11
DQ12
DQ13
DQ14
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
DQ10
DQ11
DQ12
DQ13
DQ14
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
Clock Wiring
BA0, BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE0: DDR SDRAMs
CKE1: DDR SDRAMs
WE#: DDR SDRAMs
BA0, BA1
A0-A12
RAS#
Clock
Input
SDRAMs
*Clock Net Wiring
CK0/CK0#
CK1/CK1#
CK2/CK2#
4 SDRAMs
4 SDRAMs
NC
DDR SDRAMs
DDR SDRAMs
CAS#
CKE0
CKE1
R = 120 Ohm
WE#
CK0/1/2
CK0/1/2#
Card
Edge
VCCSPD
SPD
SERIAL PD
DDR SDRAMs
DDR SDRAMs
VCC/VCCQ
VREF
DDR SDRAM
DDR SDRAM
DDR SDRAM
SCL
WP
SDA
A0 A1 A2
VSS
SA0 SA1 SA2
NOTES:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown.
NOTE: All resistor values are 22 ohms unless otherwise specified.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
VIN, VOUT
VCC, VCCQ
TSTG
Value
-0.5 ~ 3.6
-0.5 ~ 3.6
-55 ~ +150
0 ~ 70
8
Units
V
Voltage on any pin relative to VSS
Voltage on VCC and VCCQ supply relative to VSS
Storage temperature
V
°C
°C
W
Operating temperature
TA
Power Dissipation
PD
IOS
Short circuit output current
50
mA
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V 0.2V
Parameter
Symbol
VCC
Min
2.3
Max
2.7
Unit
Note
Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)
I/O Supply voltage DDR266/DDR333 (nominal VCC of 2.5V)
I/O Reference voltage
VCCQ
2.3
2.7
V
V
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
0.49*VCCQ
VREF-0.04
VREF+0.15
-0.3
0.51*VCCQ
VREF+0.04
VCCQ+0.30
VREF-0.15
VCCQ+0.30
VCCQ+0.60
VCCQ+0.60
16
1
2
I/O Termination voltage
V
Input logic high voltage
V
Input logic low voltage
V
Input voltage level, CK and CK#
Input differential voltage, CK and CK#
Input crossing point voltage, CK and CK#
-0.3
V
0.3
V
3
0.3
V
Addr, CAS#,
RAS#, WE#
CS#, CKE
CK, CK#
DM
-16
uA
-8
-8
-4
8
8
4
10
—
—
—
—
uA
uA
uA
uA
mA
mA
mA
mA
Input leakage current
II
Output leakage current
IOZ
IOH
IOL
IOH
IOL
-10
-16.8
16.8
-9
Output high current (normal strengh); VOUT = V +0.84V
Output high current (normal strengh); VOUT = VTT -0.84V
Output high current (half strengh); VOUT = VTT +0.45V
Output high current (half strengh); VOUT = VTT -0.45V
9
NOTES:
1.
V
REF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed 2ꢀ of the DC
value
2.
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors,is expected to be set equal to VREF, and must track variations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK#.
CAPACITANCE
VCC = 2.5V, VCCQ =2.5V, TA = 25°C, f = 1MHz
Parameter
Symbol
CIN1
Min
20
12
12
12
12
12
Max
28
Unit
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1)
CIN2
16
Input Capacitance (CS0#, CS1#)
CIN3
16
Input Capacitance (CK0,CK0#, CK1, CK1#)
Input Capacitance (DM0-DM7)
CIN4
16
CIN5
14
Data and DQS input/output capacitance (DQ0-DQ63), CB0-7
COUT
14
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2005
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
AC OPERATING TEST CONDITIONS
Parameter/Condition
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF +0.31
Max
Unit
V
V
V
V
Note
1
1
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Differential Voltage, CK and CK# inputs
Input Crossing Point Voltage, CK and CK# inputs
NOTES:
VREF -0.31
VCCQ+0.6
0.5*VCCQ+0.2
0.7
0.5*VCCQ-0.2
1.
V
IH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
IL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate.
V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
Conditions
Parameter
Symbol
DDR333 @
CL = 2.5 Max
Unit
Operating current
- One bank Active-
Precharge
IDD0*
tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
372
mA
Operating current
IDD1*
One bank open, BL=4, Reads - Refer to the following page for detailed test
condition
512
24
mA
mA
mA
- One bank operation
Percharge power-
down standby current
IDD2P**
IDD2F**
All banks idle; power - down mode; CKE = <VIL(max); tCK = 100Mhz for
DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM
Precharge Floating
standby current
CS# > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ,DQS and DM
240
Active power - down
standby current
IDD3P**
one bank active; power-down mode; CKE=< VIL (max); tCK = 100Mhz for
280
440
mA
mA
DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and
DM
Active standby
current
IDD3N**
CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC
= tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ, DQS and DM inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
Operating current
- burst read
IDD4R*
Burst length = 2; reads; continguous burst; One bank active; address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; 50ꢀ of data changing at every burst; lout = 0mA
812
772
mA
mA
Operating current
- burst write
IDD4W*
Burst length = 2; writes; continuous burst; One bank active address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50ꢀ of
input data changing at every burst
Auto refresh current
IDD5**
IDD6**
IDD7A*
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A &
DDR266B at 133Mhz; distributed refresh
1440
24
mA
mA
mA
Self refresh current;
CKE =< 0.2V
External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B
Orerating current
- Four bank operation
Four bank interleaving with BL=4 -Refer to the following page for detailed test
condition
1412
NOTE:
I
DD specification is based on SAMSUNG components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2005
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
Conditions
Parameter
Symbol
DDR333 @
CL = 2.5 Max
Unit
Operating current
- One bank Active-
Precharge
IDD0*
tRC = tRC(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle; address and control
inputs changing once per clock cycle
288
mA
Operating current
IDD1*
One bank open, BL=4, Reads - Refer to the following page for detailed test
condition
304
32
mA
mA
mA
- One bank operation
Percharge power-
down standby current
IDD2P**
IDD2F**
All banks idle; power - down mode; CKE = <VIL(max); tCK = 100Mhz for
DDR200, 133Mhz for DDR266A & DDR266B; Vin = Vref for DQ,DQS and DM
Precharge Floating
standby current
CS# > = VIH(min);All banks idle; CKE > = VIH(min); tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; Address and other control inputs
changing once per clock cycle; VIN = VREF for DQ,DQS and DM
200
Active power - down
standby current
IDD3P**
one bank active; power-down mode; CKE=< VIL (max); tCK = 100Mhz for
80
mA
mA
DDR200, 133Mhz for DDR266A & DDR266B; VIN = VREF for DQ, DQS and
DM
Active standby
current
IDD3N**
CS# > = VIH(min); CKE> = VIH(min); one bank active; active - precharge; tRC
= tRASmax; tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ, DQS and DM inputs changing twice per clock cycle; address and other
control inputs changing once per clock cycle
312
Operating current
- burst read
IDD4R*
Burst length = 2; reads; continguous burst; One bank active; address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; 50ꢀ of data changing at every burst; lout = 0mA
364
408
mA
mA
Operating current
- burst write
IDD4W*
Burst length = 2; writes; continuous burst; One bank active address and
control inputs changing once per clock cycle; CL = 2 at tCK = 100Mhz for
DDR200, CL = 2 at tCK = 133Mhz for DDR266A, CL = 2.5 at tCK = 133Mhz for
DDR266B ; DQ, DM and DQS inputs changing twice per clock cycle, 50ꢀ of
input data changing at every burst
Auto refresh current
IDD5**
IDD6**
IDD7A*
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A &
DDR266B at 133Mhz; distributed refresh
944
16
mA
mA
mA
Self refresh current;
CKE =< 0.2V
External clock should be on; tCK = 100Mhz for DDR200, 133Mhz for
DDR266A & DDR266B
Orerating current
- Four bank operation
Four bank interleaving with BL=4 -Refer to the following page for detailed test
condition
844
NOTE:
I
DD specification is based on Nanya components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode.
** Value calculated as all module ranks in this operation condition.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2005
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
0°C ≤ TA ≤ 70°C, VCCQ = 2.5V 0.2V, VCC = 2.5V 0.2V
335
Parameter
Symbol
Unit
Min
60
Max
Row Cycle Time
tRC
tRFC
tRAS
tRCD
tRP
ns
ns
ns
ns
ns
ns
ns
tCK
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCK
us
ns
ns
ns
ns
ns
tCK
Refresh row cycle time
72
Row active
42
120K
RAS# to CAS# delay
18
Row precharge time
18
Row active to row active delay
Write recovery time
tRRD
tWR
tWTR
12
15
Last data into Read command
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK#
Output data access time from CK/CK#
Data strobe edge to output data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
1
6
CL=2.5
tCK
12
tCH
0.45
0.55
-0.6
-0.7
-
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.75
0.75
0.7
0.7
-0.7
-0.7
10
0.55
0.55
+0.6
+0.7
0.45
1.1
tCL
tDQSCK
tAC
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tIS
0.6
1.25
DQS falling edge to CK rising-setup time
DQS falling edge to CK rising-hold time
DQS-in high level width
DQS-in low level width
Address and control input setup time (fast)
Address and control input hold time (fast)
Address and control input setup (slow)
Address and control input hold time (slow)
Data-out high impedence time from CK/CK#
Data-out low impedence time from CK/CK#
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & address input pulse width
DQ & DM input pulse width
Exit self refresh o non-Read command
Exit self refresh to Read command
Refresh interval time
tIH
tIS
tIH
tHZ
+0.7
+0.7
tLZ
tMRD
tDS
tDH
0.4
0.4
2.2
1.75
75
tIPW
tDIPW
tXSNR
tXSRD
tREFI
tQH
200
7.8
—
—
0.55
0.6
Output DQS valid window
tHP - tQHS
tCLmin or tCHmin
Clock half period
tHP
Data hold skew factor
tQHS
tWPST
tRAP
tRAL
DQS write postamble
0.4
18
Active Read with Auto precharge command
Auto precharge Write recovery + Precharge time
(tWR/tCK) + (tRP/tCK
)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
ORDERING INFORMATION FOR D4
Part Number
Speed
Height*
WV3EG216M64STSU335D4xG
166MHz/333Mbps, CL=2.5
31.75mm (1.25")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung, N = Nanya & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D4
67.60
(2.661)
3.80
(0.150) MAX.
Full R 2x
63.60
(2.504)
4.00 0.10
(0.158 0.039)
31.75
(1.25)
20
(0.787)
6.0
0.236
1
39
41
199
11.40
4.00
(0.158) MIN.
47.40
(0.449)
2- 1.80
(0.071)
(1.866)
2.15
4.20 (0.165)
(0.085)
2.40 (0.094)
1.0 0.1
(0.04 0.0039)
1.8
(0.071)
2.45
0.60
0.45 0.03
(0.098)
(0.024)
(0.018 0.001)
1.00 0.1
(0.04 0.0039)
0.25
(0.01)
2.55 Min
(0.102 Min)
4.00 0.10
(0.158 0.039)
Tolerances: 0.15 (0.006) unless otherwise specified
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
PART NUMBERING GUIDE
WV 3 E G 216M 64 S T S U xxx D4 x G
WEDC
MEMORY
DDR
GOLD
DEPTH (Daul Rank)
BUS WIDTH
x16
TSOP
2.5V
UNBUFFERED
SPEED (MHz)
PACKAGE 200 PIN
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
(N = Nanya)
G = RoHS COMPLIANT
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG216M64STSU-D4
White Electronic Designs
PRELIMINARY*
Document Title
256MB – 2x16Mx64, DDR SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date Status
Rev 0
Created
8-05
Preliminary
Rev 1
1.1 Added Samsung IDD specs
12-05
Preliminary
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
Rev. 1
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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