WV3EG32M64ETSU-D3 [WEDC]
256MB - 32Mx64 DDR SDRAM UNBUFFERED; 256MB - 32Mx64 DDR SDRAM UNBUFFERED
| 型号： | WV3EG32M64ETSU-D3 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 256MB - 32Mx64 DDR SDRAM UNBUFFERED |
| 文件： | 总12页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED*
256MB – 32Mx64 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Double-data-rate architecture
The WV3EG32M64ETSU is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eight 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin substrate.
PC2700 @ CL 2.5
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply:
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
• VCC = VCCQ = +2.5V 0.2V
ꢀ
184 pin DIMM package
• D3 PCB height: 28.58mm (1.125")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR333 @CL=2.5
166MHz
Clock Speed
CL-tRCD-tRP
2.5-3-3
July 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
A0-A12
Address input (Multiplexed)
Bank Select Address
Data Input/Output
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
BA0-BA1
1
VREF
DQ0
VSS
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
NC
A0
93
94
VSS
DQ4
DQ5
VCCQ
DM0
DQ6
DQ7
VSS
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
VSS
NC
DQ0-DQ63
DQS0-DQS7
CK0, CK1, CK2
2
Data Strobe Input/Output
3
NC
95
A10
Clock Input
4
DQ1
DQS0
DQ2
VCC
DQ3
NC
VSS
96
NC
CK0#, CK1#, CK2# Clock Input
5
NC
BA1
97
VCCQ
NC
VSS
DQ36
DQ37
VCC
DM4
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
NC
DM5
VSS
DQ46
DQ47
NC
CKE0
CS0#
RAS#
CAS#
WE#
Clock Enable input
6
98
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
7
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
99
8
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
NC
VSS
NC
DM0-DM7
VCC
Data-in-mask
Power Supply
Power Supply for DQS
Ground
NC
DQ8
DQ9
DQS1
VCCQ
CK1
CK1#
VSS
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
VCCQ
DQ12
DQ13
DM1
VCC
VCCQ
BA0
VSS
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
VREF
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
VCCSPD
SDA
DQ14
DQ15
NC
VCCQ
NC
DQ20
A12
VSS
DQ21
A11
DM2
VCC
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VCCQ
DM3
A3
DQ30
VSS
DQ31
NC
NC
VCCQ
CK0
CK0#
SCL
Serial clock
SA0-SA2
VCCID
NC
Address in EEPROM
VCC Indentification Flag
No Connect
DQS5
DQ42
DQ43
VCC
NC
DQ48
DQ49
VSS
VCCQ
DQ52
DQ53
NC
CK2#
CK2
VCCQ
DQS6
DQ50
DQ51
VSS
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
VCC
DM6
DQ54
DQ55
VCCQ
NC
DQ25
DQS3
A4
DQ60
DQ61
VSS
VCC
DQ26
DQ27
A2
DM7
DQ62
DQ63
VCCQ
SA0
VSS
A1
NC
SA1
NC
SA2
VCC
VCCSPD
July 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DM0
DQS4
DM4
DM
CS#
DQS
DM
CS#
DQS
DQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS1
DM1
DQS5
DM5
DM
CS#
DQS
DM
CS#
DQS
DQ8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2
DQS6
DM6
DM
CS#
DQS
DM
CS#
DQS
DQ16
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ48
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS3
DM3
DQS7
DM7
DM
CS#
DQS
DM
CS#
DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
RAS#
CAS#
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
BA0-BA1: DDR SDRAMs
WE#: DDR SDRAMs
A0-A12: DDR SDRAMs
CKE0: DDR SDRAMs
SERIAL PD
A1
*Clock Net Wiring
SCL
WP
SDA
BA0-BA1
WE#
DRAM 1
1.5PF
A0
A2
SA0 SA1 SA2
A0-A12
CKE0
R = 120 Ohm
DRAM 3
1.5PF
Card
Edge
VCCSPD
SPD
1.5PF
CLOCK INPUT
VCC/VCCQ
VREF
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DRAM 5
CK0, CK0#
2 SDRAMS
3 SDRAMS
3 SDRAMS
CK1, CK1#
CK2, CK2#
1.5PF
VSS
NOTE: All datalines are terminated through a 22 ohm series resistor.
July 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 to 3.6
V
Voltage on VCC supply relative to VSS
Voltage on VCCQ supply relative to VSS
Storage Temperature
VCC
VCCQ
TSTG
PD
-1.0 to 3.6
-0.5 to 3.6
-55 to +150
8
V
V
°C
W
Power Dissipation
Short Circuit Current
IOS
50
mA
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V 0.2V
Parameter
Symbol
VCC
VCCQ
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
VIX(DC)
II
Min
2.3
2.3
Max
2.7
2.7
Unit
Note
Supply voltage (for device with a nominal VCC of 2.5V)
I/O Supply voltage
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
V
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
mA
VCCQ/2 -50mV VCCQ/2 +50mV
VREF -0.04
1
2
4
4
VREF +0.04
VCCQ +0.3
VREF -0.15
VCCQ +0.3
VCCQ +0.6
1.35
VREF +0.15
-0.3
-0.3
0.36
1.15
-2
Input logic low voltage
Input Voltage Level, CK and CK# inputs
Input Differential Voltage, CK and CK# inputs
Input crossing point voltage, CK and CK# inputs
Input leakage current
3
5
2
5
Output leakage current
IOZ
IOH
IOL
IOH
-5
Output High Current (Normal strengh driver); VOUT = VTT + 0.84V
Output High Current (Normal strengh driver); VOUT = VTT + 0.84V
Output High Current (Half strengh driver); VOUT = VTT + 0.84V
Output High Current (Half strengh driver); VOUT = VTT + 0.84V
Notes:
-16.8
16.8
-9
IOL
9
1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must
accommodate DRAM current spikes on VREF and internal DRAM noise coupled to VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH.
2.
3.
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF
.
V
ID is the magnitude of the difference between the input level on CK and the input level on CK#.
4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative
to a VREF envelop that has been bandwidth limited to 200MHZ.
5. The value of VIX is expected to equal 0.5*VCCQ of the transmitting device and must track variations in the DC level of the same.
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = VCCQ = 2.5V
Parameter
Symbol
CIN1
CIN2
CIN3
CIN4
Min
49
42
42
25
6
Max
57
50
50
30
7
Unit
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)
Input Capacitance (CKE0)
Input Capacitance (CS0#)
Input Capacitance (CLK0, CLK1, CLK2)
Input Capacitance (DM0-DM7)
Data and DQS input/output capacitance (DQ0-DQ63)
CIN5
COUT1
6
7
July 2005
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V 0.2V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
DDR333@
CL = 2.5
Units
Operating one bank active-
precharge current;
IDD0
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data bus inputs
are SWITCHING
720
mA
Operating one bank active-
read-precharge current;
IDD1
IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS
=
920
mA
tRASmin(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address businputs are SWITCHING; Data pattern is same as IDD4W
Precharge power-down
current;
IDD2P
IDD2Q
IDD2F
IDD3P
IDD3N
All banks idle; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
24
mA
mA
mA
mA
mA
Precharge quiet standby
current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address
bus inputsare STABLE; Data bus inputs are FLOATING
160
200
280
440
Precharge standby current;
Active power-down current;
Active standby current;
All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING
All banks open; tCK = tCK(IDD); CKE is LOW; Other control and address bus inputs
are STABLE; Data bus inputs are FLOATING
All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH,
CS - is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Operating burst write current;
Operating burst read current;
IDD4W
IDD4R
IDD5
All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK
=
1280
1280
1360
mA
mA
mA
tCK(IDD), tRAS = tRAS-max(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between
valid commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
= 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDD4W
Burst auto refresh current;
Self refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS
is HIGH between valid commands; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
IDD6
IDD7
CK and CK at 0V; CKE 0.2V; Other control and address bus inputs are
FLOATING; Data bus inputs are FLOATING
24
mA
mA
Operating bank interleave
read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD)-
1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs; Data pattern is same as IDD4R; Refer to the following page for
detailed timing conditions
2240
Note: These specifications apply to modules built with Samsung components only.
July 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
1. Typical Case : VCC=2.5V, T=25°C
2. Worst Case : VCC=2.7V, T=10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3. Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
4. Timing Patterns :
•
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
RCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
t
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
July 2005
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
335
Parameter
Symbol
Unit
Note
Min
60
72
42
18
18
12
15
1
Max
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data into Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Output Slew Rate Matching Ratio(rise to fall)
tRC
tRFC
tRAS
tRCD
tRP
tRRD
tWR
tWTR
tCCD
tCK
ns
ns
ns
ns
ns
ns
ns
tCK
tCK
ns
tCK
tCK
ns
ns
ns
tCK
tCK
tCK
ns
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
70K
1
6
12
tCH
tCL
tDQSCK
tAC
0.45
0.45
-0.6
-0.7
—
0.9
0.4
0.75
0
0.25
0.2
0.2
0.35
0.35
0.9
0.75
0.75
0.8
0.8
0.55
0.55
+0.6
+0.7
0.45
1.1
tDQSQ
tRPRE
tRPST
tDQSS
tWPRES
tWPRE
tDSS
tDSH
tDQSH
tDQSL
tDSC
tIS
tIH
tIS
tIH
tHZ
tLZ
tSLMR
12
3
0.6
1.25
1.1
5.7~9
5.7~9
6~9
6~9
1
+0.7
+0.7
1.5
-0.7
0.67
1
July 2005
Rev. 0
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
B3
Parameter
Symbol
Unit
Note
Min
12
Max
Mode register set cycle time
DQ & DM setup time to DQS
DQ & DM hold time to DQS
Control & Address input pulse width
DQ & DM input pulse width
Power down exit time
Exit self refresh to non-Read command
Exit self refresh to read command
Refresh interval time
Output DQS valid window
Clock half period
Data hold skew factor
DQS write postamble time
tMRD
tDS
tDH
ns
ns
ns
ns
ns
ns
ns
tCK
us
ns
ns
ns
tCK
0.45
0.45
2.2
1.75
6
tIPW
8
8
tDIPW
tPDEX
tXSNR
tXSRD
tREFI
tQH
75
200
7.8
—
—
0.55
0.6
4
11
10, 11
11
tHP-tQHS
tCLmin or tCHmin
tHP
tQHS
tWPST
tRAP
tDAL
0.4
18
(tWR/tCK) +
(tRP/tCK
2
Active to Read with Auto precharge command
Autoprecharge write recovery + Precharge time
tCK
13
)
AC OPERATING TEST CONDITIONS
VCC = 2.5V, VCCQ = 2.5V, 0°C ≤ TA ≤ 70°C
Parameter
Value
0.5 * VCCQ
1.5
Unit
V
Note
Input reference voltage for Clock
Input signal maximum peak swing
Input Levels (VIH/VIL)
V
VREF+0.31/VREF-0.31
VREF
V
Input timing measurement reference level
Output timing measurement reference level
Output load condition
V
VTT
V
See Load Circuit
OUTPUT LOAD CIRCUIT (SSTL_2)
V
TT =0.5*VCCQ
RT=50Ω
Output
Z0=50Ω
VREF
=0.5*VCCQ
C
LOAD=30pF
July 2005
Rev. 0
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
Component Notes
1. tHZ and tLZ transitions occur in the same access
time windows as valid data transitions. these
parameters are not referenced to a specific voltage
level but specify when the device output in no
longer driving (HZ), or begins driving (LZ).
10. Min (tCL, tCH) refers to the smaller of the actual clock
low time and the actual clock high time as provided
to the device (i.e. this value can be greater than the
minimum specification limits for tCL and tCH).....For
example, tCL and tCH are = 50% of the period, less
the half period jitter (tJIT(HP)) of the clock source,
and less the half period jitter due to crosstalk
(tJIT(crosstalk)) into the clock traces.
2. The maximum limit for this parameter is not a
device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.
11. tQH = tHP - tQHS, where:
t
HP = minimum half clock period for any given cycle
3. The specific requirement is that DQS be valid
(HIGH, LOW, or at some point on a valid transition)
on or before this CK edge. A valid transition is
defined as monotonic and meeting the input slew
rate specifications of the device. when no writes
were previously in progress on the bus, DQS will
be tran sitioning from High- Z to logic LOW. If a
previous write was in progress, DQS could be
HIGH, LOW, or transitioning from HIGH to LOW at
and is defined by clock high or clock low (tCH, tCL).
QHS accounts for 1) The pulse duration distortion
t
of on-chip clock circuits; and 2) The worst case
push-out of DQS on one tansition followed by the
worst case pull-in of DQ on the next transition, both
of which are, separately, due to data pin skew and
output pattern effects, and pchannel to n-channel
variation of the output drivers.
this time, depending on tDQSS
.
12. tDQSQ
Consists of data pin skew and output pattern
effects, and p-channel to n-channel variation of the
output drivers for any given cycle.
4. A maximum of eight AUTO REFRESH commands
can be posted to any given DDR SDRAM device.
5. For command/address input slew rate: 1.0 V/ns
13. tDAL = (tWR/tCK) + (tRP/tCK
)
6. For command/address input slew rate: 0.5 V/ns
and 1.0 V/ns
For each of the terms above, if not already an
integer, round to the next highest integer. Example:
For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15
ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5
clocks
7. For CK & CK# slew rate 1.0 V/ns
8. These parameters guarantee device timing, but
they are not necessarily tested on each device.
They may be guaranteed by device design or tester
correlation.
9. Slew Rate is measured between VOH(ac) and VOL(ac)
.
July 2005
Rev. 0
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D3
Part Number
WV3EG32M64ETSU335D3xG
Speed
166MHz/333Mb/s
CAS Latency tRCD
2.5
tRP
3
Height*
28.58 (1.125")
Temperature
0°C to 70°C
3
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be
replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D3
133.35 0.15
(5.25 0.006)
3.30
128.95
(0.130)
(5.077")
MAX
4.00
(0.158 (2x))
28.58 0.15
(1.125 0.006)
17.80
(0.70)
2.30
(0.10)
(2x)
1.27 (0.050)
10.00
2.175
(0.393)
(0.085)
49.53
(1.95)
1.27 0.10
64.77
3.00
(0.118)
(4x)
(0.050 0.004)
(2.550)
1.80
(0.071)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
July 2005
Rev. 0
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 E G 32M 64 E T S U xxx D3 x G
WEDC
MEMORY
DDR
GOLD
DEPTH
BUS WIDTH
x8
TSOP
2.5V
UNBUFFERED
SPEED (MHz)
PACKAGE 184 PIN
COMPONENT VENDOR
NAME
(M = Micron)
(S = Samsung)
G = ROHS COMPLIANT
July 2005
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3EG32M64ETSU-D3
White Electronic Designs
ADVANCED
Document Title
256MB – 32Mx64 DDR SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date Status
Rev 0
Created
7-05
Advanced
July 2005
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
©2020 ICPDF网 联系我们和版权申明