WV3H2256M72AER806D6SG [WEDC]
4GB - 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL; 4GB - 2x256Mx72 DDR2 SDRAM RDIMM ，W / PLL
| 型号： | WV3H2256M72AER806D6SG |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 4GB - 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL |
| 文件： | 总12页 (文件大小：239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED*
4GB – 2x256Mx72 DDR2 SDRAM RDIMM, w/PLL
FEATURES
DESCRIPTION
ꢀ
240-pin, dual in-line memory module (DIMM)
The WV3HG2256M72AER is a 2x256Mx72 Double Data
Rate DDR2 SDRAM high density module based on 1Gb
DDR2 SDRAM components. This memory module consists
of eighteen stacks of 256Mx4 bit with 8 banks DDR2
Synchronous DRAMs in FBGA packages, two - 14 bit
registered buffers in BGApackages mounted on a 240-pin
DIMM FR4 substrate.
ꢀ
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Support ECC error detection and correction
V
V
CC = VCCQ = 1.8V 0.1V
CCSPD = +1.7V to +3.6V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5* and 6*
Adjustable data-output drive strength
On-die termination (ODT)
Serial Presence Detect (SPD) with EEPROM
Auto & self refresh: 64ms 8,192 cycle refresh
Gold edge contacts
RoHS compliant
Dual Rank
Package option
• 240 Pin DIMM
• PCB –30.00mm (1.181") TYP
OPERATING FREQUENCIES
PC2-3200
200MHz
3-3-3
PC2-4300
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
Clock Speed
CL-tRCD-tRP
* Consult factory for availability
April 2006
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
PIN CONFIGURATION
PIN NAMES
Function
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
Pin No.
1
2
3
4
5
6
7
8
Symbol
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
RESET#
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3#
DQS3
VSS
DQ26
DQ27
VSS
Pin No.
61
Symbol
A4
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
VSS
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
VCCQ
A3
A1
VCC
CK0
CK0#
VCC
A0
VCC
Pin Name
A0-A13
BA0,BA2
DQ0-DQ63
CB0-CB7
DQS0-DQS17
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
VCCQ
A2
VCC
VSS
VSS
VCC
NC
VCC
A10/AP
BA0
DQ4
DQ5
VSS
DM0/DQS9
NC/DQS9#
VSS
DQ6
DQ7
Data strobes
DQS0#-DQS17# Data strobes complement
9
DM0-DM8
ODT0, ODT1
CK0,CK0#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
RESET#
SA0-SA2
SDA
Data Masks
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
VSS
BA1
VCCQ
On-die termination control
Clock Inputs, positive line
Clock Enables
DQ12
DQ13
VSS
DM1/DQS10
NC/DQS10#
VSS
VCCQ
WE#
CAS#
VCCQ
CS1#
ODT1
VCCQ
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5#
DQS5
VSS
DQ42
DQ43
VSS
RAS#
CS0#
VCCQ
ODT0
A13
Chip Selects
Row Address Strobe
Column Address Strobe
Write Enable
Register Reset Input
SPD address
SPD Data Input/Output
SPD Clock Input
Core Power
I/O Power
Ground
Power Supply for Reference
SPD Power supply
No connect
NC
NC
VSS
VCC
VSS
DQ36
DQ37
VSS
DM4/DQS13
NC/DQS13#
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5/DQS14
NC/DQS14#
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2/DQS11
NC/DQS11#
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3/DQS12
NC/DQS12#
VSS
DQ30
DQ31
VSS
CB4
CB5
VSS
DM8DQS17
NC/DQS17#
VSS
CB6
CB7
VSS
VCCQ
CKE1
VCC
NC
NC
VCCQ
A12
A9
SCL
VCC
VCCQ
VSS
VREF
VCCSPD
NC
94
95
96
97
98
99
DQ48
DQ49
VSS
SA2
NC
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
NC
NC
VSS
CB0
CB1
VSS
DQS8#
DQS8
VSS
CB2
CB3
VSS
DM6/DQS15
NC/DQS15#
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7/DQS16
NC/DQS16#
VSS
DQ62
DQ63
VSS
VCCSPD
SA0
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7#
DQS7
VSS
DQ58
DQ59
VSS
SDA
SCL
VSS
VCCQ
CKE0
VCC
BA2
NC
VCCQ
A11
A7
VCC
A5
VCC
A8
A6
SA1
April 2006
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
FUNCTIONAL BLOCK DIAGRAM
VSS
RCS1#
RCS0#
DQS0
DQS0#
DM0/DQS9
NC/DQS9#
DM
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
DQ0
DQ4
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
I/O 1
I/O 2
I/O 3
I/O 1
I/O 2
I/O 3
DQS1
DQS1#
DM1/DQS10
NC/DQS10#
DM
DM
DM
DM
DQ8
DQ12
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ9
DQ13
DQ14
DQ15
DQ10
DQ11
DQS2
DQS2#
DM2/DQS11
NC/DQS11#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQ16
DQ20
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ17
DQ18
DQ19
DQ21
DQ22
DQ23
DQS3
DQS3#
DM3/DQS12
NC/DQS12#
DM
DM
DM
DM
DQ24
DQ28
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ25
DQ26
DQ27
DQ29
DQ30
DQ31
DQS4
DQS4#
DM4/DQS13
NC/DQS13#
DM
DM
DM
DM
DQ32
DQ36
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ33
DQ34
DQ35
DQ37
DQ38
DQ39
DQS5
DQS5#
DM5/DQS14
NC/DQS14#
DM
DM
DM
DM
DQ40
DQ44
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ41
DQ42
DQ43
DQ45
DQ46
DQ47
DQS6
DQS6#
DM6/DQS15
NC/DQS15#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DM
CS# DQS DQS#
CS# DQS DQS#
CS# DQS DQS#
DQ48
DQ52
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ49
DQ50
DQ51
DQ53
DQ54
DQ55
DQS#7
DQS7#
DM7/DQS16
NC/DQS16#
DM
DM
DM
DM
DQ56
DQ60
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ57
DQ58
DQ59
DQ61
DQ62
DQ63
DQS8
DQS8#
DM8/DQS17
NC/DQS17#
DM
DM
DM
DM
CB0
CB4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB1
CB2
CB3
CB5
CB6
CB7
VCCSPD
VCC/VCCQ
VREF
Serial PD
CS0#
CS1#
BA0-BA2
A0-A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
RCS0# CS# : DDR2 SDRAMs
RCS1# CS# : DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
1:2
RBA0-RBA2
RA0-RA13
BA0-BA2 : DDR2 SDRAMs
A0-A13 : DDR2 SDRAMs
R
E
G
I
S
T
E
R
RRAS#
RCAS#
RWE#
RCKE0
RCKE1
RODT0
RODT1
RAS# : DDR2 SDRAMs
CAS# : DDR2 SDRAMs
WE# : DDR2 SDRAMs
CKE : DDR2 SDRAMs
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
ODT : DDR2 SDRAMs
VSS
Serial PD
SCL
SDA
WP A0 A1 A2
SA0 SA1 SA2
PCK0-PCK6, PCK8, PCK9
RST#
RESET#**
CK0
CK : DDR2 SDRAMs
CK# : DDR2 SDRAMs
P
L
L
PCK7**
PCK7#**
PCK0#-PCK6#, PCK8#, PCK9#
CK0#
PCK7
PCK7#
CK : Register
CK# : Register
OE
RESET#**
NOTE: All resistor values are 22 ohms unless otherwise specified.
** RESET#, PCK7 and PCK7# connect to both registers. Other signals connect to one of two registers.
April 2006
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
RECOMMENDED DC OPERATING CONDITIONS
All Voltages Referenced to VSS
Rating
Parameter
Symbol
VCC
Min.
1.7
Type
1.8
Max.
1.9
Units
Notes
Supply Voltage
V
V
V
V
3
1
2
I/O Input Reference Voltage
I/O Termination Voltage
SPD Supply Voltage
Notes:
VREF
0.49*VCC
VREF-0.04
1.7
0.50*VCC
VREF
0.51*VCC
VREF+0.04
3.6
VTT
VCCSPD
—
1. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed 2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor..
2.
3.
V
TT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF
.
V
CCQ of all IC's are tied to VCC
.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
VCC Voltage on VCC pin relative to VSS
VIN, VOUT Voltage on any pin relative to VSS
TSTG Storage Temperature
Min
-0.5
-0.5
-55
Max
2.3
Units
V
2.3
V
100
°C
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
CK, CK#
DM
Input leakage current; Any input 0V<VIN<VCC; VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
IL
-10
10
µA
IOZ
Output leakage current; 0V<VOUT<VCCQ; DQs and ODT are disable
VREF leakage current; VREF = Valid VREF level
DQ, DQS, DQS#
-10
-72
10
72
µA
µA
IVREF
CAPACITANCE
TA = 25°C, f = 100MHz, VCC = 1.8V
Parameter
Symbol
Min
10
10
10
10
9
Max
12
12
12
11
Units
Input Capacitance: (A0 ~ A13, BA0 ~ BA2, RAS#, CAS#, WE#)
Input Capacitance: (CKE0, CKE1), (ODT0, ODT1)
Input Capacitance: (CS0#, CS1#)
CIN1
CIN2
pF
pF
pF
pF
pF
pF
pF
pF
CIN3
Input Capacitance: (CK0, CK0#)
CIN4
CIN5 (665)
CIN5 (534, 403)
COUT1 (665)
COUT1 (534, 403)
11
Input Capacitance: (DM0 ~ DM8), (DQS0 ~ DQ17)
9
12
11
9
Input/Output Capacitance: (DQ0 ~ DQ63), (CB0 ~ CB7)
9
12
April 2006
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating temperature (commercial)
Notes:
TOPER
0 to +85°C
°C
1, 2
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDED JESD51.2
2. At 0°C to +85°C, operation temperature range, all DRAM specification will be supported.
INPUT DC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(DC)
VIL(DC)
Min
Max
Units
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
VREF + 0.125
-0.300
VCC + 0.300
VREF - 0.125
V
V
INPUT AC LOGIC LEVEL
All voltages referenced to VSS
Parameter
Symbol
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
Min
Max
Units
AC Input High (Logic 1) Voltage DDR2-400 & DDR-533
AC Input High ( Logic 1) Voltage DDR2-667*
AC Input Low (Logic 0) Voltage DDR2-400 & DDR2-533
AC Input Low (Logic 0) Voltage DDR2-667*
* Consult factory for availability
VREF + 0.250
-
V
V
V
V
VREF + 0.200
-
-
-
VREF - 0.250
VREF - 0.200
April 2006
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
DDR2 ICC SPECIFICATIONS AND CONDITIONS
VCC = +1.8V 0.1V
Symbol Proposed Conditions
Operating one bank active-precharge current;
ICC0* tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
806
665
534
403
Units
2,336 2,246 2,156
mA
TBD
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD
=
ICC1*
2,516 2,426 2,336
mA
TBD
tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as ICC4W
Precharge power-down current;
ICC2P** All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
932
932
932
mA
mA
mA
TBD
TBD
TBD
Precharge quiet standby current;
ICC2Q** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
1,940 1,760 1,760
Precharge standby current;
ICC2N** All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
2,120 1,940 1,940
1,580 1,400 1,400
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
mA
mA
TBD
TBD
ICC3P**
Slow PDN Exit MRS(12) = 1
932
932
932
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
ICC3N**
2,300 2,120 2,120
3,056 2,876 2,516
mA
mA
TBD
TBD
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
=
ICC4W*
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
=
ICC4R*
3,056 2,876 2,516
8,420 8,240 8,060
mA
mA
mA
TBD
TBD
TBD
Burst auto refresh current;
ICC5B** tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus
ICC6**
Normal
360
360
360
inputs
are FLOATING; Data bus inputs are FLOATING
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
ICC7* tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the
following page for detailed timing conditions
6,116 5,756 5,396
mA
TBD
Note:
CC specs are based on SAMSUNG components. Other DRAM manufacturers parameters may be different.
* Value calculated as one module rank in this operation condition, and all other module ranks in ICC2P (CKE LOW) mode.
I
April 2006
Rev. 1
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WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS
VCC = +1.8V 0.1V
AC Characteristics
Parameter
806
665
534
403
Symbol
tCK (6)
tCK (5)
tCK (4)
tCK (3)
tCH
Min
TBD
TBD
TBD
TBD
TBD
TBD
Max
TBD
TBD
TBD
TBD
TBD
TBD
Min
Max
Min
Max
Min
Max
Unit
ps
CL = 6
CL = 5
CL = 4
CL = 3
3,000
3,750
5,000
0.45
8,000
8,000
8,000
0.55
ps
Clock cycle time
3,750
5,000
0.45
8,000
8,000
0.55
5,000
5,000
0.45
8,000
8,000
0.55
ps
ps
CK high-level width
CK low-level width
tCK
tCK
tCL
0.45
0.55
0.45
0.55
0.45
0.55
MIN
MIN
MIN
Half clock period
tHP
(tCH
,
(tCH
,
(tCH
,
ps
TBD
TBD
tCL
)
tCL
)
tCL)
Clock jitter
tJIT
tAC
tHZ
-125
-450
125
+450
tAC
-125
-500
125
+500
tAC
-125
-600
125
+600
tAC
ps
ps
TBD
TBD
DQ output access time from CK/CK#
TBD
TBD
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
ps
ps
TBD
TBD
(
(
(
MAX)
MAX)
MAX)
tAC
tAC
tAC
tAC
tAC
tAC
tLZ
tDS
tDH
TBD
(MIN)
(MAX)
(MIN)
(MAX)
(MIN)
(MAX)
DQ and DM input setup time relative to DQS
DQ and DM input hold time relative to DQS
100
175
100
225
150
275
tCK
ps
TBD
TBD
TBD
TBD
DQ…DQS hold, DQS to first DQ to go nonvalid,
per access relative to DQS
tDIPW
tQHS
tQH
0.35
0.35
0.35
ps
TBD
TBD
TBD
TBD
TBD
TBD
Data hold skew factor
340
400
450
DQ–DQS hold, DQS to first DQ to go nonvalid,
per access
tHP-
tHP-
tHP-
tQHS
tQHS
tQHS
tQH-
tQH-
tQH-
Data valid output window (DVW)
tDVW
TBD
TBD
tDQSQ
0.35
0.35
-400
tDQSQ
0.35
0.35
-450
tDQSQ
0.35
0.35
-500
DQS input high pulse width
tDQSH
tDQSL
tCK
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
DQS input low pulse width
DQS output access time from CK/CK#
tDQSCK
+400
+450
+500
DQS falling edge to CK rising– setup time
DQS falling edge from CK rising – hold time
tDSS
tDSH
tDQSQ
tRPRE
0.2
0.2
0.2
0.2
0.2
0.2
tCK
tCK
TBD
TBD
TBD
TBD
DQS–DQ skew, DQS to last DQ valid, per group,
per access
240
1.1
300
1.1
350
1.1
ps
TBD
TBD
TBD
TBD
DQS read preamble
0.9
0.9
0.9
tCK
Note:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
April 2006
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (Continued)
VCC = +1.8V 0.1V
AC Characteristics
Parameter
806
665
534
403
Symbol
tRPST
Min
Max
TBD
TBD
TBD
TBD
Min
Max
Min
0.4
0
Max
Min
0.4
0
Max
Unit
tCK
ps
DQS read preamble
0.4
0
0.6
0.6
0.6
TBD
TBD
TBD
TBD
DQS write preamble setup time
DQS write preamble
tWPRES
tWPRE
0.35
0.4
0.35
0.4
0.35
0.4
tCK
tCK
tCK
DQS write postamble
tWPST
0.6
0.6
0.6
Write command to first DQS latching
transition
WL-0.25 WL+0.25 WL-0.25 WL+0.25 WL-0.25 WL+0.25
tDQSS
tIPW
TBD
TBD
TBD
TBD
Address and control input pulse width
for each input
0.6
0.6
0.6
tCK
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
tISa
tIHa
tCCD
tRC
200
275
2
250
375
2
350
475
2
ps
ps
tCK
ns
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Active to Active (same bank) command
54
55
55
Active bank a to Active b bank
command
tRRD
7.5
7.5
7.5
ns
TBD
TBD
Active to Read or Write delay
Four Bank Activate period
Active to precharge command
tRCD
tFAW
tRAS
15
37.5
39
15
37.5
40
15
37.5
40
ns
ns
ns
TBD
TBD
TBD
TBD
TBD
TBD
37.5
37.5
37.5
70,000
70,000
70,000
Internal Read to precharge command
delay
tRTP
tWR
tDAL
7.5
15
7.5
15
7.5
15
ns
ns
ns
TBD
TBD
TBD
TBD
TBD
TBD
Write recovery time
Auto precharge write recovery and
precharge time
tWR+tRP
tWR+tRP
tWR+tRP
Interval Write to Read command delay
Precharge command period
tWTR
tRP
tRPA
tMRD
7.5
15
7.5
15
10
15
ns
ns
ns
tCK
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Precharge All command period
Load Mode command cycle time
tRP+tCK
2
tRP+tCK
2
tRP+tCK
2
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
CKE low to CK,CK# uncertainty
tDELAY
ns
TBD
TBD
Note:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
Continued on next page
April 2006
Rev. 1
8
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WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
AC TIMING PARAMETERS (Continued)
VCC = +1.8V 0.1V
AC Characteristics
Parameter
806
665
534
403
Symbol
tRFC
Min
Max
TBD
TBD
TBD
Min
Max
70,000
7.8
Min
Max
70,000
7.8
Min
Max
70,000
7.8
Unit
ns
Refresh to Active or Refresh to Refresh
command interval
127.5
127.5
127.5
TBD
TBD
TBD
Average periodic refresh interval
tREFI
µs
ns
tRFC
tRFC
tRFC
Exit self refresh to non-read command
tXSNR
(MIN)+10
(MIN)+10
(MIN)+10
Exit self refresh to read command
Exit self refresh timing reference
ODT turn-on delay
tXSRD
tISXR
200
tIS
200
tIS
200
tIS
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
tAOND
2
2
2
2
2
2
tCK
tAC(MAX)
+1,000
tAC(MAX)
+1,000
tAC(MAX)
+1,000
ODT turn-on
tAON
tAOFD
tAOF
tAC(MIN)
2.5
tAC(MIN)
2.5
tAC(MIN)
2.5
ps
tCK
ps
TBD
TBD
TBD
TBD
TBD
TBD
ODT turn-off delay
ODT turn-off
2.5
2.5
2.5
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MAX)
+600
tAC(MIN)
tAC(MIN)
tAC(MIN)
2x tCK
+
2x tCK
+
2x tCK +
tAC(MIN)
+2,000
tAC(MIN)
+2,000
tAC(MIN)
+2,000
tAC (MAX)
+ 1,000
tAC (MAX)
+ 1,000
tAC (MAX)
+ 1,000
ODT turn-on (power-down mode)
ODT turn-off (power-down mode)
tAONPD
ps
TBD
TBD
TBD
TBD
2.5x tCK
+ tAC
2.5x tCK
+ tAC
2.5x tCK
+ tAC
tAC(MIN)
+2,000
tAC(MIN)
+2,000
tAC(MIN)
+2,000
tAOFPD
tCK
+
+
+
(MAX)
1,000
(MAX)
1,000
(MAX)
1,000
ODT to power-down entry latency
ODT power-down exit latency
tANPD
tAXPD
3
8
3
8
3
8
tCK
tCK
tCK
TBD
TBD
TBD
TBD
Exit active power-down to READ
command, MR[bit12=0]
tXARD
2
2
2
TBD
TBD
TBD
TBD
Exit active power-down to READ
command, MR[bit12=1]
tXARDS
7-AL
6-AL
6-AL
tCK
Exit precharge power-down to any non-
READ command.
tXP
2
3
2
3
2
3
tCK
tCK
TBD
TBD
TBD
TBD
CKE minimum high/low time
tCKE
Note:
• AC specification is based on SAMSUNG components. Other DRAM manufactures specification may be different.
April 2006
Rev. 1
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WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
ORDERING INFORMATION FOR D6
Part Number
Speed/Data Rate
400MHz/800Mb/s
333MHz/667Mb/s
266MHz/533Mb/s
200MHz/400Mb/s
CAS Latency
tRCD
6
5
4
3
tRP
6
5
4
3
Height*
W3HG2256M72ACER806D6xxG**
W3HG2256M72ACER665D6xxG**
W3HG2256M72ACER534D6xxG
W3HG2256M72ACER403D6xxG
6
5
4
3
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
30.00mm (1.181") TYP
** Contact factory for availability
Notes:
• RoHS compliant product. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory component source control. The place holder for this is shown as a lower case "x"
in the part numbers above and is to be replaced with respective vendors code. Consult factory for qualified sourcing options.
(M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D6
FRONT VIEW
133.50 (5.256)
133.20 (5.244)
3.00 (0.118)
(4X)
4.00 (0.158)
(4X)
30.50 (1.201)
29.851 (1.175)
17.80 (0.700)
TYP.
0.270 (6.73)
MAX
PIN 1
5.175 (0.204)
(2X)
10.00 (0.394)
TYP.
1.0 (0.039)
TYP.
0.80 (0.032)
TYP.
1.50 (0.059)
PIN 120
4.843 (123.0)
TYP.
BACK VIEW
1.37 (0.054)
1.17 (0.046)
PIN 121
PIN 240
5.0 (0.197) TYP.
63.0 (2.480)
TYP.
55.0 (2.165)
TYP.
Detail B
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
April 2006
Rev. 1
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WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
PART NUMBERING GUIDE
WV 3 H G 2 256M 72 A E R xxx D6 x x G
WEDC
MEMORY (SDRAM)
DDR 2
GOLD
DUAL RANK
DEPTH
BUS WIDTH
COMPONENT WIDTH x4
1.8V
REGISTERED
SPEED (Mb/s)
PACKAGE 240 PIN DIMM
INDUSTRIAL TEMP OPTION
(For commercial leave "blank"
for industrial add "I")
COMPONENT VENDOR NAME
(M = Micron)
(S = Samsung)
G = RoHS COMPLIANT
April 2006
Rev. 1
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WV3HG2256M72AER-D6
White Electronic Designs
ADVANCED
Document Title
4GB – 2x256Mx72 DDR2 SDRAM REGISTERED, w/PLL
DRAM DIE OPTIONS:
• SAMSUNG: A-Die, will move to B-Die Q1'07
• MICRON: U28A: A-Die, will move to U38Z: D-Die Q4'06
Revision History
Rev #
History
Release Date Status
Rev 0
Evaluation and review
March 2006
Concept
Rev 1
April 2006
Advanced
1.0 Update VCC specifications
1.1 Moved from concept to advanced
1.2 Added DRAM die verification
April 2006
Rev. 1
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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